MOESI_CMP_directory.py revision 11065
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Brad Beckmann 29 30import math 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from Ruby import create_topology 35from Ruby import send_evicts 36 37# 38# Declare caches used by the protocol 39# 40class L1Cache(RubyCache): pass 41class L2Cache(RubyCache): pass 42 43def define_options(parser): 44 return 45 46def create_system(options, full_system, system, dma_ports, ruby_system): 47 48 if buildEnv['PROTOCOL'] != 'MOESI_CMP_directory': 49 panic("This script requires the MOESI_CMP_directory protocol to be built.") 50 51 cpu_sequencers = [] 52 53 # 54 # The ruby network creation expects the list of nodes in the system to be 55 # consistent with the NetDest list. Therefore the l1 controller nodes must be 56 # listed before the directory nodes and directory nodes before dma nodes, etc. 57 # 58 l1_cntrl_nodes = [] 59 l2_cntrl_nodes = [] 60 dir_cntrl_nodes = [] 61 dma_cntrl_nodes = [] 62 63 # 64 # Must create the individual controllers before the network to ensure the 65 # controller constructors are called before the network constructor 66 # 67 l2_bits = int(math.log(options.num_l2caches, 2)) 68 block_size_bits = int(math.log(options.cacheline_size, 2)) 69 70 for i in xrange(options.num_cpus): 71 # 72 # First create the Ruby objects associated with this cpu 73 # 74 l1i_cache = L1Cache(size = options.l1i_size, 75 assoc = options.l1i_assoc, 76 start_index_bit = block_size_bits, 77 is_icache = True) 78 l1d_cache = L1Cache(size = options.l1d_size, 79 assoc = options.l1d_assoc, 80 start_index_bit = block_size_bits, 81 is_icache = False) 82 83 l1_cntrl = L1Cache_Controller(version = i, 84 L1Icache = l1i_cache, 85 L1Dcache = l1d_cache, 86 l2_select_num_bits = l2_bits, 87 send_evictions = send_evicts(options), 88 transitions_per_cycle = options.ports, 89 clk_domain=system.cpu[i].clk_domain, 90 ruby_system = ruby_system) 91 92 cpu_seq = RubySequencer(version = i, 93 icache = l1i_cache, 94 dcache = l1d_cache, 95 clk_domain=system.cpu[i].clk_domain, 96 ruby_system = ruby_system) 97 98 l1_cntrl.sequencer = cpu_seq 99 exec("ruby_system.l1_cntrl%d = l1_cntrl" % i) 100 101 # Add controllers and sequencers to the appropriate lists 102 cpu_sequencers.append(cpu_seq) 103 l1_cntrl_nodes.append(l1_cntrl) 104 105 # Connect the L1 controllers and the network 106 l1_cntrl.mandatoryQueue = MessageBuffer() 107 l1_cntrl.requestFromL1Cache = MessageBuffer() 108 l1_cntrl.requestFromL1Cache.master = ruby_system.network.slave 109 l1_cntrl.responseFromL1Cache = MessageBuffer() 110 l1_cntrl.responseFromL1Cache.master = ruby_system.network.slave 111 l1_cntrl.requestToL1Cache = MessageBuffer() 112 l1_cntrl.requestToL1Cache.slave = ruby_system.network.master 113 l1_cntrl.responseToL1Cache = MessageBuffer() 114 l1_cntrl.responseToL1Cache.slave = ruby_system.network.master 115 l1_cntrl.triggerQueue = MessageBuffer(ordered = True) 116 117 118 l2_index_start = block_size_bits + l2_bits 119 120 for i in xrange(options.num_l2caches): 121 # 122 # First create the Ruby objects associated with this cpu 123 # 124 l2_cache = L2Cache(size = options.l2_size, 125 assoc = options.l2_assoc, 126 start_index_bit = l2_index_start) 127 128 l2_cntrl = L2Cache_Controller(version = i, 129 L2cache = l2_cache, 130 transitions_per_cycle = options.ports, 131 ruby_system = ruby_system) 132 133 exec("ruby_system.l2_cntrl%d = l2_cntrl" % i) 134 l2_cntrl_nodes.append(l2_cntrl) 135 136 # Connect the L2 controllers and the network 137 l2_cntrl.GlobalRequestFromL2Cache = MessageBuffer() 138 l2_cntrl.GlobalRequestFromL2Cache.master = ruby_system.network.slave 139 l2_cntrl.L1RequestFromL2Cache = MessageBuffer() 140 l2_cntrl.L1RequestFromL2Cache.master = ruby_system.network.slave 141 l2_cntrl.responseFromL2Cache = MessageBuffer() 142 l2_cntrl.responseFromL2Cache.master = ruby_system.network.slave 143 144 l2_cntrl.GlobalRequestToL2Cache = MessageBuffer() 145 l2_cntrl.GlobalRequestToL2Cache.slave = ruby_system.network.master 146 l2_cntrl.L1RequestToL2Cache = MessageBuffer() 147 l2_cntrl.L1RequestToL2Cache.slave = ruby_system.network.master 148 l2_cntrl.responseToL2Cache = MessageBuffer() 149 l2_cntrl.responseToL2Cache.slave = ruby_system.network.master 150 l2_cntrl.triggerQueue = MessageBuffer(ordered = True) 151 152 153 phys_mem_size = sum(map(lambda r: r.size(), system.mem_ranges)) 154 assert(phys_mem_size % options.num_dirs == 0) 155 mem_module_size = phys_mem_size / options.num_dirs 156 157 158 # Run each of the ruby memory controllers at a ratio of the frequency of 159 # the ruby system. 160 # clk_divider value is a fix to pass regression. 161 ruby_system.memctrl_clk_domain = DerivedClockDomain( 162 clk_domain=ruby_system.clk_domain, 163 clk_divider=3) 164 165 for i in xrange(options.num_dirs): 166 dir_size = MemorySize('0B') 167 dir_size.value = mem_module_size 168 169 dir_cntrl = Directory_Controller(version = i, 170 directory = RubyDirectoryMemory( 171 version = i, size = dir_size), 172 transitions_per_cycle = options.ports, 173 ruby_system = ruby_system) 174 175 exec("ruby_system.dir_cntrl%d = dir_cntrl" % i) 176 dir_cntrl_nodes.append(dir_cntrl) 177 178 # Connect the directory controllers and the network 179 dir_cntrl.requestToDir = MessageBuffer() 180 dir_cntrl.requestToDir.slave = ruby_system.network.master 181 dir_cntrl.responseToDir = MessageBuffer() 182 dir_cntrl.responseToDir.slave = ruby_system.network.master 183 dir_cntrl.responseFromDir = MessageBuffer() 184 dir_cntrl.responseFromDir.master = ruby_system.network.slave 185 dir_cntrl.forwardFromDir = MessageBuffer() 186 dir_cntrl.forwardFromDir.master = ruby_system.network.slave 187 dir_cntrl.responseFromMemory = MessageBuffer() 188 189 190 for i, dma_port in enumerate(dma_ports): 191 # 192 # Create the Ruby objects associated with the dma controller 193 # 194 dma_seq = DMASequencer(version = i, 195 ruby_system = ruby_system, 196 slave = dma_port) 197 198 dma_cntrl = DMA_Controller(version = i, 199 dma_sequencer = dma_seq, 200 transitions_per_cycle = options.ports, 201 ruby_system = ruby_system) 202 203 exec("ruby_system.dma_cntrl%d = dma_cntrl" % i) 204 dma_cntrl_nodes.append(dma_cntrl) 205 206 # Connect the dma controller to the network 207 dma_cntrl.mandatoryQueue = MessageBuffer() 208 dma_cntrl.responseFromDir = MessageBuffer() 209 dma_cntrl.responseFromDir.slave = ruby_system.network.master 210 dma_cntrl.reqToDir = MessageBuffer() 211 dma_cntrl.reqToDir.master = ruby_system.network.slave 212 dma_cntrl.respToDir = MessageBuffer() 213 dma_cntrl.respToDir.master = ruby_system.network.slave 214 dma_cntrl.triggerQueue = MessageBuffer(ordered = True) 215 216 217 all_cntrls = l1_cntrl_nodes + \ 218 l2_cntrl_nodes + \ 219 dir_cntrl_nodes + \ 220 dma_cntrl_nodes 221 222 # Create the io controller and the sequencer 223 if full_system: 224 io_seq = DMASequencer(version=len(dma_ports), ruby_system=ruby_system) 225 ruby_system._io_port = io_seq 226 io_controller = DMA_Controller(version = len(dma_ports), 227 dma_sequencer = io_seq, 228 ruby_system = ruby_system) 229 ruby_system.io_controller = io_controller 230 231 # Connect the dma controller to the network 232 io_controller.mandatoryQueue = MessageBuffer() 233 io_controller.responseFromDir = MessageBuffer() 234 io_controller.responseFromDir.slave = ruby_system.network.master 235 io_controller.reqToDir = MessageBuffer() 236 io_controller.reqToDir.master = ruby_system.network.slave 237 io_controller.respToDir = MessageBuffer() 238 io_controller.respToDir.master = ruby_system.network.slave 239 io_controller.triggerQueue = MessageBuffer(ordered = True) 240 241 all_cntrls = all_cntrls + [io_controller] 242 243 244 ruby_system.network.number_of_virtual_networks = 3 245 topology = create_topology(all_cntrls, options) 246 return (cpu_sequencers, dir_cntrl_nodes, topology) 247