msi_caches.py revision 13774
16899SN/A# -*- coding: utf-8 -*- 28851Sandreas.hansson@arm.com# Copyright (c) 2017 Jason Power 38851Sandreas.hansson@arm.com# All rights reserved. 48851Sandreas.hansson@arm.com# 58851Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 68851Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 78851Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 88851Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 98851Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 108851Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 118851Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 128851Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 138851Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 146899SN/A# this software without specific prior written permission. 157553SN/A# 166899SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176899SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186899SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196899SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206899SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216899SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226899SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236899SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246899SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256899SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266899SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276899SN/A# 286899SN/A# Authors: Jason Power 296899SN/A 306899SN/A""" This file creates a set of Ruby caches, the Ruby network, and a simple 316899SN/Apoint-to-point topology. 326899SN/ASee Part 3 in the Learning gem5 book: learning.gem5.org/book/part3 336899SN/A 346899SN/AIMPORTANT: If you modify this file, it's likely that the Learning gem5 book 356899SN/A also needs to be updated. For now, email Jason <jason@lowepower.com> 366899SN/A 376899SN/A""" 386899SN/A 396899SN/Afrom __future__ import print_function 406899SN/Afrom __future__ import absolute_import 416899SN/A 4211793Sbrandon.potter@amd.comimport math 4311793Sbrandon.potter@amd.com 4411800Sbrandon.potter@amd.comfrom m5.defines import buildEnv 457632SBrad.Beckmann@amd.comfrom m5.util import fatal, panic 468232Snate@binkert.org 476899SN/Afrom m5.objects import * 486899SN/A 497553SN/Aclass MyCacheSystem(RubySystem): 5012129Sspwilson2@wisc.edu 5112129Sspwilson2@wisc.edu def __init__(self): 5212129Sspwilson2@wisc.edu if buildEnv['PROTOCOL'] != 'MSI': 537553SN/A fatal("This system assumes MSI from learning gem5!") 547553SN/A 556899SN/A super(MyCacheSystem, self).__init__() 567553SN/A 576899SN/A def setup(self, system, cpus, mem_ctrls): 588851Sandreas.hansson@arm.com """Set up the Ruby cache subsystem. Note: This can't be done in the 598851Sandreas.hansson@arm.com constructor because many of these items require a pointer to the 608851Sandreas.hansson@arm.com ruby system (self). This causes infinite recursion in initialize() 618851Sandreas.hansson@arm.com if we do this in the __init__. 628851Sandreas.hansson@arm.com """ 638851Sandreas.hansson@arm.com # Ruby's global network. 647053SN/A self.network = MyNetwork(self) 657553SN/A 666899SN/A # MSI uses 3 virtual networks. One for requests (lowest priority), one 676899SN/A # for responses (highest priority), and one for "forwards" or 687553SN/A # cache-to-cache requests. See *.sm files for details. 696899SN/A self.number_of_virtual_networks = 3 707053SN/A self.network.number_of_virtual_networks = 3 717053SN/A 726899SN/A # There is a single global list of all of the controllers to make it 736899SN/A # easier to connect everything to the global network. This can be 747053SN/A # customized depending on the topology/network requirements. 757553SN/A # Create one controller for each L1 cache (and the cache mem obj.) 766899SN/A # Create a single directory controller (Really the memory cntrl) 777053SN/A self.controllers = \ 787553SN/A [L1Cache(system, self, cpu) for cpu in cpus] + \ 796899SN/A [DirController(self, system.mem_ranges, mem_ctrls)] 806899SN/A 8113784Sgabeblack@google.com # Create one sequencer per CPU. In many systems this is more 8213784Sgabeblack@google.com # complicated since you have to create sequencers for DMA controllers 836899SN/A # and other controllers, too. 846899SN/A self.sequencers = [RubySequencer(version = i, 858922Swilliam.wang@arm.com # I/D cache is combined and grab from ctrl 8613784Sgabeblack@google.com icache = self.controllers[i].cacheMemory, 878922Swilliam.wang@arm.com dcache = self.controllers[i].cacheMemory, 888922Swilliam.wang@arm.com clk_domain = self.controllers[i].clk_domain, 8913784Sgabeblack@google.com ) for i in range(len(cpus))] 908922Swilliam.wang@arm.com 918922Swilliam.wang@arm.com # We know that we put the controllers in an order such that the first 928922Swilliam.wang@arm.com # N of them are the L1 caches which need a sequencer pointer 936899SN/A for i,c in enumerate(self.controllers[0:len(self.sequencers)]): 946899SN/A c.sequencer = self.sequencers[i] 956899SN/A 966899SN/A self.num_of_sequencers = len(self.sequencers) 978975Sandreas.hansson@arm.com 986899SN/A # Create the network and connect the controllers. 998965Sandreas.hansson@arm.com # NOTE: This is quite different if using Garnet! 10011320Ssteve.reinhardt@amd.com self.network.connectControllers(self.controllers) 1017553SN/A self.network.setup_buffers() 1027553SN/A 1037553SN/A # Set up a proxy port for the system_port. Used for load binaries and 1047053SN/A # other functional-only things. 1057053SN/A self.sys_port_proxy = RubyPortProxy() 1066899SN/A system.system_port = self.sys_port_proxy.slave 1076899SN/A 1088922Swilliam.wang@arm.com # Connect the cpu's cache, interrupt, and TLB ports to Ruby 1097553SN/A for i,cpu in enumerate(cpus): 1106899SN/A cpu.icache_port = self.sequencers[i].slave 1117053SN/A cpu.dcache_port = self.sequencers[i].slave 1126899SN/A isa = buildEnv['TARGET_ISA'] 1137053SN/A if isa == 'x86': 1146899SN/A cpu.interrupts[0].pio = self.sequencers[i].master 1156899SN/A cpu.interrupts[0].int_master = self.sequencers[i].slave 1167053SN/A cpu.interrupts[0].int_slave = self.sequencers[i].master 1177553SN/A if isa == 'x86' or isa == 'arm': 1186899SN/A cpu.itb.walker.port = self.sequencers[i].slave 1197553SN/A cpu.dtb.walker.port = self.sequencers[i].slave 1207553SN/A 1217553SN/A 1227553SN/Aclass L1Cache(L1Cache_Controller): 1236899SN/A 12411320Ssteve.reinhardt@amd.com _version = 0 1257823Ssteve.reinhardt@amd.com @classmethod 1266899SN/A def versionCount(cls): 1276899SN/A cls._version += 1 # Use count for this particular type 1287053SN/A return cls._version - 1 1297553SN/A 1307053SN/A def __init__(self, system, ruby_system, cpu): 1317553SN/A """CPUs are needed to grab the clock domain and system is needed for 1327553SN/A the cache block size. 1337823Ssteve.reinhardt@amd.com """ 1347553SN/A super(L1Cache, self).__init__() 1357053SN/A 1367553SN/A self.version = self.versionCount() 1377053SN/A # This is the cache memory object that stores the cache data and tags 1386899SN/A self.cacheMemory = RubyCache(size = '16kB', 1396899SN/A assoc = 8, 1407553SN/A start_index_bit = self.getBlockSizeBits(system)) 1417553SN/A self.clk_domain = cpu.clk_domain 1426899SN/A self.send_evictions = self.sendEvicts(cpu) 1437553SN/A self.ruby_system = ruby_system 1446899SN/A self.connectQueues(ruby_system) 145 146 def getBlockSizeBits(self, system): 147 bits = int(math.log(system.cache_line_size, 2)) 148 if 2**bits != system.cache_line_size.value: 149 panic("Cache line size not a power of 2!") 150 return bits 151 152 def sendEvicts(self, cpu): 153 """True if the CPU model or ISA requires sending evictions from caches 154 to the CPU. Two scenarios warrant forwarding evictions to the CPU: 155 1. The O3 model must keep the LSQ coherent with the caches 156 2. The x86 mwait instruction is built on top of coherence 157 3. The local exclusive monitor in ARM systems 158 """ 159 if type(cpu) is DerivO3CPU or \ 160 buildEnv['TARGET_ISA'] in ('x86', 'arm'): 161 return True 162 return False 163 164 def connectQueues(self, ruby_system): 165 """Connect all of the queues for this controller. 166 """ 167 # mandatoryQueue is a special variable. It is used by the sequencer to 168 # send RubyRequests from the CPU (or other processor). It isn't 169 # explicitly connected to anything. 170 self.mandatoryQueue = MessageBuffer() 171 172 # All message buffers must be created and connected to the general 173 # Ruby network. In this case, "slave/master" don't mean the same thing 174 # as normal gem5 ports. If a MessageBuffer is a "to" buffer (i.e., out) 175 # then you use the "master", otherwise, the slave. 176 self.requestToDir = MessageBuffer(ordered = True) 177 self.requestToDir.master = ruby_system.network.slave 178 self.responseToDirOrSibling = MessageBuffer(ordered = True) 179 self.responseToDirOrSibling.master = ruby_system.network.slave 180 self.forwardFromDir = MessageBuffer(ordered = True) 181 self.forwardFromDir.slave = ruby_system.network.master 182 self.responseFromDirOrSibling = MessageBuffer(ordered = True) 183 self.responseFromDirOrSibling.slave = ruby_system.network.master 184 185class DirController(Directory_Controller): 186 187 _version = 0 188 @classmethod 189 def versionCount(cls): 190 cls._version += 1 # Use count for this particular type 191 return cls._version - 1 192 193 def __init__(self, ruby_system, ranges, mem_ctrls): 194 """ranges are the memory ranges assigned to this controller. 195 """ 196 if len(mem_ctrls) > 1: 197 panic("This cache system can only be connected to one mem ctrl") 198 super(DirController, self).__init__() 199 self.version = self.versionCount() 200 self.addr_ranges = ranges 201 self.ruby_system = ruby_system 202 self.directory = RubyDirectoryMemory() 203 # Connect this directory to the memory side. 204 self.memory = mem_ctrls[0].port 205 self.connectQueues(ruby_system) 206 207 def connectQueues(self, ruby_system): 208 self.requestFromCache = MessageBuffer(ordered = True) 209 self.requestFromCache.slave = ruby_system.network.master 210 self.responseFromCache = MessageBuffer(ordered = True) 211 self.responseFromCache.slave = ruby_system.network.master 212 213 self.responseToCache = MessageBuffer(ordered = True) 214 self.responseToCache.master = ruby_system.network.slave 215 self.forwardToCache = MessageBuffer(ordered = True) 216 self.forwardToCache.master = ruby_system.network.slave 217 218 # This is another special message buffer. It is used to send replies 219 # from memory back to the controller. Any messages received on the 220 # memory port (see self.memory above) will be directed to this 221 # message buffer. 222 self.responseFromMemory = MessageBuffer() 223 224class MyNetwork(SimpleNetwork): 225 """A simple point-to-point network. This doesn't not use garnet. 226 """ 227 228 def __init__(self, ruby_system): 229 super(MyNetwork, self).__init__() 230 self.netifs = [] 231 self.ruby_system = ruby_system 232 233 def connectControllers(self, controllers): 234 """Connect all of the controllers to routers and connec the routers 235 together in a point-to-point network. 236 """ 237 # Create one router/switch per controller in the system 238 self.routers = [Switch(router_id = i) for i in range(len(controllers))] 239 240 # Make a link from each controller to the router. The link goes 241 # externally to the network. 242 self.ext_links = [SimpleExtLink(link_id=i, ext_node=c, 243 int_node=self.routers[i]) 244 for i, c in enumerate(controllers)] 245 246 # Make an "internal" link (internal to the network) between every pair 247 # of routers. 248 link_count = 0 249 self.int_links = [] 250 for ri in self.routers: 251 for rj in self.routers: 252 if ri == rj: continue # Don't connect a router to itself! 253 link_count += 1 254 self.int_links.append(SimpleIntLink(link_id = link_count, 255 src_node = ri, 256 dst_node = rj)) 257