ruby_mem_test.py revision 7635:a322932de08f 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Ron Dreslinski
29#          Brad Beckmann
30
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from m5.util import addToPath
35import os, optparse, sys
36addToPath('../common')
37addToPath('../ruby')
38
39import Ruby
40
41if buildEnv['FULL_SYSTEM']:
42    panic("This script requires system-emulation mode (*_SE).")
43
44# Get paths we might need.  It's expected this file is in m5/configs/example.
45config_path = os.path.dirname(os.path.abspath(__file__))
46config_root = os.path.dirname(config_path)
47m5_root = os.path.dirname(config_root)
48
49parser = optparse.OptionParser()
50
51parser.add_option("-l", "--maxloads", metavar="N", default=0,
52                  help="Stop after N loads")
53parser.add_option("--progress", type="int", default=1000,
54                  metavar="NLOADS",
55                  help="Progress message interval "
56                  "[default: %default]")
57parser.add_option("--num-dmas", type="int", default=0, help="# of dma testers")
58
59#
60# Add the ruby specific and protocol specific options
61#
62Ruby.define_options(parser)
63
64execfile(os.path.join(config_root, "common", "Options.py"))
65
66(options, args) = parser.parse_args()
67
68#
69# Set the default cache size and associativity to be very small to encourage
70# races between requests and writebacks.
71#
72options.l1d_size="256B"
73options.l1i_size="256B"
74options.l2_size="512B"
75options.l3_size="1kB"
76options.l1d_assoc=2
77options.l1i_assoc=2
78options.l2_assoc=2
79options.l3_assoc=2
80
81if args:
82     print "Error: script doesn't take any positional arguments"
83     sys.exit(1)
84
85block_size = 64
86
87if options.num_cpus > block_size:
88     print "Error: Number of testers %d limited to %d because of false sharing" \
89           % (options.num_cpus, block_size)
90     sys.exit(1)
91
92#
93# Currently ruby does not support atomic, functional, or uncacheable accesses
94#
95cpus = [ MemTest(atomic = False, \
96                 max_loads = options.maxloads, \
97                 issue_dmas = False, \
98                 percent_functional = 0, \
99                 percent_uncacheable = 0, \
100                 progress_interval = options.progress) \
101         for i in xrange(options.num_cpus) ]
102
103system = System(cpu = cpus,
104                funcmem = PhysicalMemory(),
105                physmem = PhysicalMemory())
106
107if options.num_dmas > 0:
108    dmas = [ MemTest(atomic = False, \
109                     max_loads = options.maxloads, \
110                     issue_dmas = True, \
111                     percent_functional = 0, \
112                     percent_uncacheable = 0, \
113                     progress_interval = options.progress) \
114             for i in xrange(options.num_dmas) ]
115    system.dma_devices = dmas
116else:
117    dmas = []
118
119system.ruby = Ruby.create_system(options, \
120                                 system, \
121                                 dma_devices = dmas)
122
123#
124# The tester is most effective when randomization is turned on and
125# artifical delay is randomly inserted on messages
126#
127system.ruby.randomization = True
128
129assert(len(cpus) == len(system.ruby.cpu_ruby_ports))
130
131for (i, cpu) in enumerate(cpus):
132    #
133    # Tie the cpu memtester ports to the correct system ports
134    #
135    cpu.test = system.ruby.cpu_ruby_ports[i].port
136    cpu.functional = system.funcmem.port
137
138for (i, dma) in enumerate(dmas):
139    #
140    # Tie the dma memtester ports to the correct functional port
141    # Note that the test port has already been connected to the dma_sequencer
142    #
143    dma.functional = system.funcmem.port
144
145# -----------------------
146# run simulation
147# -----------------------
148
149root = Root( system = system )
150root.system.mem_mode = 'timing'
151
152# Not much point in this being higher than the L1 latency
153m5.ticks.setGlobalFrequency('1ns')
154
155# instantiate configuration
156m5.instantiate()
157
158# simulate until program terminates
159exit_event = m5.simulate(options.maxtick)
160
161print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
162