ruby_mem_test.py revision 11688:725fef71f376 
1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# Copyright (c) 2009 Advanced Micro Devices, Inc.
3# All rights reserved.
4#
5# Redistribution and use in source and binary forms, with or without
6# modification, are permitted provided that the following conditions are
7# met: redistributions of source code must retain the above copyright
8# notice, this list of conditions and the following disclaimer;
9# redistributions in binary form must reproduce the above copyright
10# notice, this list of conditions and the following disclaimer in the
11# documentation and/or other materials provided with the distribution;
12# neither the name of the copyright holders nor the names of its
13# contributors may be used to endorse or promote products derived from
14# this software without specific prior written permission.
15#
16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27#
28# Authors: Ron Dreslinski
29#          Brad Beckmann
30
31import m5
32from m5.objects import *
33from m5.defines import buildEnv
34from m5.util import addToPath
35import os, optparse, sys
36
37addToPath('../')
38
39from common import Options
40from ruby import Ruby
41
42# Get paths we might need.  It's expected this file is in m5/configs/example.
43config_path = os.path.dirname(os.path.abspath(__file__))
44config_root = os.path.dirname(config_path)
45
46parser = optparse.OptionParser()
47Options.addNoISAOptions(parser)
48
49parser.add_option("--maxloads", metavar="N", default=0,
50                  help="Stop after N loads")
51parser.add_option("--progress", type="int", default=1000,
52                  metavar="NLOADS",
53                  help="Progress message interval "
54                  "[default: %default]")
55parser.add_option("--num-dmas", type="int", default=0, help="# of dma testers")
56parser.add_option("--functional", type="int", default=0,
57                  help="percentage of accesses that should be functional")
58parser.add_option("--suppress-func-warnings", action="store_true",
59                  help="suppress warnings when functional accesses fail")
60
61#
62# Add the ruby specific and protocol specific options
63#
64Ruby.define_options(parser)
65
66execfile(os.path.join(config_root, "common", "Options.py"))
67
68(options, args) = parser.parse_args()
69
70#
71# Set the default cache size and associativity to be very small to encourage
72# races between requests and writebacks.
73#
74options.l1d_size="256B"
75options.l1i_size="256B"
76options.l2_size="512B"
77options.l3_size="1kB"
78options.l1d_assoc=2
79options.l1i_assoc=2
80options.l2_assoc=2
81options.l3_assoc=2
82
83if args:
84     print "Error: script doesn't take any positional arguments"
85     sys.exit(1)
86
87block_size = 64
88
89if options.num_cpus > block_size:
90     print "Error: Number of testers %d limited to %d because of false sharing" \
91           % (options.num_cpus, block_size)
92     sys.exit(1)
93
94#
95# Currently ruby does not support atomic or uncacheable accesses
96#
97cpus = [ MemTest(atomic = False,
98                 max_loads = options.maxloads,
99                 issue_dmas = False,
100                 percent_functional = options.functional,
101                 percent_uncacheable = 0,
102                 progress_interval = options.progress,
103                 suppress_func_warnings = options.suppress_func_warnings) \
104         for i in xrange(options.num_cpus) ]
105
106system = System(cpu = cpus,
107                funcmem = SimpleMemory(in_addr_map = False),
108                funcbus = IOXBar(),
109                clk_domain = SrcClockDomain(clock = options.sys_clock),
110                mem_ranges = [AddrRange(options.mem_size)])
111
112if options.num_dmas > 0:
113    dmas = [ MemTest(atomic = False,
114                     max_loads = options.maxloads,
115                     issue_dmas = True,
116                     percent_functional = 0,
117                     percent_uncacheable = 0,
118                     progress_interval = options.progress,
119                     suppress_func_warnings =
120                                        not options.suppress_func_warnings) \
121             for i in xrange(options.num_dmas) ]
122    system.dma_devices = dmas
123else:
124    dmas = []
125
126dma_ports = []
127for (i, dma) in enumerate(dmas):
128    dma_ports.append(dma.test)
129Ruby.create_system(options, False, system, dma_ports = dma_ports)
130
131# Create a top-level voltage domain and clock domain
132system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
133system.clk_domain = SrcClockDomain(clock = options.sys_clock,
134                                   voltage_domain = system.voltage_domain)
135# Create a seperate clock domain for Ruby
136system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
137                                        voltage_domain = system.voltage_domain)
138
139#
140# The tester is most effective when randomization is turned on and
141# artifical delay is randomly inserted on messages
142#
143system.ruby.randomization = True
144
145assert(len(cpus) == len(system.ruby._cpu_ports))
146
147for (i, cpu) in enumerate(cpus):
148    #
149    # Tie the cpu memtester ports to the correct system ports
150    #
151    cpu.test = system.ruby._cpu_ports[i].slave
152    cpu.functional = system.funcbus.slave
153
154    #
155    # Since the memtester is incredibly bursty, increase the deadlock
156    # threshold to 5 million cycles
157    #
158    system.ruby._cpu_ports[i].deadlock_threshold = 5000000
159
160for (i, dma) in enumerate(dmas):
161    #
162    # Tie the dma memtester ports to the correct functional port
163    # Note that the test port has already been connected to the dma_sequencer
164    #
165    dma.functional = system.funcbus.slave
166
167# connect reference memory to funcbus
168system.funcbus.master = system.funcmem.port
169
170# -----------------------
171# run simulation
172# -----------------------
173
174root = Root( full_system = False, system = system )
175root.system.mem_mode = 'timing'
176
177# Not much point in this being higher than the L1 latency
178m5.ticks.setGlobalFrequency('1ns')
179
180# instantiate configuration
181m5.instantiate()
182
183# simulate until program terminates
184exit_event = m5.simulate(options.abs_max_tick)
185
186print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
187