ruby_mem_test.py revision 10083:2beea2a439b4
12SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 21762SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 32SN/A# All rights reserved. 42SN/A# 52SN/A# Redistribution and use in source and binary forms, with or without 62SN/A# modification, are permitted provided that the following conditions are 72SN/A# met: redistributions of source code must retain the above copyright 82SN/A# notice, this list of conditions and the following disclaimer; 92SN/A# redistributions in binary form must reproduce the above copyright 102SN/A# notice, this list of conditions and the following disclaimer in the 112SN/A# documentation and/or other materials provided with the distribution; 122SN/A# neither the name of the copyright holders nor the names of its 132SN/A# contributors may be used to endorse or promote products derived from 142SN/A# this software without specific prior written permission. 152SN/A# 162SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu# 282665Ssaidi@eecs.umich.edu# Authors: Ron Dreslinski 292665Ssaidi@eecs.umich.edu# Brad Beckmann 302SN/A 312SN/Aimport m5 322SN/Afrom m5.objects import * 332SN/Afrom m5.defines import buildEnv 342SN/Afrom m5.util import addToPath 352520SN/Aimport os, optparse, sys 362207SN/AaddToPath('../common') 372207SN/AaddToPath('../ruby') 3811389Sbrandon.potter@amd.comaddToPath('../topologies') 396214Snate@binkert.org 402SN/Aimport Options 418706Sandreas.hansson@arm.comimport Ruby 422SN/A 432SN/A# Get paths we might need. It's expected this file is in m5/configs/example. 442SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 452SN/Aconfig_root = os.path.dirname(config_path) 46360SN/A 47360SN/Aparser = optparse.OptionParser() 48360SN/AOptions.addCommonOptions(parser) 49360SN/A 502207SN/Aparser.add_option("--maxloads", metavar="N", default=0, 514111Sgblack@eecs.umich.edu help="Stop after N loads") 524111Sgblack@eecs.umich.eduparser.add_option("--progress", type="int", default=1000, 534155Sgblack@eecs.umich.edu metavar="NLOADS", 545874Sgblack@eecs.umich.edu help="Progress message interval " 555874Sgblack@eecs.umich.edu "[default: %default]") 5610037SARM gem5 Developersparser.add_option("--num-dmas", type="int", default=0, help="# of dma testers") 576691Stjones1@inf.ed.ac.ukparser.add_option("--functional", type="int", default=0, 587095Sgblack@eecs.umich.edu help="percentage of accesses that should be functional") 596691Stjones1@inf.ed.ac.ukparser.add_option("--suppress-func-warnings", action="store_true", 60360SN/A help="suppress warnings when functional accesses fail") 61360SN/A 62360SN/A# 63360SN/A# Add the ruby specific and protocol specific options 64360SN/A# 652207SN/ARuby.define_options(parser) 666392Ssaidi@eecs.umich.edu 6710810Sbr@bsdpad.comexecfile(os.path.join(config_root, "common", "Options.py")) 6810810Sbr@bsdpad.com 69360SN/A(options, args) = parser.parse_args() 70360SN/A 712SN/A# 7212SN/A# Set the default cache size and associativity to be very small to encourage 7312SN/A# races between requests and writebacks. 742SN/A# 752SN/Aoptions.l1d_size="256B" 76360SN/Aoptions.l1i_size="256B" 77360SN/Aoptions.l2_size="512B" 78360SN/Aoptions.l3_size="1kB" 7910880SCurtis.Dunham@arm.comoptions.l1d_assoc=2 80360SN/Aoptions.l1i_assoc=2 8112SN/Aoptions.l2_assoc=2 822SN/Aoptions.l3_assoc=2 832SN/A 842SN/Aif args: 8511392Sbrandon.potter@amd.com print "Error: script doesn't take any positional arguments" 8611392Sbrandon.potter@amd.com sys.exit(1) 8711392Sbrandon.potter@amd.com 8811392Sbrandon.potter@amd.comblock_size = 64 8911392Sbrandon.potter@amd.com 9011392Sbrandon.potter@amd.comif options.num_cpus > block_size: 9111392Sbrandon.potter@amd.com print "Error: Number of testers %d limited to %d because of false sharing" \ 9211392Sbrandon.potter@amd.com % (options.num_cpus, block_size) 9311392Sbrandon.potter@amd.com sys.exit(1) 9411392Sbrandon.potter@amd.com 9511392Sbrandon.potter@amd.com# 9611392Sbrandon.potter@amd.com# Currently ruby does not support atomic or uncacheable accesses 9711392Sbrandon.potter@amd.com# 989641Sguodeyuan@tsinghua.org.cncpus = [ MemTest(atomic = False, 992SN/A max_loads = options.maxloads, 10011389Sbrandon.potter@amd.com issue_dmas = False, 10111389Sbrandon.potter@amd.com percent_functional = options.functional, 10211389Sbrandon.potter@amd.com percent_uncacheable = 0, 10311389Sbrandon.potter@amd.com progress_interval = options.progress, 10411389Sbrandon.potter@amd.com suppress_func_warnings = options.suppress_func_warnings) \ 10511389Sbrandon.potter@amd.com for i in xrange(options.num_cpus) ] 10611389Sbrandon.potter@amd.com 10711389Sbrandon.potter@amd.comsystem = System(cpu = cpus, 1085070Ssaidi@eecs.umich.edu funcmem = SimpleMemory(in_addr_map = False), 1093917Ssaidi@eecs.umich.edu funcbus = NoncoherentBus(), 110360SN/A physmem = SimpleMemory(), 111360SN/A clk_domain = SrcClockDomain(clock = options.sys_clock), 112360SN/A mem_ranges = [AddrRange(options.mem_size)]) 1132SN/A 1142SN/Aif options.num_dmas > 0: 11512SN/A dmas = [ MemTest(atomic = False, 1162420SN/A max_loads = options.maxloads, 1172420SN/A issue_dmas = True, 1182420SN/A percent_functional = 0, 11912SN/A percent_uncacheable = 0, 12012SN/A progress_interval = options.progress, 12112SN/A suppress_func_warnings = 12212SN/A not options.suppress_func_warnings) \ 12312SN/A for i in xrange(options.num_dmas) ] 12412SN/A system.dma_devices = dmas 12512SN/Aelse: 12612SN/A dmas = [] 1272SN/A 12811392Sbrandon.potter@amd.comdma_ports = [] 12910037SARM gem5 Developersfor (i, dma) in enumerate(dmas): 1302472SN/A dma_ports.append(dma.test) 1312420SN/ARuby.create_system(options, system, dma_ports = dma_ports) 1322SN/A 13312SN/A# Create a top-level voltage domain and clock domain 1342472SN/Asystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 13512SN/Asystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 1362SN/A voltage_domain = system.voltage_domain) 13712SN/A# Create a seperate clock domain for Ruby 13812SN/Asystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 13912SN/A voltage_domain = system.voltage_domain) 14012SN/A 14112SN/A# 14212SN/A# The tester is most effective when randomization is turned on and 14312SN/A# artifical delay is randomly inserted on messages 1443584Ssaidi@eecs.umich.edu# 1459261Sdam.sunwoo@arm.comsystem.ruby.randomization = True 1469261Sdam.sunwoo@arm.com 1479261Sdam.sunwoo@arm.comassert(len(cpus) == len(system.ruby._cpu_ruby_ports)) 1489261Sdam.sunwoo@arm.com 1499261Sdam.sunwoo@arm.comfor (i, cpu) in enumerate(cpus): 1503584Ssaidi@eecs.umich.edu # 1512SN/A # Tie the cpu memtester ports to the correct system ports 1522SN/A # 1533584Ssaidi@eecs.umich.edu cpu.test = system.ruby._cpu_ruby_ports[i].slave 1542SN/A cpu.functional = system.funcbus.slave 1552SN/A 1562SN/A # 157 # Since the memtester is incredibly bursty, increase the deadlock 158 # threshold to 5 million cycles 159 # 160 system.ruby._cpu_ruby_ports[i].deadlock_threshold = 5000000 161 162 # 163 # Ruby doesn't need the backing image of memory when running with 164 # the tester. 165 # 166 system.ruby._cpu_ruby_ports[i].access_phys_mem = False 167 168for (i, dma) in enumerate(dmas): 169 # 170 # Tie the dma memtester ports to the correct functional port 171 # Note that the test port has already been connected to the dma_sequencer 172 # 173 dma.functional = system.funcbus.slave 174 175# connect reference memory to funcbus 176system.funcbus.master = system.funcmem.port 177 178# ----------------------- 179# run simulation 180# ----------------------- 181 182root = Root( full_system = False, system = system ) 183root.system.mem_mode = 'timing' 184 185# Not much point in this being higher than the L1 latency 186m5.ticks.setGlobalFrequency('1ns') 187 188# instantiate configuration 189m5.instantiate() 190 191# simulate until program terminates 192exit_event = m5.simulate(options.abs_max_tick) 193 194print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 195