ruby_direct_test.py revision 9870:e147cc305061
1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# Copyright (c) 2009 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# Redistribution and use in source and binary forms, with or without 6# modification, are permitted provided that the following conditions are 7# met: redistributions of source code must retain the above copyright 8# notice, this list of conditions and the following disclaimer; 9# redistributions in binary form must reproduce the above copyright 10# notice, this list of conditions and the following disclaimer in the 11# documentation and/or other materials provided with the distribution; 12# neither the name of the copyright holders nor the names of its 13# contributors may be used to endorse or promote products derived from 14# this software without specific prior written permission. 15# 16# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27# 28# Authors: Ron Dreslinski 29# Brad Beckmann 30 31import m5 32from m5.objects import * 33from m5.defines import buildEnv 34from m5.util import addToPath 35import os, optparse, sys 36addToPath('../common') 37addToPath('../ruby') 38addToPath('../topologies') 39 40import Options 41import Ruby 42 43# Get paths we might need. It's expected this file is in m5/configs/example. 44config_path = os.path.dirname(os.path.abspath(__file__)) 45config_root = os.path.dirname(config_path) 46m5_root = os.path.dirname(config_root) 47 48parser = optparse.OptionParser() 49Options.addCommonOptions(parser) 50 51parser.add_option("-l", "--requests", metavar="N", default=100, 52 help="Stop after N requests") 53parser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 54 help="Wakeup every N cycles") 55parser.add_option("--test-type", type="choice", default="SeriesGetx", 56 choices = ["SeriesGetx", "SeriesGets", "SeriesGetMixed", 57 "Invalidate"], 58 help = "Type of test") 59parser.add_option("--percent-writes", type="int", default=100, 60 help="percentage of accesses that should be writes") 61 62# 63# Add the ruby specific and protocol specific options 64# 65Ruby.define_options(parser) 66(options, args) = parser.parse_args() 67 68if args: 69 print "Error: script doesn't take any positional arguments" 70 sys.exit(1) 71 72# 73# Select the direct test generator 74# 75if options.test_type == "SeriesGetx": 76 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 77 percent_writes = 100) 78elif options.test_type == "SeriesGets": 79 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 80 percent_writes = 0) 81elif options.test_type == "SeriesGetMixed": 82 generator = SeriesRequestGenerator(num_cpus = options.num_cpus, 83 percent_writes = options.percent_writes) 84elif options.test_type == "Invalidate": 85 generator = InvalidateGenerator(num_cpus = options.num_cpus) 86else: 87 print "Error: unknown direct test generator" 88 sys.exit(1) 89 90# 91# Create the M5 system. Note that the Memory Object isn't 92# actually used by the rubytester, but is included to support the 93# M5 memory size == Ruby memory size checks 94# 95system = System(physmem = SimpleMemory()) 96 97 98# Create a top-level voltage domain and clock domain 99system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 100 101system.clk_domain = SrcClockDomain(clock = options.sys_clock, 102 voltage_domain = system.voltage_domain) 103 104# 105# Create the ruby random tester 106# 107system.tester = RubyDirectedTester(requests_to_complete = \ 108 options.requests, 109 generator = generator) 110 111Ruby.create_system(options, system) 112 113# Since Ruby runs at an independent frequency, create a seperate clock 114system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 115 voltage_domain = system.voltage_domain) 116 117assert(options.num_cpus == len(system.ruby._cpu_ruby_ports)) 118 119for ruby_port in system.ruby._cpu_ruby_ports: 120 # 121 # Tie the ruby tester ports to the ruby cpu ports 122 # 123 system.tester.cpuPort = ruby_port.slave 124 125# ----------------------- 126# run simulation 127# ----------------------- 128 129root = Root( full_system = False, system = system ) 130root.system.mem_mode = 'timing' 131 132# Not much point in this being higher than the L1 latency 133m5.ticks.setGlobalFrequency('1ns') 134 135# instantiate configuration 136m5.instantiate() 137 138# simulate until program terminates 139exit_event = m5.simulate(options.maxtick) 140 141print 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 142