ruby_direct_test.py revision 9909
16899SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan
26899SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc.
36899SN/A# All rights reserved.
46899SN/A#
56899SN/A# Redistribution and use in source and binary forms, with or without
66899SN/A# modification, are permitted provided that the following conditions are
76899SN/A# met: redistributions of source code must retain the above copyright
86899SN/A# notice, this list of conditions and the following disclaimer;
96899SN/A# redistributions in binary form must reproduce the above copyright
106899SN/A# notice, this list of conditions and the following disclaimer in the
116899SN/A# documentation and/or other materials provided with the distribution;
126899SN/A# neither the name of the copyright holders nor the names of its
136899SN/A# contributors may be used to endorse or promote products derived from
146899SN/A# this software without specific prior written permission.
156899SN/A#
166899SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176899SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186899SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
196899SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
206899SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
216899SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
226899SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
236899SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
246899SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
256899SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
266899SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276899SN/A#
286899SN/A# Authors: Ron Dreslinski
296899SN/A#          Brad Beckmann
306899SN/A
316899SN/Aimport m5
326899SN/Afrom m5.objects import *
336899SN/Afrom m5.defines import buildEnv
346899SN/Afrom m5.util import addToPath
356899SN/Aimport os, optparse, sys
366899SN/AaddToPath('../common')
376899SN/AaddToPath('../ruby')
389100SBrad.Beckmann@amd.comaddToPath('../topologies')
396899SN/A
408928Sandreas.hansson@arm.comimport Options
416899SN/Aimport Ruby
426899SN/A
436899SN/A# Get paths we might need.  It's expected this file is in m5/configs/example.
446899SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__))
456899SN/Aconfig_root = os.path.dirname(config_path)
466899SN/Am5_root = os.path.dirname(config_root)
476899SN/A
486899SN/Aparser = optparse.OptionParser()
498928Sandreas.hansson@arm.comOptions.addCommonOptions(parser)
506899SN/A
517553SN/Aparser.add_option("-l", "--requests", metavar="N", default=100,
527553SN/A                  help="Stop after N requests")
536899SN/Aparser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
546899SN/A                  help="Wakeup every N cycles")
559365Snilay@cs.wisc.eduparser.add_option("--test-type", type="choice", default="SeriesGetx",
569365Snilay@cs.wisc.edu                  choices = ["SeriesGetx", "SeriesGets", "SeriesGetMixed",
579365Snilay@cs.wisc.edu                             "Invalidate"],
589365Snilay@cs.wisc.edu                  help = "Type of test")
599365Snilay@cs.wisc.eduparser.add_option("--percent-writes", type="int", default=100,
609365Snilay@cs.wisc.edu                  help="percentage of accesses that should be writes")
616899SN/A
626899SN/A#
637538SN/A# Add the ruby specific and protocol specific options
646899SN/A#
657538SN/ARuby.define_options(parser)
666899SN/A(options, args) = parser.parse_args()
676899SN/A
686899SN/Aif args:
696899SN/A     print "Error: script doesn't take any positional arguments"
706899SN/A     sys.exit(1)
716899SN/A
726899SN/A#
737632SBrad.Beckmann@amd.com# Select the direct test generator
746899SN/A#
757553SN/Aif options.test_type == "SeriesGetx":
767553SN/A    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
779365Snilay@cs.wisc.edu                                       percent_writes = 100)
787553SN/Aelif options.test_type == "SeriesGets":
797553SN/A    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
809365Snilay@cs.wisc.edu                                       percent_writes = 0)
819365Snilay@cs.wisc.eduelif options.test_type == "SeriesGetMixed":
829365Snilay@cs.wisc.edu    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
839365Snilay@cs.wisc.edu                                       percent_writes = options.percent_writes)
847553SN/Aelif options.test_type == "Invalidate":
857553SN/A    generator = InvalidateGenerator(num_cpus = options.num_cpus)
867553SN/Aelse:
877632SBrad.Beckmann@amd.com    print "Error: unknown direct test generator"
887553SN/A    sys.exit(1)
896899SN/A
906899SN/A#
918931Sandreas.hansson@arm.com# Create the M5 system.  Note that the Memory Object isn't
926899SN/A# actually used by the rubytester, but is included to support the
936899SN/A# M5 memory size == Ruby memory size checks
946899SN/A#
959909Snilay@cs.wisc.edusystem = System(physmem = SimpleMemory(),
969909Snilay@cs.wisc.edu                mem_ranges = [AddrRange(options.mem_size)])
979870Sandreas.hansson@arm.com
989870Sandreas.hansson@arm.com
999870Sandreas.hansson@arm.com# Create a top-level voltage domain and clock domain
1009870Sandreas.hansson@arm.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
1019870Sandreas.hansson@arm.com
1029870Sandreas.hansson@arm.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock,
1039870Sandreas.hansson@arm.com                                   voltage_domain = system.voltage_domain)
1049793Sakash.bagdia@arm.com
1057553SN/A#
1067553SN/A# Create the ruby random tester
1077553SN/A#
1087553SN/Asystem.tester = RubyDirectedTester(requests_to_complete = \
1097553SN/A                                   options.requests,
1107632SBrad.Beckmann@amd.com                                   generator = generator)
1117553SN/A
1128436SBrad.Beckmann@amd.comRuby.create_system(options, system)
1136899SN/A
1149793Sakash.bagdia@arm.com# Since Ruby runs at an independent frequency, create a seperate clock
1159870Sandreas.hansson@arm.comsystem.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
1169870Sandreas.hansson@arm.com                                        voltage_domain = system.voltage_domain)
1179793Sakash.bagdia@arm.com
1188322Ssteve.reinhardt@amd.comassert(options.num_cpus == len(system.ruby._cpu_ruby_ports))
1196899SN/A
1208322Ssteve.reinhardt@amd.comfor ruby_port in system.ruby._cpu_ruby_ports:
1216899SN/A    #
1226899SN/A    # Tie the ruby tester ports to the ruby cpu ports
1236899SN/A    #
1248845Sandreas.hansson@arm.com    system.tester.cpuPort = ruby_port.slave
1256899SN/A
1266899SN/A# -----------------------
1276899SN/A# run simulation
1286899SN/A# -----------------------
1296899SN/A
1308801Sgblack@eecs.umich.eduroot = Root( full_system = False, system = system )
1316899SN/Aroot.system.mem_mode = 'timing'
1326899SN/A
1336899SN/A# Not much point in this being higher than the L1 latency
1346899SN/Am5.ticks.setGlobalFrequency('1ns')
1356899SN/A
1366899SN/A# instantiate configuration
1377525SN/Am5.instantiate()
1386899SN/A
1396899SN/A# simulate until program terminates
1409909Snilay@cs.wisc.eduexit_event = m5.simulate(options.abs_max_tick)
1416899SN/A
1426899SN/Aprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
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