ruby_direct_test.py revision 7553
16019Shines@cs.fsu.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan
211495Sandreas.sandberg@arm.com# Copyright (c) 2009 Advanced Micro Devices, Inc.
37093Sgblack@eecs.umich.edu# All rights reserved.
47093Sgblack@eecs.umich.edu#
57093Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
67093Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are
77093Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright
87093Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
97093Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
107093Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
117093Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution;
127093Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its
137093Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from
146019Shines@cs.fsu.edu# this software without specific prior written permission.
156019Shines@cs.fsu.edu#
166019Shines@cs.fsu.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
176019Shines@cs.fsu.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
186019Shines@cs.fsu.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
196019Shines@cs.fsu.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
206019Shines@cs.fsu.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
216019Shines@cs.fsu.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
226019Shines@cs.fsu.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
236019Shines@cs.fsu.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
246019Shines@cs.fsu.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
256019Shines@cs.fsu.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
266019Shines@cs.fsu.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
276019Shines@cs.fsu.edu#
286019Shines@cs.fsu.edu# Authors: Ron Dreslinski
296019Shines@cs.fsu.edu#          Brad Beckmann
306019Shines@cs.fsu.edu
316019Shines@cs.fsu.eduimport m5
326019Shines@cs.fsu.edufrom m5.objects import *
336019Shines@cs.fsu.edufrom m5.defines import buildEnv
346019Shines@cs.fsu.edufrom m5.util import addToPath
356019Shines@cs.fsu.eduimport os, optparse, sys
366019Shines@cs.fsu.eduaddToPath('../common')
376019Shines@cs.fsu.eduaddToPath('../ruby')
386019Shines@cs.fsu.edu
396019Shines@cs.fsu.eduimport Ruby
407399SAli.Saidi@ARM.com
417399SAli.Saidi@ARM.comif buildEnv['FULL_SYSTEM']:
426019Shines@cs.fsu.edu    panic("This script requires system-emulation mode (*_SE).")
436019Shines@cs.fsu.edu
446019Shines@cs.fsu.edu# Get paths we might need.  It's expected this file is in m5/configs/example.
4510873Sandreas.sandberg@arm.comconfig_path = os.path.dirname(os.path.abspath(__file__))
4610873Sandreas.sandberg@arm.comconfig_root = os.path.dirname(config_path)
4710474Sandreas.hansson@arm.comm5_root = os.path.dirname(config_root)
486019Shines@cs.fsu.edu
496019Shines@cs.fsu.eduparser = optparse.OptionParser()
506019Shines@cs.fsu.edu
516116Snate@binkert.orgparser.add_option("-l", "--requests", metavar="N", default=100,
526019Shines@cs.fsu.edu                  help="Stop after N requests")
538782Sgblack@eecs.umich.eduparser.add_option("-f", "--wakeup_freq", metavar="N", default=10,
548756Sgblack@eecs.umich.edu                  help="Wakeup every N cycles")
5510037SARM gem5 Developersparser.add_option("--test-type", type="string", default="SeriesGetx",
5610037SARM gem5 Developers                  help="SeriesGetx|SeriesGets|Invalidate")
576019Shines@cs.fsu.edu
586019Shines@cs.fsu.edu#
596019Shines@cs.fsu.edu# Add the ruby specific and protocol specific options
606019Shines@cs.fsu.edu#
6110024Sdam.sunwoo@arm.comRuby.define_options(parser)
626019Shines@cs.fsu.edu
638232Snate@binkert.orgexecfile(os.path.join(config_root, "common", "Options.py"))
648232Snate@binkert.org
658232Snate@binkert.org(options, args) = parser.parse_args()
666116Snate@binkert.org
676116Snate@binkert.orgif args:
688756Sgblack@eecs.umich.edu     print "Error: script doesn't take any positional arguments"
696019Shines@cs.fsu.edu     sys.exit(1)
706019Shines@cs.fsu.edu
716019Shines@cs.fsu.edu#
726019Shines@cs.fsu.edu# Select the directed generator
736019Shines@cs.fsu.edu#
7410037SARM gem5 Developersif options.test_type == "SeriesGetx":
7510037SARM gem5 Developers    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
7610418Sandreas.hansson@arm.com                                             issue_writes = True)
7710418Sandreas.hansson@arm.comelif options.test_type == "SeriesGets":
7811395Sandreas.sandberg@arm.com    generator = SeriesRequestGenerator(num_cpus = options.num_cpus,
7910537Sandreas.hansson@arm.com                                             issue_writes = False)
8010537Sandreas.hansson@arm.comelif options.test_type == "Invalidate":
8111152Smitch.hayenga@arm.com    generator = InvalidateGenerator(num_cpus = options.num_cpus)
826019Shines@cs.fsu.eduelse:
8310037SARM gem5 Developers    print "Error: unknown directed generator"
847399SAli.Saidi@ARM.com    sys.exit(1)
8510037SARM gem5 Developers
8610037SARM gem5 Developers#
8710037SARM gem5 Developers# Create the M5 system.  Note that the PhysicalMemory Object isn't
8810037SARM gem5 Developers# actually used by the rubytester, but is included to support the
896019Shines@cs.fsu.edu# M5 memory size == Ruby memory size checks
906019Shines@cs.fsu.edu#
916019Shines@cs.fsu.edusystem = System(physmem = PhysicalMemory())
926019Shines@cs.fsu.edu
9310037SARM gem5 Developers#
9410037SARM gem5 Developers# Create the ruby random tester
9510037SARM gem5 Developers#
9610037SARM gem5 Developerssystem.tester = RubyDirectedTester(requests_to_complete = \
9710037SARM gem5 Developers                                   options.requests,
9810037SARM gem5 Developers                                 generator = generator)
9910037SARM gem5 Developers
10010037SARM gem5 Developerssystem.ruby = Ruby.create_system(options, system)
10110037SARM gem5 Developers
10210037SARM gem5 Developersassert(options.num_cpus == len(system.ruby.cpu_ruby_ports))
10310037SARM gem5 Developers
10410717Sandreas.hansson@arm.comfor ruby_port in system.ruby.cpu_ruby_ports:
10510037SARM gem5 Developers    #
10610037SARM gem5 Developers    # Tie the ruby tester ports to the ruby cpu ports
10710717Sandreas.hansson@arm.com    #
1086019Shines@cs.fsu.edu    system.tester.cpuPort = ruby_port.port
1096019Shines@cs.fsu.edu
1107694SAli.Saidi@ARM.com# -----------------------
1117694SAli.Saidi@ARM.com# run simulation
1127694SAli.Saidi@ARM.com# -----------------------
11310037SARM gem5 Developers
11410037SARM gem5 Developersroot = Root( system = system )
11510037SARM gem5 Developersroot.system.mem_mode = 'timing'
11610037SARM gem5 Developers
11710037SARM gem5 Developers# Not much point in this being higher than the L1 latency
11810037SARM gem5 Developersm5.ticks.setGlobalFrequency('1ns')
11910037SARM gem5 Developers
12010037SARM gem5 Developers# instantiate configuration
12110037SARM gem5 Developersm5.instantiate()
1227694SAli.Saidi@ARM.com
1237694SAli.Saidi@ARM.com# simulate until program terminates
1247694SAli.Saidi@ARM.comexit_event = m5.simulate(options.maxtick)
1257694SAli.Saidi@ARM.com
1267694SAli.Saidi@ARM.comprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause()
1277694SAli.Saidi@ARM.com