ruby_direct_test.py revision 7525
12SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 22188SN/A# Copyright (c) 2009 Advanced Micro Devices, Inc. 32SN/A# All rights reserved. 42SN/A# 52SN/A# Redistribution and use in source and binary forms, with or without 62SN/A# modification, are permitted provided that the following conditions are 72SN/A# met: redistributions of source code must retain the above copyright 82SN/A# notice, this list of conditions and the following disclaimer; 92SN/A# redistributions in binary form must reproduce the above copyright 102SN/A# notice, this list of conditions and the following disclaimer in the 112SN/A# documentation and/or other materials provided with the distribution; 122SN/A# neither the name of the copyright holders nor the names of its 132SN/A# contributors may be used to endorse or promote products derived from 142SN/A# this software without specific prior written permission. 152SN/A# 162SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A# 282665SN/A# Authors: Ron Dreslinski 292665SN/A# Brad Beckmann 302665SN/A 312665SN/Aimport m5 322SN/Afrom m5.objects import * 332SN/Afrom m5.defines import buildEnv 342SN/Afrom m5.util import addToPath 352SN/Aimport os, optparse, sys 362465SN/AaddToPath('../common') 371717SN/AaddToPath('../ruby') 382683Sktlim@umich.edu 392680SN/Aimport Ruby 402SN/A 411858SN/Aif buildEnv['FULL_SYSTEM']: 421917SN/A panic("This script requires system-emulation mode (*_SE).") 431070SN/A 441917SN/A# Get paths we might need. It's expected this file is in m5/configs/example. 452188SN/Aconfig_path = os.path.dirname(os.path.abspath(__file__)) 461917SN/Aconfig_root = os.path.dirname(config_path) 472290SN/Am5_root = os.path.dirname(config_root) 481070SN/A 491070SN/Aparser = optparse.OptionParser() 501917SN/A 512170SN/Aparser.add_option("-l", "--checks", metavar="N", default=100, 522SN/A help="Stop after N checks (loads)") 53360SN/Aparser.add_option("-f", "--wakeup_freq", metavar="N", default=10, 542519SN/A help="Wakeup every N cycles") 552420SN/A 562SN/A# 572SN/A# Set the default cache size and associativity to be very small to encourage 582SN/A# races between requests and writebacks. 592SN/A# 602SN/Aparser.add_option("--l1d_size", type="string", default="256B") 611858SN/Aparser.add_option("--l1i_size", type="string", default="256B") 622683Sktlim@umich.eduparser.add_option("--l2_size", type="string", default="512B") 632683Sktlim@umich.eduparser.add_option("--l1d_assoc", type="int", default=2) 642683Sktlim@umich.eduparser.add_option("--l1i_assoc", type="int", default=2) 652683Sktlim@umich.eduparser.add_option("--l2_assoc", type="int", default=2) 662683Sktlim@umich.edu 672521SN/Aexecfile(os.path.join(config_root, "common", "Options.py")) 682SN/A 692683Sktlim@umich.edu(options, args) = parser.parse_args() 702190SN/A 712680SN/Aif args: 722290SN/A print "Error: script doesn't take any positional arguments" 732526SN/A sys.exit(1) 741917SN/A 751917SN/A# 761982SN/A# Create the ruby random tester 771917SN/A# 782683Sktlim@umich.edutester = RubyTester(checks_to_complete = options.checks, 792683Sktlim@umich.edu wakeup_frequency = options.wakeup_freq) 801917SN/A 811917SN/A# 821917SN/A# Create the M5 system. Note that the PhysicalMemory Object isn't 831917SN/A# actually used by the rubytester, but is included to support the 841917SN/A# M5 memory size == Ruby memory size checks 851917SN/A# 861917SN/Asystem = System(physmem = PhysicalMemory()) 871917SN/A 882521SN/Asystem.ruby = Ruby.create_system(options, system.physmem) 892341SN/A 902341SN/Aassert(options.num_cpus == len(system.ruby.cpu_ruby_ports)) 912341SN/A 922341SN/A# 932341SN/A# The tester is most effective when randomization is turned on and 942521SN/A# artifical delay is randomly inserted on messages 952640SN/A# 962683Sktlim@umich.edusystem.ruby.randomization = True 972521SN/A 982521SN/Afor ruby_port in system.ruby.cpu_ruby_ports: 992521SN/A # 1002521SN/A # Tie the ruby tester ports to the ruby cpu ports 1012640SN/A # 1022683Sktlim@umich.edu tester.cpuPort = ruby_port.port 1032521SN/A 1042521SN/A # 1052521SN/A # Tell each sequencer this is the ruby tester so that it 1062SN/A # copies the subblock back to the checker 1072SN/A # 1082683Sktlim@umich.edu ruby_port.using_ruby_tester = True 1092520SN/A 1102791Sktlim@umich.edu# ----------------------- 1112683Sktlim@umich.edu# run simulation 1122SN/A# ----------------------- 1132519SN/A 1142519SN/Aroot = Root( system = system ) 1152640SN/Aroot.system.mem_mode = 'timing' 1162683Sktlim@umich.edu 1172640SN/A# Not much point in this being higher than the L1 latency 1182520SN/Am5.ticks.setGlobalFrequency('1ns') 1192519SN/A 1202519SN/A# instantiate configuration 1212519SN/Am5.instantiate() 1222526SN/A 1232683Sktlim@umich.edu# simulate until program terminates 1242SN/Aexit_event = m5.simulate(options.maxtick) 1252190SN/A 1262862Sktlim@umich.eduprint 'Exiting @ tick', m5.curTick(), 'because', exit_event.getCause() 1272862Sktlim@umich.edu