hmctest.py revision 12340:a52f6d327259 
1import sys
2import argparse
3import subprocess
4from pprint import pprint
5
6import m5
7from m5.objects import *
8from m5.util import *
9
10addToPath('../')
11
12from common import MemConfig
13from common import HMC
14
15
16def add_options(parser):
17    parser.add_argument("--external-memory-system", default=0, action="store",
18                        type=int, help="External memory system")
19    # TLM related options, currently optional in configs/common/MemConfig.py
20    parser.add_argument("--tlm-memory", action="store_true", help="use\
21                        external port for SystemC TLM co-simulation. Default:\
22                        no")
23    # Elastic traces related options, currently optional in
24    # configs/common/MemConfig.py
25    parser.add_argument("--elastic-trace-en", action="store_true",
26                        help="enable capture of data dependency and\
27                        instruction fetch traces using elastic trace\
28                        probe.\nDefault: no")
29    # Options related to traffic generation
30    parser.add_argument("--num-tgen", default=4, action="store", type=int,
31                        choices=[4], help="number of traffic generators.\
32                        Right now this script supports only 4.\nDefault: 4")
33    parser.add_argument("--tgen-cfg-file",
34                        default="./configs/example/hmc_tgen.cfg",
35                        type=str, help="Traffic generator(s) configuration\
36                        file. Note: this script uses the same configuration\
37                        file for all traffic generators")
38
39
40# considering 4GB HMC device with following parameters
41# hmc_device_size = '4GB'
42# hmc_vault_size = '256MB'
43# hmc_stack_size = 8
44# hmc_bank_in_stack = 2
45# hmc_bank_size = '16MB'
46# hmc_bank_in_vault = 16
47def build_system(options):
48    # create the system we are going to simulate
49    system = System()
50    # use timing mode for the interaction between master-slave ports
51    system.mem_mode = 'timing'
52    # set the clock fequency of the system
53    clk = '100GHz'
54    vd = VoltageDomain(voltage='1V')
55    system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
56    # add traffic generators to the system
57    system.tgen = [TrafficGen(config_file=options.tgen_cfg_file) for i in
58                   xrange(options.num_tgen)]
59    # Config memory system with given HMC arch
60    MemConfig.config_mem(options, system)
61    # Connect the traffic generatiors
62    if options.arch == "distributed":
63        for i in xrange(options.num_tgen):
64            system.tgen[i].port = system.membus.slave
65        # connect the system port even if it is not used in this example
66        system.system_port = system.membus.slave
67    if options.arch == "mixed":
68        for i in xrange(int(options.num_tgen/2)):
69            system.tgen[i].port = system.membus.slave
70        hh = system.hmc_host
71        if options.enable_global_monitor:
72            system.tgen[2].port = hh.lmonitor[2].slave
73            hh.lmonitor[2].master = hh.seriallink[2].slave
74            system.tgen[3].port = hh.lmonitor[3].slave
75            hh.lmonitor[3].master = hh.seriallink[3].slave
76        else:
77            system.tgen[2].port = hh.seriallink[2].slave
78            system.tgen[3].port = hh.seriallink[3].slave
79        # connect the system port even if it is not used in this example
80        system.system_port = system.membus.slave
81    if options.arch == "same":
82        hh = system.hmc_host
83        for i in xrange(options.num_links_controllers):
84            if options.enable_global_monitor:
85                system.tgen[i].port = hh.lmonitor[i].slave
86            else:
87                system.tgen[i].port = hh.seriallink[i].slave
88    # set up the root SimObject
89    root = Root(full_system=False, system=system)
90    return root
91
92
93def main():
94    parser = argparse.ArgumentParser(description="Simple system using HMC as\
95                                     main memory")
96    HMC.add_options(parser)
97    add_options(parser)
98    options = parser.parse_args()
99    # build the system
100    root = build_system(options)
101    # instantiate all of the objects we've created so far
102    m5.instantiate()
103    print "Beginning simulation!"
104    event = m5.simulate(10000000000)
105    m5.stats.dump()
106    print 'Exiting @ tick %i because %s (exit code is %i)' % (m5.curTick(),
107                                                              event.getCause(),
108                                                              event.getCode())
109    print "Done"
110
111
112if __name__ == "__m5_main__":
113    main()
114