hmctest.py revision 11552:354e5631a6c1
1import optparse 2import sys 3import subprocess 4 5import m5 6from m5.objects import * 7from m5.util import addToPath 8 9addToPath('../common') 10import MemConfig 11import HMC 12 13parser = optparse.OptionParser() 14 15# Use a HMC_2500_x32 by default 16parser.add_option("--mem-type", type = "choice", default = "HMC_2500_x32", 17 choices = MemConfig.mem_names(), 18 help = "type of memory to use") 19 20parser.add_option("--ranks", "-r", type = "int", default = 1, 21 help = "Number of ranks to iterate across") 22 23parser.add_option("--rd_perc", type ="int", default=100, 24 help = "Percentage of read commands") 25 26parser.add_option("--mode", type ="choice", default ="DRAM", 27 choices = ["DRAM", "DRAM_ROTATE", "RANDOM"], 28 help = "DRAM: Random traffic; \ 29 DRAM_ROTATE: Traffic rotating across banks and ranks" 30 ) 31 32parser.add_option("--addr_map", type ="int", default = 1, 33 help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo") 34 35parser.add_option("--arch", type = "choice", default = "distributed", 36 choices = ["same", "distributed", "mixed"], 37 help = "same: HMC-4 links with same range\ 38 distributed: HMC-4 links with distributed range\ 39 mixed: mixed with same & distributed range") 40 41parser.add_option("--linkaggr", type = "int", default = 0, 42 help = "1: enable link crossbar, 0: disable link crossbar") 43 44parser.add_option("--num_cross", type = "int", default = 4, 45 help = "1: number of crossbar in HMC=1;\ 46 4: number of crossbar = 4") 47 48parser.add_option("--tlm-memory", type = "string", 49 help="use external port for SystemC TLM cosimulation") 50 51parser.add_option("--elastic-trace-en", action ="store_true", 52 help = """Enable capture of data dependency and instruction 53 fetch traces using elastic trace probe.""") 54 55(options, args) = parser.parse_args() 56 57if args: 58 print "Error: script doesn't take any positional arguments" 59 sys.exit(1) 60 61system = System() 62system.clk_domain = SrcClockDomain(clock='100GHz', 63 voltage_domain= 64 VoltageDomain(voltage = '1V')) 65# Create additional crossbar for arch1 66if options.arch == "distributed" or options.arch == "mixed" : 67 system.membus = NoncoherentXBar( width=8 ) 68 system.membus.badaddr_responder = BadAddr() 69 system.membus.default = Self.badaddr_responder.pio 70 system.membus.width = 8 71 system.membus.frontend_latency = 3 72 system.membus.forward_latency = 4 73 system.membus.response_latency = 2 74 75 system.membus.clk_domain = SrcClockDomain(clock='100GHz', voltage_domain= 76 VoltageDomain(voltage = '1V')) 77 78# we are considering 4GB HMC device with following parameters 79# hmc_device_size = '4GB' 80# hmc_num_vaults = 16 81# hmc_vault_size = '256MB' 82# hmc_stack_size = 8 83# hmc_bank_in_stack = 2 84# hmc_bank_size = '16MB' 85# hmc_bank_in_vault = 16 86 87# determine the burst length in bytes 88burst_size = 256 89num_serial_links = 4 90num_vault_ctrl = 16 91options.mem_channels = 1 92options.external_memory_system = 0 93options.mem_ranks=1 94stride_size = burst_size 95system.cache_line_size = burst_size 96 97# Enable performance monitoring 98options.enable_global_monitor = True 99options.enable_link_monitor = False 100 101# Bytes used for calculations 102oneGBytes = 1024 * 1024 * 1024 103oneMBytes = 1024 * 1024 104 105# Memory ranges of 16 vault controller - Total_HMC_size / 16 106mem_range_vault = [ AddrRange(i * 256 * oneMBytes, ((i + 1) * 256 * oneMBytes) 107 - 1) 108 for i in range(num_vault_ctrl)] 109 110# Memmory ranges of serial link for arch-0 111# Same as the ranges of vault controllers - 4 vault - to - 1 serial link 112if options.arch == "same": 113 ser_range = [ AddrRange(0, (4 * oneGBytes) - 1) 114 for i in range(num_serial_links)] 115 options.ser_ranges = ser_range 116 117# Memmory ranges of serial link for arch-1 118# Distributed range accross links 119if options.arch == "distributed": 120 ser_range = [ AddrRange(i * oneGBytes, ((i + 1) * oneGBytes) - 1) 121 for i in range(num_serial_links)] 122 options.ser_ranges = ser_range 123 124# Memmory ranges of serial link for arch-2 125# "Mixed" address distribution over links 126if options.arch == "mixed": 127 ser_range0 = AddrRange(0 , (1 * oneGBytes) - 1) 128 ser_range1 = AddrRange(1 * oneGBytes , (2 * oneGBytes) - 1) 129 ser_range2 = AddrRange(0 , (4 * oneGBytes) - 1) 130 ser_range3 = AddrRange(0 , (4 * oneGBytes) - 1) 131 options.ser_ranges = [ser_range0, ser_range1, ser_range2, ser_range3] 132 133# Assign ranges of vault controller to system ranges 134system.mem_ranges = mem_range_vault 135 136# open traffic generator 137cfg_file_name = "./tests/quick/se/70.tgen/traffic.cfg" 138cfg_file = open(cfg_file_name, 'r') 139 140# number of traffic generator 141np = 4 142# create a traffic generator, and point it to the file we just created 143system.tgen = [ TrafficGen(config_file = cfg_file_name) for i in xrange(np)] 144 145# Config memory system with given HMC arch 146MemConfig.config_mem(options, system) 147 148if options.arch == "distributed": 149 for i in xrange(np): 150 system.tgen[i].port = system.membus.slave 151 # connect the system port even if it is not used in this example 152 system.system_port = system.membus.slave 153 154if options.arch == "mixed": 155 for i in xrange(int(np/2)): 156 system.tgen[i].port = system.membus.slave 157 # connect the system port even if it is not used in this example 158 system.system_port = system.membus.slave 159 160 161# run Forrest, run! 162root = Root(full_system = False, system = system) 163root.system.mem_mode = 'timing' 164 165m5.instantiate() 166m5.simulate(10000000000) 167 168m5.stats.dump() 169 170print "Done!" 171