hmctest.py revision 12340
111552Sabdul.mutaal@gmail.comimport sys
212340Szulian@eit.uni-kl.deimport argparse
311552Sabdul.mutaal@gmail.comimport subprocess
412340Szulian@eit.uni-kl.defrom pprint import pprint
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611552Sabdul.mutaal@gmail.comimport m5
711552Sabdul.mutaal@gmail.comfrom m5.objects import *
812340Szulian@eit.uni-kl.defrom m5.util import *
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1011682Sandreas.hansson@arm.comaddToPath('../')
1111682Sandreas.hansson@arm.com
1211682Sandreas.hansson@arm.comfrom common import MemConfig
1311682Sandreas.hansson@arm.comfrom common import HMC
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1612340Szulian@eit.uni-kl.dedef add_options(parser):
1712340Szulian@eit.uni-kl.de    parser.add_argument("--external-memory-system", default=0, action="store",
1812340Szulian@eit.uni-kl.de                        type=int, help="External memory system")
1912340Szulian@eit.uni-kl.de    # TLM related options, currently optional in configs/common/MemConfig.py
2012340Szulian@eit.uni-kl.de    parser.add_argument("--tlm-memory", action="store_true", help="use\
2112340Szulian@eit.uni-kl.de                        external port for SystemC TLM co-simulation. Default:\
2212340Szulian@eit.uni-kl.de                        no")
2312340Szulian@eit.uni-kl.de    # Elastic traces related options, currently optional in
2412340Szulian@eit.uni-kl.de    # configs/common/MemConfig.py
2512340Szulian@eit.uni-kl.de    parser.add_argument("--elastic-trace-en", action="store_true",
2612340Szulian@eit.uni-kl.de                        help="enable capture of data dependency and\
2712340Szulian@eit.uni-kl.de                        instruction fetch traces using elastic trace\
2812340Szulian@eit.uni-kl.de                        probe.\nDefault: no")
2912340Szulian@eit.uni-kl.de    # Options related to traffic generation
3012340Szulian@eit.uni-kl.de    parser.add_argument("--num-tgen", default=4, action="store", type=int,
3112340Szulian@eit.uni-kl.de                        choices=[4], help="number of traffic generators.\
3212340Szulian@eit.uni-kl.de                        Right now this script supports only 4.\nDefault: 4")
3312340Szulian@eit.uni-kl.de    parser.add_argument("--tgen-cfg-file",
3412340Szulian@eit.uni-kl.de                        default="./configs/example/hmc_tgen.cfg",
3512340Szulian@eit.uni-kl.de                        type=str, help="Traffic generator(s) configuration\
3612340Szulian@eit.uni-kl.de                        file. Note: this script uses the same configuration\
3712340Szulian@eit.uni-kl.de                        file for all traffic generators")
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4012340Szulian@eit.uni-kl.de# considering 4GB HMC device with following parameters
4111552Sabdul.mutaal@gmail.com# hmc_device_size = '4GB'
4211552Sabdul.mutaal@gmail.com# hmc_vault_size = '256MB'
4311552Sabdul.mutaal@gmail.com# hmc_stack_size = 8
4411552Sabdul.mutaal@gmail.com# hmc_bank_in_stack = 2
4511552Sabdul.mutaal@gmail.com# hmc_bank_size = '16MB'
4611552Sabdul.mutaal@gmail.com# hmc_bank_in_vault = 16
4712340Szulian@eit.uni-kl.dedef build_system(options):
4812340Szulian@eit.uni-kl.de    # create the system we are going to simulate
4912340Szulian@eit.uni-kl.de    system = System()
5012340Szulian@eit.uni-kl.de    # use timing mode for the interaction between master-slave ports
5112340Szulian@eit.uni-kl.de    system.mem_mode = 'timing'
5212340Szulian@eit.uni-kl.de    # set the clock fequency of the system
5312340Szulian@eit.uni-kl.de    clk = '100GHz'
5412340Szulian@eit.uni-kl.de    vd = VoltageDomain(voltage='1V')
5512340Szulian@eit.uni-kl.de    system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
5612340Szulian@eit.uni-kl.de    # add traffic generators to the system
5712340Szulian@eit.uni-kl.de    system.tgen = [TrafficGen(config_file=options.tgen_cfg_file) for i in
5812340Szulian@eit.uni-kl.de                   xrange(options.num_tgen)]
5912340Szulian@eit.uni-kl.de    # Config memory system with given HMC arch
6012340Szulian@eit.uni-kl.de    MemConfig.config_mem(options, system)
6112340Szulian@eit.uni-kl.de    # Connect the traffic generatiors
6212340Szulian@eit.uni-kl.de    if options.arch == "distributed":
6312340Szulian@eit.uni-kl.de        for i in xrange(options.num_tgen):
6412340Szulian@eit.uni-kl.de            system.tgen[i].port = system.membus.slave
6512340Szulian@eit.uni-kl.de        # connect the system port even if it is not used in this example
6612340Szulian@eit.uni-kl.de        system.system_port = system.membus.slave
6712340Szulian@eit.uni-kl.de    if options.arch == "mixed":
6812340Szulian@eit.uni-kl.de        for i in xrange(int(options.num_tgen/2)):
6912340Szulian@eit.uni-kl.de            system.tgen[i].port = system.membus.slave
7012340Szulian@eit.uni-kl.de        hh = system.hmc_host
7112340Szulian@eit.uni-kl.de        if options.enable_global_monitor:
7212340Szulian@eit.uni-kl.de            system.tgen[2].port = hh.lmonitor[2].slave
7312340Szulian@eit.uni-kl.de            hh.lmonitor[2].master = hh.seriallink[2].slave
7412340Szulian@eit.uni-kl.de            system.tgen[3].port = hh.lmonitor[3].slave
7512340Szulian@eit.uni-kl.de            hh.lmonitor[3].master = hh.seriallink[3].slave
7612340Szulian@eit.uni-kl.de        else:
7712340Szulian@eit.uni-kl.de            system.tgen[2].port = hh.seriallink[2].slave
7812340Szulian@eit.uni-kl.de            system.tgen[3].port = hh.seriallink[3].slave
7912340Szulian@eit.uni-kl.de        # connect the system port even if it is not used in this example
8012340Szulian@eit.uni-kl.de        system.system_port = system.membus.slave
8112340Szulian@eit.uni-kl.de    if options.arch == "same":
8212340Szulian@eit.uni-kl.de        hh = system.hmc_host
8312340Szulian@eit.uni-kl.de        for i in xrange(options.num_links_controllers):
8412340Szulian@eit.uni-kl.de            if options.enable_global_monitor:
8512340Szulian@eit.uni-kl.de                system.tgen[i].port = hh.lmonitor[i].slave
8612340Szulian@eit.uni-kl.de            else:
8712340Szulian@eit.uni-kl.de                system.tgen[i].port = hh.seriallink[i].slave
8812340Szulian@eit.uni-kl.de    # set up the root SimObject
8912340Szulian@eit.uni-kl.de    root = Root(full_system=False, system=system)
9012340Szulian@eit.uni-kl.de    return root
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9312340Szulian@eit.uni-kl.dedef main():
9412340Szulian@eit.uni-kl.de    parser = argparse.ArgumentParser(description="Simple system using HMC as\
9512340Szulian@eit.uni-kl.de                                     main memory")
9612340Szulian@eit.uni-kl.de    HMC.add_options(parser)
9712340Szulian@eit.uni-kl.de    add_options(parser)
9812340Szulian@eit.uni-kl.de    options = parser.parse_args()
9912340Szulian@eit.uni-kl.de    # build the system
10012340Szulian@eit.uni-kl.de    root = build_system(options)
10112340Szulian@eit.uni-kl.de    # instantiate all of the objects we've created so far
10212340Szulian@eit.uni-kl.de    m5.instantiate()
10312340Szulian@eit.uni-kl.de    print "Beginning simulation!"
10412340Szulian@eit.uni-kl.de    event = m5.simulate(10000000000)
10512340Szulian@eit.uni-kl.de    m5.stats.dump()
10612340Szulian@eit.uni-kl.de    print 'Exiting @ tick %i because %s (exit code is %i)' % (m5.curTick(),
10712340Szulian@eit.uni-kl.de                                                              event.getCause(),
10812340Szulian@eit.uni-kl.de                                                              event.getCode())
10912340Szulian@eit.uni-kl.de    print "Done"
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11212340Szulian@eit.uni-kl.deif __name__ == "__m5_main__":
11312340Szulian@eit.uni-kl.de    main()
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