hmc_hello.py revision 13774
12810SN/A# Copyright (c) 2017, University of Kaiserslautern 212728Snikos.nikoleris@arm.com# All rights reserved. 39796Sprakash.ramrakhyani@arm.com# 49796Sprakash.ramrakhyani@arm.com# Redistribution and use in source and binary forms, with or without 59796Sprakash.ramrakhyani@arm.com# modification, are permitted provided that the following conditions are 69796Sprakash.ramrakhyani@arm.com# met: 79796Sprakash.ramrakhyani@arm.com# 89796Sprakash.ramrakhyani@arm.com# 1. Redistributions of source code must retain the above copyright notice, 99796Sprakash.ramrakhyani@arm.com# this list of conditions and the following disclaimer. 109796Sprakash.ramrakhyani@arm.com# 119796Sprakash.ramrakhyani@arm.com# 2. Redistributions in binary form must reproduce the above copyright 129796Sprakash.ramrakhyani@arm.com# notice, this list of conditions and the following disclaimer in the 139796Sprakash.ramrakhyani@arm.com# documentation and/or other materials provided with the distribution. 142810SN/A# 152810SN/A# 3. Neither the name of the copyright holder nor the names of its 162810SN/A# contributors may be used to endorse or promote products derived from 172810SN/A# this software without specific prior written permission. 182810SN/A# 192810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 202810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 212810SN/A# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 222810SN/A# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER 232810SN/A# OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 242810SN/A# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 252810SN/A# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 262810SN/A# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 272810SN/A# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 282810SN/A# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 292810SN/A# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 302810SN/A# 312810SN/A# Author: Éder F. Zulian 322810SN/A 332810SN/Afrom __future__ import print_function 342810SN/Afrom __future__ import absolute_import 352810SN/A 362810SN/Aimport sys 372810SN/Aimport argparse 382810SN/A 392810SN/Aimport m5 402810SN/Afrom m5.objects import * 412810SN/Afrom m5.util import * 422810SN/AaddToPath('../') 432810SN/Afrom common import MemConfig 442810SN/Afrom common import HMC 452810SN/A 462810SN/A 472810SN/Apd = "Simple 'hello world' example using HMC as main memory" 482810SN/Aparser = argparse.ArgumentParser(description=pd) 4911486Snikos.nikoleris@arm.comHMC.add_options(parser) 5011486Snikos.nikoleris@arm.comoptions = parser.parse_args() 5112727Snikos.nikoleris@arm.com# create the system we are going to simulate 5212727Snikos.nikoleris@arm.comsystem = System() 5312727Snikos.nikoleris@arm.com# use timing mode for the interaction between master-slave ports 545338Sstever@gmail.comsystem.mem_mode = 'timing' 5512727Snikos.nikoleris@arm.com# set the clock fequency of the system 5612727Snikos.nikoleris@arm.comclk = '1GHz' 572810SN/Avd = VoltageDomain(voltage='1V') 5812727Snikos.nikoleris@arm.comsystem.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd) 592810SN/A# create a simple CPU 609796Sprakash.ramrakhyani@arm.comsystem.cpu = TimingSimpleCPU() 6111893Snikos.nikoleris@arm.com# config memory system 6211893Snikos.nikoleris@arm.comMemConfig.config_mem(options, system) 6311722Ssophiane.senni@gmail.com# hook the CPU ports up to the membus 6411722Ssophiane.senni@gmail.comsystem.cpu.icache_port = system.membus.slave 6511722Ssophiane.senni@gmail.comsystem.cpu.dcache_port = system.membus.slave 6611722Ssophiane.senni@gmail.com# create the interrupt controller for the CPU and connect to the membus 6712513Sodanrc@yahoo.com.brsystem.cpu.createInterruptController() 6812513Sodanrc@yahoo.com.br# connect special port in the system to the membus. This port is a 6912629Sodanrc@yahoo.com.br# functional-only port to allow the system to read and write memory. 7012629Sodanrc@yahoo.com.brsystem.system_port = system.membus.slave 719796Sprakash.ramrakhyani@arm.com# get ISA for the binary to run. 729796Sprakash.ramrakhyani@arm.comisa = str(m5.defines.buildEnv['TARGET_ISA']).lower() 739796Sprakash.ramrakhyani@arm.com# run 'hello' and use the compiled ISA to find the binary 742810SN/Abinary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello' 752810SN/A# create a process for a simple "Hello World" application 762810SN/Aprocess = Process() 7710360Sandreas.hansson@arm.com# cmd is a list which begins with the executable (like argv) 782810SN/Aprocess.cmd = [binary] 792810SN/A# set the cpu workload 802810SN/Asystem.cpu.workload = process 8113217Sodanrc@yahoo.com.br# create thread contexts 8213217Sodanrc@yahoo.com.brsystem.cpu.createThreads() 8313217Sodanrc@yahoo.com.br# set up the root SimObject 8413217Sodanrc@yahoo.com.brroot = Root(full_system=False, system=system) 8513217Sodanrc@yahoo.com.brm5.instantiate() 8613217Sodanrc@yahoo.com.brm5.simulate() 8713217Sodanrc@yahoo.com.br