hmc_hello.py revision 12340
110447Snilay@cs.wisc.edu# Copyright (c) 2017, University of Kaiserslautern
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3110447Snilay@cs.wisc.edu# Author: Éder F. Zulian
3210447Snilay@cs.wisc.edu
3310447Snilay@cs.wisc.eduimport sys
3410447Snilay@cs.wisc.eduimport argparse
3510447Snilay@cs.wisc.edu
3610447Snilay@cs.wisc.eduimport m5
3710447Snilay@cs.wisc.edufrom m5.objects import *
3810447Snilay@cs.wisc.edufrom m5.util import *
3910447Snilay@cs.wisc.eduaddToPath('../')
4010447Snilay@cs.wisc.edufrom common import MemConfig
4110447Snilay@cs.wisc.edufrom common import HMC
4210447Snilay@cs.wisc.edu
4310447Snilay@cs.wisc.edu
4410447Snilay@cs.wisc.edupd = "Simple 'hello world' example using HMC as main memory"
4510447Snilay@cs.wisc.eduparser = argparse.ArgumentParser(description=pd)
4610447Snilay@cs.wisc.eduHMC.add_options(parser)
4710447Snilay@cs.wisc.eduoptions = parser.parse_args()
4810447Snilay@cs.wisc.edu# create the system we are going to simulate
4910447Snilay@cs.wisc.edusystem = System()
5010447Snilay@cs.wisc.edu# use timing mode for the interaction between master-slave ports
5110447Snilay@cs.wisc.edusystem.mem_mode = 'timing'
5210447Snilay@cs.wisc.edu# set the clock fequency of the system
5310447Snilay@cs.wisc.educlk = '1GHz'
5410447Snilay@cs.wisc.eduvd = VoltageDomain(voltage='1V')
5510447Snilay@cs.wisc.edusystem.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
5610447Snilay@cs.wisc.edu# create a simple CPU
5710447Snilay@cs.wisc.edusystem.cpu = TimingSimpleCPU()
5810447Snilay@cs.wisc.edu# config memory system
5910447Snilay@cs.wisc.eduMemConfig.config_mem(options, system)
6010447Snilay@cs.wisc.edu# hook the CPU ports up to the membus
6110447Snilay@cs.wisc.edusystem.cpu.icache_port = system.membus.slave
6210447Snilay@cs.wisc.edusystem.cpu.dcache_port = system.membus.slave
6310447Snilay@cs.wisc.edu# create the interrupt controller for the CPU and connect to the membus
6410447Snilay@cs.wisc.edusystem.cpu.createInterruptController()
6510447Snilay@cs.wisc.edu# connect special port in the system to the membus. This port is a
6610447Snilay@cs.wisc.edu# functional-only port to allow the system to read and write memory.
6710447Snilay@cs.wisc.edusystem.system_port = system.membus.slave
6810447Snilay@cs.wisc.edu# get ISA for the binary to run.
6910447Snilay@cs.wisc.eduisa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
7010447Snilay@cs.wisc.edu# run 'hello' and use the compiled ISA to find the binary
7110447Snilay@cs.wisc.edubinary = 'tests/test-progs/hello/bin/' + isa + '/linux/hello'
7210447Snilay@cs.wisc.edu# create a process for a simple "Hello World" application
7310447Snilay@cs.wisc.eduprocess = Process()
7410447Snilay@cs.wisc.edu# cmd is a list which begins with the executable (like argv)
7510447Snilay@cs.wisc.eduprocess.cmd = [binary]
7610447Snilay@cs.wisc.edu# set the cpu workload
7710447Snilay@cs.wisc.edusystem.cpu.workload = process
7810447Snilay@cs.wisc.edu# create thread contexts
7910447Snilay@cs.wisc.edusystem.cpu.createThreads()
8010447Snilay@cs.wisc.edu# set up the root SimObject
8110447Snilay@cs.wisc.eduroot = Root(full_system=False, system=system)
8210447Snilay@cs.wisc.edum5.instantiate()
8310447Snilay@cs.wisc.edum5.simulate()
8410447Snilay@cs.wisc.edu