fs.py revision 9653
18926Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited
27586SAli.Saidi@arm.com# All rights reserved.
37586SAli.Saidi@arm.com#
47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall
57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual
67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating
77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software
87586SAli.Saidi@arm.com# licensed hereunder.  You may use the software subject to the license
97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated
107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software,
117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form.
127586SAli.Saidi@arm.com#
133970Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan
143005Sstever@eecs.umich.edu# All rights reserved.
153005Sstever@eecs.umich.edu#
163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without
173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are
183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright
193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer;
203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright
213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the
223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution;
233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its
243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from
253005Sstever@eecs.umich.edu# this software without specific prior written permission.
263005Sstever@eecs.umich.edu#
273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
293005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
303005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
313005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
323005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
333005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
343005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
353005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
363005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
373005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
383005Sstever@eecs.umich.edu#
393005Sstever@eecs.umich.edu# Authors: Ali Saidi
403005Sstever@eecs.umich.edu
416654Snate@binkert.orgimport optparse
426654Snate@binkert.orgimport sys
432889SN/A
442710SN/Aimport m5
456654Snate@binkert.orgfrom m5.defines import buildEnv
466654Snate@binkert.orgfrom m5.objects import *
476654Snate@binkert.orgfrom m5.util import addToPath, fatal
485457Ssaidi@eecs.umich.edu
496654Snate@binkert.orgaddToPath('../common')
506654Snate@binkert.org
512934SN/Afrom FSConfig import *
522549SN/Afrom SysPaths import *
532995SN/Afrom Benchmarks import *
543395Shsul@eecs.umich.eduimport Simulation
556981SLisa.Hsu@amd.comimport CacheConfig
563448Shsul@eecs.umich.edufrom Caches import *
578920Snilay@cs.wisc.eduimport Options
583444Sktlim@umich.edu
592889SN/Aparser = optparse.OptionParser()
608920Snilay@cs.wisc.eduOptions.addCommonOptions(parser)
618920Snilay@cs.wisc.eduOptions.addFSOptions(parser)
623322Shsul@eecs.umich.edu
632710SN/A(options, args) = parser.parse_args()
642710SN/A
652710SN/Aif args:
662710SN/A    print "Error: script doesn't take any positional arguments"
672710SN/A    sys.exit(1)
682710SN/A
693322Shsul@eecs.umich.edu# driver system CPU is always simple... note this is an assignment of
703304Sstever@eecs.umich.edu# a class, not an instance.
713322Shsul@eecs.umich.eduDriveCPUClass = AtomicSimpleCPU
723322Shsul@eecs.umich.edudrive_mem_mode = 'atomic'
733304Sstever@eecs.umich.edu
749653SAndreas.Sandberg@ARM.com# Check if KVM support has been enabled, we might need to do VM
759653SAndreas.Sandberg@ARM.com# configuration if that's the case.
769653SAndreas.Sandberg@ARM.comhave_kvm_support = 'BaseKvmCPU' in globals()
779653SAndreas.Sandberg@ARM.comdef is_kvm_cpu(cpu_class):
789653SAndreas.Sandberg@ARM.com    return have_kvm_support and cpu_class != None and \
799653SAndreas.Sandberg@ARM.com        issubclass(cpu_class, BaseKvmCPU)
809653SAndreas.Sandberg@ARM.com
813481Shsul@eecs.umich.edu# system under test can be any CPU
823481Shsul@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
832566SN/A
849129Sandreas.hansson@arm.comTestCPUClass.clock = options.clock
859129Sandreas.hansson@arm.comDriveCPUClass.clock = options.clock
862995SN/A
872995SN/Aif options.benchmark:
883304Sstever@eecs.umich.edu    try:
893304Sstever@eecs.umich.edu        bm = Benchmarks[options.benchmark]
903304Sstever@eecs.umich.edu    except KeyError:
912995SN/A        print "Error benchmark %s has not been defined." % options.benchmark
922995SN/A        print "Valid benchmarks are: %s" % DefinedBenchmarks
932995SN/A        sys.exit(1)
942917SN/Aelse:
952995SN/A    if options.dual:
968956Sjayneel@cs.wisc.edu        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
972995SN/A    else:
988956Sjayneel@cs.wisc.edu        bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
993304Sstever@eecs.umich.edu
1006135Sgblack@eecs.umich.edunp = options.num_cpus
1016135Sgblack@eecs.umich.edu
1026654Snate@binkert.orgif buildEnv['TARGET_ISA'] == "alpha":
1033819Shsul@eecs.umich.edu    test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
1046654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "mips":
1055222Sksewell@umich.edu    test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
1066654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "sparc":
1073819Shsul@eecs.umich.edu    test_sys = makeSparcSystem(test_mem_mode, bm[0])
1086654Snate@binkert.orgelif buildEnv['TARGET_ISA'] == "x86":
1097925Sgblack@eecs.umich.edu    test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
1107586SAli.Saidi@arm.comelif buildEnv['TARGET_ISA'] == "arm":
1119539Satgutier@umich.edu    test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
1129539Satgutier@umich.edu            options.dtb_filename, bare_metal=options.bare_metal)
1133819Shsul@eecs.umich.eduelse:
1149059Snilay@cs.wisc.edu    fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
1153819Shsul@eecs.umich.edu
1163873Sbinkertn@umich.eduif options.kernel is not None:
1173873Sbinkertn@umich.edu    test_sys.kernel = binary(options.kernel)
1183873Sbinkertn@umich.edu
1193873Sbinkertn@umich.eduif options.script is not None:
1203873Sbinkertn@umich.edu    test_sys.readfile = options.script
1213873Sbinkertn@umich.edu
1228659SAli.Saidi@ARM.comtest_sys.init_param = options.init_param
1238659SAli.Saidi@ARM.com
1246995Sgblack@eecs.umich.edutest_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
1253668Srdreslin@umich.edu
1269653SAndreas.Sandberg@ARM.comif is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
1279653SAndreas.Sandberg@ARM.com    test_sys.vm = KvmVM()
1289653SAndreas.Sandberg@ARM.com
1296636Ssteve.reinhardt@amd.comif options.caches or options.l2cache:
1309288Sandreas.hansson@arm.com    test_sys.iocache = IOCache(clock = '1GHz',
1319408Sandreas.hansson@arm.com                               addr_ranges = test_sys.mem_ranges)
1328839Sandreas.hansson@arm.com    test_sys.iocache.cpu_side = test_sys.iobus.master
1338839Sandreas.hansson@arm.com    test_sys.iocache.mem_side = test_sys.membus.slave
1348713Sandreas.hansson@arm.comelse:
1359408Sandreas.hansson@arm.com    test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
1368839Sandreas.hansson@arm.com    test_sys.iobridge.slave = test_sys.iobus.master
1378839Sandreas.hansson@arm.com    test_sys.iobridge.master = test_sys.membus.slave
1385142Ssaidi@eecs.umich.edu
1398926Sandreas.hansson@arm.com# Sanity check
1409317Sandreas.hansson@arm.comif options.fastmem:
1419317Sandreas.hansson@arm.com    if TestCPUClass != AtomicSimpleCPU:
1429317Sandreas.hansson@arm.com        fatal("Fastmem can only be used with atomic CPU!")
1439317Sandreas.hansson@arm.com    if (options.caches or options.l2cache):
1449317Sandreas.hansson@arm.com        fatal("You cannot use fastmem in combination with caches!")
1458926Sandreas.hansson@arm.com
1463312Sstever@eecs.umich.edufor i in xrange(np):
1474968Sacolyte@umich.edu    if options.fastmem:
1488926Sandreas.hansson@arm.com        test_sys.cpu[i].fastmem = True
1498887Sgeoffrey.blake@arm.com    if options.checker:
1508887Sgeoffrey.blake@arm.com        test_sys.cpu[i].addCheckerCpu()
1519384SAndreas.Sandberg@arm.com    test_sys.cpu[i].createThreads()
1528887Sgeoffrey.blake@arm.com
1538887Sgeoffrey.blake@arm.comCacheConfig.config_cache(options, test_sys)
1544968Sacolyte@umich.edu
1553005Sstever@eecs.umich.eduif len(bm) == 2:
1566654Snate@binkert.org    if buildEnv['TARGET_ISA'] == 'alpha':
1573819Shsul@eecs.umich.edu        drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
1586654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'mips':
1595222Sksewell@umich.edu        drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
1606654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'sparc':
1613819Shsul@eecs.umich.edu        drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
1626654Snate@binkert.org    elif buildEnv['TARGET_ISA'] == 'x86':
1636135Sgblack@eecs.umich.edu        drive_sys = makeX86System(drive_mem_mode, np, bm[1])
1647586SAli.Saidi@arm.com    elif buildEnv['TARGET_ISA'] == 'arm':
1658661SAli.Saidi@ARM.com        drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
1668661SAli.Saidi@ARM.com
1673322Shsul@eecs.umich.edu    drive_sys.cpu = DriveCPUClass(cpu_id=0)
1689384SAndreas.Sandberg@arm.com    drive_sys.cpu.createThreads()
1698863Snilay@cs.wisc.edu    drive_sys.cpu.createInterruptController()
1707876Sgblack@eecs.umich.edu    drive_sys.cpu.connectAllPorts(drive_sys.membus)
1714968Sacolyte@umich.edu    if options.fastmem:
1728926Sandreas.hansson@arm.com        drive_sys.cpu.fastmem = True
1734837Ssaidi@eecs.umich.edu    if options.kernel is not None:
1744837Ssaidi@eecs.umich.edu        drive_sys.kernel = binary(options.kernel)
1759408Sandreas.hansson@arm.com
1769653SAndreas.Sandberg@ARM.com    if is_kvm_cpu(DriveCPUClass):
1779653SAndreas.Sandberg@ARM.com        drive_sys.vm = KvmVM()
1789653SAndreas.Sandberg@ARM.com
1799164Sandreas.hansson@arm.com    drive_sys.iobridge = Bridge(delay='50ns',
1809408Sandreas.hansson@arm.com                                ranges = drive_sys.mem_ranges)
1818845Sandreas.hansson@arm.com    drive_sys.iobridge.slave = drive_sys.iobus.master
1828845Sandreas.hansson@arm.com    drive_sys.iobridge.master = drive_sys.membus.slave
1834837Ssaidi@eecs.umich.edu
1848659SAli.Saidi@ARM.com    drive_sys.init_param = options.init_param
1858801Sgblack@eecs.umich.edu    root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
1863005Sstever@eecs.umich.eduelif len(bm) == 1:
1878801Sgblack@eecs.umich.edu    root = Root(full_system=True, system=test_sys)
1883005Sstever@eecs.umich.eduelse:
1893005Sstever@eecs.umich.edu    print "Error I don't know how to create more than 2 systems."
1903005Sstever@eecs.umich.edu    sys.exit(1)
1912566SN/A
1927861Sgblack@eecs.umich.eduif options.timesync:
1937861Sgblack@eecs.umich.edu    root.time_sync_enable = True
1947861Sgblack@eecs.umich.edu
1958635Schris.emmons@arm.comif options.frame_capture:
1968635Schris.emmons@arm.com    VncServer.frame_capture = True
1978635Schris.emmons@arm.com
1989061Snilay@cs.wisc.eduSimulation.setWorkCountOptions(test_sys, options)
1993481Shsul@eecs.umich.eduSimulation.run(options, root, test_sys, FutureClass)
200