fs.py revision 9653
13970Sgblack@eecs.umich.edu# Copyright (c) 2010-2012 ARM Limited 23005Sstever@eecs.umich.edu# All rights reserved. 33005Sstever@eecs.umich.edu# 43005Sstever@eecs.umich.edu# The license below extends only to copyright in the software and shall 53005Sstever@eecs.umich.edu# not be construed as granting a license to any other intellectual 63005Sstever@eecs.umich.edu# property including but not limited to intellectual property relating 73005Sstever@eecs.umich.edu# to a hardware implementation of the functionality of the software 83005Sstever@eecs.umich.edu# licensed hereunder. You may use the software subject to the license 93005Sstever@eecs.umich.edu# terms below provided that you ensure that this notice is replicated 103005Sstever@eecs.umich.edu# unmodified and in its entirety in all distributions of the software, 113005Sstever@eecs.umich.edu# modified or unmodified, in source code or in binary form. 123005Sstever@eecs.umich.edu# 133005Sstever@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 143005Sstever@eecs.umich.edu# All rights reserved. 153005Sstever@eecs.umich.edu# 163005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 173005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 183005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 193005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 203005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 213005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 223005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 233005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 243005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 253005Sstever@eecs.umich.edu# this software without specific prior written permission. 263005Sstever@eecs.umich.edu# 273005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 283005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292889SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302889SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312710SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322710SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332934SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342934SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352549SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362995SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 373395Shsul@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 383448Shsul@eecs.umich.edu# 392549SN/A# Authors: Ali Saidi 403088Sstever@eecs.umich.edu 413088Sstever@eecs.umich.eduimport optparse 423088Sstever@eecs.umich.eduimport sys 433444Sktlim@umich.edu 443444Sktlim@umich.eduimport m5 453444Sktlim@umich.edufrom m5.defines import buildEnv 463444Sktlim@umich.edufrom m5.objects import * 472889SN/Afrom m5.util import addToPath, fatal 482710SN/A 493873Sbinkertn@umich.eduaddToPath('../common') 503873Sbinkertn@umich.edu 513873Sbinkertn@umich.edufrom FSConfig import * 523873Sbinkertn@umich.edufrom SysPaths import * 533322Shsul@eecs.umich.edufrom Benchmarks import * 542995SN/Aimport Simulation 552995SN/Aimport CacheConfig 562995SN/Afrom Caches import * 572995SN/Aimport Options 582995SN/A 593143Shsul@eecs.umich.eduparser = optparse.OptionParser() 603322Shsul@eecs.umich.eduOptions.addCommonOptions(parser) 613322Shsul@eecs.umich.eduOptions.addFSOptions(parser) 623025Ssaidi@eecs.umich.edu 633143Shsul@eecs.umich.edu(options, args) = parser.parse_args() 643143Shsul@eecs.umich.edu 653322Shsul@eecs.umich.eduif args: 663444Sktlim@umich.edu print "Error: script doesn't take any positional arguments" 673322Shsul@eecs.umich.edu sys.exit(1) 682710SN/A 692710SN/A# driver system CPU is always simple... note this is an assignment of 702710SN/A# a class, not an instance. 712710SN/ADriveCPUClass = AtomicSimpleCPU 722710SN/Adrive_mem_mode = 'atomic' 732710SN/A 743322Shsul@eecs.umich.edu# Check if KVM support has been enabled, we might need to do VM 753304Sstever@eecs.umich.edu# configuration if that's the case. 763322Shsul@eecs.umich.eduhave_kvm_support = 'BaseKvmCPU' in globals() 773322Shsul@eecs.umich.edudef is_kvm_cpu(cpu_class): 783304Sstever@eecs.umich.edu return have_kvm_support and cpu_class != None and \ 793481Shsul@eecs.umich.edu issubclass(cpu_class, BaseKvmCPU) 803481Shsul@eecs.umich.edu 812566SN/A# system under test can be any CPU 823322Shsul@eecs.umich.edu(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 833322Shsul@eecs.umich.edu 842995SN/ATestCPUClass.clock = options.clock 852995SN/ADriveCPUClass.clock = options.clock 863304Sstever@eecs.umich.edu 873304Sstever@eecs.umich.eduif options.benchmark: 883304Sstever@eecs.umich.edu try: 892995SN/A bm = Benchmarks[options.benchmark] 902995SN/A except KeyError: 912995SN/A print "Error benchmark %s has not been defined." % options.benchmark 922917SN/A print "Valid benchmarks are: %s" % DefinedBenchmarks 932995SN/A sys.exit(1) 943304Sstever@eecs.umich.eduelse: 952995SN/A if options.dual: 963304Sstever@eecs.umich.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 973304Sstever@eecs.umich.edu else: 983819Shsul@eecs.umich.edu bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 993819Shsul@eecs.umich.edu 1005222Sksewell@umich.edunp = options.num_cpus 1015222Sksewell@umich.edu 1023819Shsul@eecs.umich.eduif buildEnv['TARGET_ISA'] == "alpha": 1033819Shsul@eecs.umich.edu test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 1045133Sgblack@eecs.umich.eduelif buildEnv['TARGET_ISA'] == "mips": 1055133Sgblack@eecs.umich.edu test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 1063819Shsul@eecs.umich.eduelif buildEnv['TARGET_ISA'] == "sparc": 1073819Shsul@eecs.umich.edu test_sys = makeSparcSystem(test_mem_mode, bm[0]) 1083819Shsul@eecs.umich.eduelif buildEnv['TARGET_ISA'] == "x86": 1093873Sbinkertn@umich.edu test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 1103873Sbinkertn@umich.eduelif buildEnv['TARGET_ISA'] == "arm": 1113873Sbinkertn@umich.edu test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 1123873Sbinkertn@umich.edu options.dtb_filename, bare_metal=options.bare_metal) 1133873Sbinkertn@umich.eduelse: 1143873Sbinkertn@umich.edu fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 1153312Sstever@eecs.umich.edu 1163668Srdreslin@umich.eduif options.kernel is not None: 1173668Srdreslin@umich.edu test_sys.kernel = binary(options.kernel) 1183668Srdreslin@umich.edu 1193668Srdreslin@umich.eduif options.script is not None: 1203668Srdreslin@umich.edu test_sys.readfile = options.script 1213668Srdreslin@umich.edu 1223668Srdreslin@umich.edutest_sys.init_param = options.init_param 1233322Shsul@eecs.umich.edu 1245142Ssaidi@eecs.umich.edutest_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 1255142Ssaidi@eecs.umich.edu 1265142Ssaidi@eecs.umich.eduif is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 1275142Ssaidi@eecs.umich.edu test_sys.vm = KvmVM() 1285142Ssaidi@eecs.umich.edu 1295142Ssaidi@eecs.umich.eduif options.caches or options.l2cache: 1305142Ssaidi@eecs.umich.edu test_sys.iocache = IOCache(clock = '1GHz', 1315142Ssaidi@eecs.umich.edu addr_ranges = test_sys.mem_ranges) 1325142Ssaidi@eecs.umich.edu test_sys.iocache.cpu_side = test_sys.iobus.master 1333312Sstever@eecs.umich.edu test_sys.iocache.mem_side = test_sys.membus.slave 1343514Sktlim@umich.eduelse: 1353395Shsul@eecs.umich.edu test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 1363448Shsul@eecs.umich.edu test_sys.iobridge.slave = test_sys.iobus.master 1373668Srdreslin@umich.edu test_sys.iobridge.master = test_sys.membus.slave 1383668Srdreslin@umich.edu 1393668Srdreslin@umich.edu# Sanity check 1403668Srdreslin@umich.eduif options.fastmem: 1413005Sstever@eecs.umich.edu if TestCPUClass != AtomicSimpleCPU: 1424968Sacolyte@umich.edu fatal("Fastmem can only be used with atomic CPU!") 1434968Sacolyte@umich.edu if (options.caches or options.l2cache): 1444968Sacolyte@umich.edu fatal("You cannot use fastmem in combination with caches!") 1455222Sksewell@umich.edu 1465254Sksewell@umich.edufor i in xrange(np): 1475222Sksewell@umich.edu if options.fastmem: 1483005Sstever@eecs.umich.edu test_sys.cpu[i].fastmem = True 1493819Shsul@eecs.umich.edu if options.checker: 1503819Shsul@eecs.umich.edu test_sys.cpu[i].addCheckerCpu() 1515222Sksewell@umich.edu test_sys.cpu[i].createThreads() 1525222Sksewell@umich.edu 1533819Shsul@eecs.umich.eduCacheConfig.config_cache(options, test_sys) 1543819Shsul@eecs.umich.edu 1555133Sgblack@eecs.umich.eduif len(bm) == 2: 1565133Sgblack@eecs.umich.edu if buildEnv['TARGET_ISA'] == 'alpha': 1573322Shsul@eecs.umich.edu drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 1583322Shsul@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'mips': 1594968Sacolyte@umich.edu drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 1604968Sacolyte@umich.edu elif buildEnv['TARGET_ISA'] == 'sparc': 1614837Ssaidi@eecs.umich.edu drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 1624837Ssaidi@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'x86': 1634837Ssaidi@eecs.umich.edu drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 1643322Shsul@eecs.umich.edu elif buildEnv['TARGET_ISA'] == 'arm': 1653005Sstever@eecs.umich.edu drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 1664167Sbinkertn@umich.edu 1673005Sstever@eecs.umich.edu drive_sys.cpu = DriveCPUClass(cpu_id=0) 1683005Sstever@eecs.umich.edu drive_sys.cpu.createThreads() 1693005Sstever@eecs.umich.edu drive_sys.cpu.createInterruptController() 1702566SN/A drive_sys.cpu.connectAllPorts(drive_sys.membus) 1713481Shsul@eecs.umich.edu if options.fastmem: 172 drive_sys.cpu.fastmem = True 173 if options.kernel is not None: 174 drive_sys.kernel = binary(options.kernel) 175 176 if is_kvm_cpu(DriveCPUClass): 177 drive_sys.vm = KvmVM() 178 179 drive_sys.iobridge = Bridge(delay='50ns', 180 ranges = drive_sys.mem_ranges) 181 drive_sys.iobridge.slave = drive_sys.iobus.master 182 drive_sys.iobridge.master = drive_sys.membus.slave 183 184 drive_sys.init_param = options.init_param 185 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 186elif len(bm) == 1: 187 root = Root(full_system=True, system=test_sys) 188else: 189 print "Error I don't know how to create more than 2 systems." 190 sys.exit(1) 191 192if options.timesync: 193 root.time_sync_enable = True 194 195if options.frame_capture: 196 VncServer.frame_capture = True 197 198Simulation.setWorkCountOptions(test_sys, options) 199Simulation.run(options, root, test_sys, FutureClass) 200