devices.py revision 12148 
1# Copyright (c) 2016-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
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8# licensed hereunder.  You may use the software subject to the license
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16# notice, this list of conditions and the following disclaimer;
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22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37#          Gabor Dozsa
38
39# System components used by the bigLITTLE.py configuration script
40
41import m5
42from m5.objects import *
43m5.util.addToPath('../../')
44from common.Caches import *
45from common import CpuConfig
46
47have_kvm = "kvm" in CpuConfig.cpu_names()
48
49class L1I(L1_ICache):
50    tag_latency = 1
51    data_latency = 1
52    response_latency = 1
53    mshrs = 4
54    tgts_per_mshr = 8
55    size = '48kB'
56    assoc = 3
57
58
59class L1D(L1_DCache):
60    tag_latency = 2
61    data_latency = 2
62    response_latency = 1
63    mshrs = 16
64    tgts_per_mshr = 16
65    size = '32kB'
66    assoc = 2
67    write_buffers = 16
68
69
70class WalkCache(PageTableWalkerCache):
71    tag_latency = 4
72    data_latency = 4
73    response_latency = 4
74    mshrs = 6
75    tgts_per_mshr = 8
76    size = '1kB'
77    assoc = 8
78    write_buffers = 16
79
80
81class L2(L2Cache):
82    tag_latency = 12
83    data_latency = 12
84    response_latency = 5
85    mshrs = 32
86    tgts_per_mshr = 8
87    size = '1MB'
88    assoc = 16
89    write_buffers = 8
90    clusivity='mostly_excl'
91
92
93class L3(Cache):
94    size = '16MB'
95    assoc = 16
96    tag_latency = 20
97    data_latency = 20
98    response_latency = 20
99    mshrs = 20
100    tgts_per_mshr = 12
101    clusivity='mostly_excl'
102
103
104class MemBus(SystemXBar):
105    badaddr_responder = BadAddr(warn_access="warn")
106    default = Self.badaddr_responder.pio
107
108
109class CpuCluster(SubSystem):
110    def __init__(self, system,  num_cpus, cpu_clock, cpu_voltage,
111                 cpu_type, l1i_type, l1d_type, wcache_type, l2_type):
112        super(CpuCluster, self).__init__()
113        self._cpu_type = cpu_type
114        self._l1i_type = l1i_type
115        self._l1d_type = l1d_type
116        self._wcache_type = wcache_type
117        self._l2_type = l2_type
118
119        assert num_cpus > 0
120
121        self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
122        self.clk_domain = SrcClockDomain(clock=cpu_clock,
123                                         voltage_domain=self.voltage_domain)
124
125        self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
126                                     clk_domain=self.clk_domain)
127                      for idx in range(num_cpus) ]
128
129        for cpu in self.cpus:
130            cpu.createThreads()
131            cpu.createInterruptController()
132            cpu.socket_id = system.numCpuClusters()
133        system.addCpuCluster(self, num_cpus)
134
135    def requireCaches(self):
136        return self._cpu_type.require_caches()
137
138    def memoryMode(self):
139        return self._cpu_type.memory_mode()
140
141    def addL1(self):
142        for cpu in self.cpus:
143            l1i = None if self._l1i_type is None else self._l1i_type()
144            l1d = None if self._l1d_type is None else self._l1d_type()
145            iwc = None if self._wcache_type is None else self._wcache_type()
146            dwc = None if self._wcache_type is None else self._wcache_type()
147            cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
148
149    def addL2(self, clk_domain):
150        if self._l2_type is None:
151            return
152        self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
153        self.l2 = self._l2_type()
154        for cpu in self.cpus:
155            cpu.connectAllPorts(self.toL2Bus)
156        self.toL2Bus.master = self.l2.cpu_side
157
158    def connectMemSide(self, bus):
159        bus.slave
160        try:
161            self.l2.mem_side = bus.slave
162        except AttributeError:
163            for cpu in self.cpus:
164                cpu.connectAllPorts(bus)
165
166
167class AtomicCluster(CpuCluster):
168    def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
169        cpu_config = [ CpuConfig.get("atomic"), None, None, None, None ]
170        super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
171                                            cpu_voltage, *cpu_config)
172    def addL1(self):
173        pass
174
175class KvmCluster(CpuCluster):
176    def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
177        cpu_config = [ CpuConfig.get("kvm"), None, None, None, None ]
178        super(KvmCluster, self).__init__(system, num_cpus, cpu_clock,
179                                         cpu_voltage, *cpu_config)
180    def addL1(self):
181        pass
182
183
184class SimpleSystem(LinuxArmSystem):
185    cache_line_size = 64
186
187    def __init__(self, caches, mem_size, **kwargs):
188        super(SimpleSystem, self).__init__(**kwargs)
189
190        self.voltage_domain = VoltageDomain(voltage="1.0V")
191        self.clk_domain = SrcClockDomain(clock="1GHz",
192                                         voltage_domain=Parent.voltage_domain)
193
194        self.realview = VExpress_GEM5_V1()
195
196        self.gic_cpu_addr = self.realview.gic.cpu_addr
197        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
198
199        self.membus = MemBus()
200
201        self.intrctrl = IntrControl()
202        self.terminal = Terminal()
203        self.vncserver = VncServer()
204
205        self.iobus = IOXBar()
206        # CPUs->PIO
207        self.iobridge = Bridge(delay='50ns')
208        # Device DMA -> MEM
209        mem_range = self.realview._mem_regions[0]
210        mem_range_size = long(mem_range[1]) - long(mem_range[0])
211        assert mem_range_size >= long(Addr(mem_size))
212        self.mem_ranges = [ AddrRange(start=mem_range[0], size=mem_size) ]
213        self._caches = caches
214        if self._caches:
215            self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]])
216        else:
217            self.dmabridge = Bridge(delay='50ns',
218                                    ranges=[self.mem_ranges[0]])
219
220        self._pci_devices = 0
221        self._clusters = []
222        self._num_cpus = 0
223
224    def attach_pci(self, dev):
225        dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
226        self._pci_devices += 1
227        self.realview.attachPciDevice(dev, self.iobus)
228
229    def connect(self):
230        self.iobridge.master = self.iobus.slave
231        self.iobridge.slave = self.membus.master
232
233        if self._caches:
234            self.iocache.mem_side = self.membus.slave
235            self.iocache.cpu_side = self.iobus.master
236        else:
237            self.dmabridge.master = self.membus.slave
238            self.dmabridge.slave = self.iobus.master
239
240        self.gic_cpu_addr = self.realview.gic.cpu_addr
241        self.realview.attachOnChipIO(self.membus, self.iobridge)
242        self.realview.attachIO(self.iobus)
243        self.system_port = self.membus.slave
244
245    def numCpuClusters(self):
246        return len(self._clusters)
247
248    def addCpuCluster(self, cpu_cluster, num_cpus):
249        assert cpu_cluster not in self._clusters
250        assert num_cpus > 0
251        self._clusters.append(cpu_cluster)
252        self._num_cpus += num_cpus
253
254    def numCpus(self):
255        return self._num_cpus
256
257    def addCaches(self, need_caches, last_cache_level):
258        if not need_caches:
259            # connect each cluster to the memory hierarchy
260            for cluster in self._clusters:
261                cluster.connectMemSide(self.membus)
262            return
263
264        cluster_mem_bus = self.membus
265        assert last_cache_level >= 1 and last_cache_level <= 3
266        for cluster in self._clusters:
267            cluster.addL1()
268        if last_cache_level > 1:
269            for cluster in self._clusters:
270                cluster.addL2(cluster.clk_domain)
271        if last_cache_level > 2:
272            max_clock_cluster = max(self._clusters,
273                                    key=lambda c: c.clk_domain.clock[0])
274            self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
275            self.toL3Bus = L2XBar(width=64)
276            self.toL3Bus.master = self.l3.cpu_side
277            self.l3.mem_side = self.membus.slave
278            cluster_mem_bus = self.toL3Bus
279
280        # connect each cluster to the memory hierarchy
281        for cluster in self._clusters:
282            cluster.connectMemSide(cluster_mem_bus)
283