devices.py revision 11756:0d38e56356c7 
1# Copyright (c) 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
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14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
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20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Andreas Sandberg
37#          Gabor Dozsa
38
39# System components used by the bigLITTLE.py configuration script
40
41import m5
42from m5.objects import *
43m5.util.addToPath('../../')
44from common.Caches import *
45from common import CpuConfig
46
47class L1I(L1_ICache):
48    tag_latency = 1
49    data_latency = 1
50    response_latency = 1
51    mshrs = 4
52    tgts_per_mshr = 8
53    size = '48kB'
54    assoc = 3
55
56
57class L1D(L1_DCache):
58    tag_latency = 2
59    data_latency = 2
60    response_latency = 1
61    mshrs = 16
62    tgts_per_mshr = 16
63    size = '32kB'
64    assoc = 2
65    write_buffers = 16
66
67
68class WalkCache(PageTableWalkerCache):
69    tag_latency = 4
70    data_latency = 4
71    response_latency = 4
72    mshrs = 6
73    tgts_per_mshr = 8
74    size = '1kB'
75    assoc = 8
76    write_buffers = 16
77
78
79class L2(L2Cache):
80    tag_latency = 12
81    data_latency = 12
82    response_latency = 5
83    mshrs = 32
84    tgts_per_mshr = 8
85    size = '1MB'
86    assoc = 16
87    write_buffers = 8
88    clusivity='mostly_excl'
89
90
91class L3(Cache):
92    size = '16MB'
93    assoc = 16
94    tag_latency = 20
95    data_latency = 20
96    response_latency = 20
97    mshrs = 20
98    tgts_per_mshr = 12
99    clusivity='mostly_excl'
100
101
102class MemBus(SystemXBar):
103    badaddr_responder = BadAddr(warn_access="warn")
104    default = Self.badaddr_responder.pio
105
106
107class CpuCluster(SubSystem):
108    def __init__(self, system,  num_cpus, cpu_clock, cpu_voltage,
109                 cpu_type, l1i_type, l1d_type, wcache_type, l2_type):
110        super(CpuCluster, self).__init__()
111        self._cpu_type = cpu_type
112        self._l1i_type = l1i_type
113        self._l1d_type = l1d_type
114        self._wcache_type = wcache_type
115        self._l2_type = l2_type
116
117        assert num_cpus > 0
118
119        self.voltage_domain = VoltageDomain(voltage=cpu_voltage)
120        self.clk_domain = SrcClockDomain(clock=cpu_clock,
121                                         voltage_domain=self.voltage_domain)
122
123        self.cpus = [ self._cpu_type(cpu_id=system.numCpus() + idx,
124                                     clk_domain=self.clk_domain)
125                      for idx in range(num_cpus) ]
126
127        for cpu in self.cpus:
128            cpu.createThreads()
129            cpu.createInterruptController()
130            cpu.socket_id = system.numCpuClusters()
131        system.addCpuCluster(self, num_cpus)
132
133    def requireCaches(self):
134        return self._cpu_type.require_caches()
135
136    def memoryMode(self):
137        return self._cpu_type.memory_mode()
138
139    def addL1(self):
140        for cpu in self.cpus:
141            l1i = None if self._l1i_type is None else self._l1i_type()
142            l1d = None if self._l1d_type is None else self._l1d_type()
143            iwc = None if self._wcache_type is None else self._wcache_type()
144            dwc = None if self._wcache_type is None else self._wcache_type()
145            cpu.addPrivateSplitL1Caches(l1i, l1d, iwc, dwc)
146
147    def addL2(self, clk_domain):
148        if self._l2_type is None:
149            return
150        self.toL2Bus = L2XBar(width=64, clk_domain=clk_domain)
151        self.l2 = self._l2_type()
152        for cpu in self.cpus:
153            cpu.connectAllPorts(self.toL2Bus)
154        self.toL2Bus.master = self.l2.cpu_side
155
156    def connectMemSide(self, bus):
157        bus.slave
158        try:
159            self.l2.mem_side = bus.slave
160        except AttributeError:
161            for cpu in self.cpus:
162                cpu.connectAllPorts(bus)
163
164
165class AtomicCluster(CpuCluster):
166    def __init__(self, system, num_cpus, cpu_clock, cpu_voltage="1.0V"):
167        cpu_config = [ CpuConfig.get("atomic"), None, None, None, None ]
168        super(AtomicCluster, self).__init__(system, num_cpus, cpu_clock,
169                                            cpu_voltage, *cpu_config)
170    def addL1(self):
171        pass
172
173
174class SimpleSystem(LinuxArmSystem):
175    cache_line_size = 64
176
177    def __init__(self, caches, mem_size, **kwargs):
178        super(SimpleSystem, self).__init__(**kwargs)
179
180        self.voltage_domain = VoltageDomain(voltage="1.0V")
181        self.clk_domain = SrcClockDomain(clock="1GHz",
182                                         voltage_domain=Parent.voltage_domain)
183
184        self.realview = VExpress_GEM5_V1()
185
186        self.gic_cpu_addr = self.realview.gic.cpu_addr
187        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
188
189        self.membus = MemBus()
190
191        self.intrctrl = IntrControl()
192        self.terminal = Terminal()
193        self.vncserver = VncServer()
194
195        self.iobus = IOXBar()
196        # CPUs->PIO
197        self.iobridge = Bridge(delay='50ns')
198        # Device DMA -> MEM
199        mem_range = self.realview._mem_regions[0]
200        mem_range_size = long(mem_range[1]) - long(mem_range[0])
201        assert mem_range_size >= long(Addr(mem_size))
202        self._mem_range = AddrRange(start=mem_range[0], size=mem_size)
203        self._caches = caches
204        if self._caches:
205            self.iocache = IOCache(addr_ranges=[self._mem_range])
206        else:
207            self.dmabridge = Bridge(delay='50ns',
208                                    ranges=[self._mem_range])
209
210        self._pci_devices = 0
211        self._clusters = []
212        self._num_cpus = 0
213
214    def attach_pci(self, dev):
215        dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0)
216        self._pci_devices += 1
217        self.realview.attachPciDevice(dev, self.iobus)
218
219    def connect(self):
220        self.iobridge.master = self.iobus.slave
221        self.iobridge.slave = self.membus.master
222
223        if self._caches:
224            self.iocache.mem_side = self.membus.slave
225            self.iocache.cpu_side = self.iobus.master
226        else:
227            self.dmabridge.master = self.membus.slave
228            self.dmabridge.slave = self.iobus.master
229
230        self.gic_cpu_addr = self.realview.gic.cpu_addr
231        self.realview.attachOnChipIO(self.membus, self.iobridge)
232        self.realview.attachIO(self.iobus)
233        self.system_port = self.membus.slave
234
235    def numCpuClusters(self):
236        return len(self._clusters)
237
238    def addCpuCluster(self, cpu_cluster, num_cpus):
239        assert cpu_cluster not in self._clusters
240        assert num_cpus > 0
241        self._clusters.append(cpu_cluster)
242        self._num_cpus += num_cpus
243
244    def numCpus(self):
245        return self._num_cpus
246
247    def addCaches(self, need_caches, last_cache_level):
248        if not need_caches:
249            # connect each cluster to the memory hierarchy
250            for cluster in self._clusters:
251                cluster.connectMemSide(self.membus)
252            return
253
254        cluster_mem_bus = self.membus
255        assert last_cache_level >= 1 and last_cache_level <= 3
256        for cluster in self._clusters:
257            cluster.addL1()
258        if last_cache_level > 1:
259            for cluster in self._clusters:
260                cluster.addL2(cluster.clk_domain)
261        if last_cache_level > 2:
262            max_clock_cluster = max(self._clusters,
263                                    key=lambda c: c.clk_domain.clock[0])
264            self.l3 = L3(clk_domain=max_clock_cluster.clk_domain)
265            self.toL3Bus = L2XBar(width=64)
266            self.toL3Bus.master = self.l3.cpu_side
267            self.l3.mem_side = self.membus.slave
268            cluster_mem_bus = self.toL3Bus
269
270        # connect each cluster to the memory hierarchy
271        for cluster in self._clusters:
272            cluster.connectMemSide(cluster_mem_bus)
273