apu_se.py revision 11682:612f75cf36a0
1# 2# Copyright (c) 2015 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# For use for simulation and test purposes only 6# 7# Redistribution and use in source and binary forms, with or without 8# modification, are permitted provided that the following conditions are met: 9# 10# 1. Redistributions of source code must retain the above copyright notice, 11# this list of conditions and the following disclaimer. 12# 13# 2. Redistributions in binary form must reproduce the above copyright notice, 14# this list of conditions and the following disclaimer in the documentation 15# and/or other materials provided with the distribution. 16# 17# 3. Neither the name of the copyright holder nor the names of its contributors 18# may be used to endorse or promote products derived from this software 19# without specific prior written permission. 20# 21# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31# POSSIBILITY OF SUCH DAMAGE. 32# 33# Author: Sooraj Puthoor 34# 35 36import optparse, os, re 37import math 38import glob 39import inspect 40 41import m5 42from m5.objects import * 43from m5.util import addToPath 44 45addToPath('../') 46 47from ruby import Ruby 48 49from common import Options 50from common import Simulation 51from common import GPUTLBOptions, GPUTLBConfig 52 53########################## Script Options ######################## 54def setOption(parser, opt_str, value = 1): 55 # check to make sure the option actually exists 56 if not parser.has_option(opt_str): 57 raise Exception("cannot find %s in list of possible options" % opt_str) 58 59 opt = parser.get_option(opt_str) 60 # set the value 61 exec("parser.values.%s = %s" % (opt.dest, value)) 62 63def getOption(parser, opt_str): 64 # check to make sure the option actually exists 65 if not parser.has_option(opt_str): 66 raise Exception("cannot find %s in list of possible options" % opt_str) 67 68 opt = parser.get_option(opt_str) 69 # get the value 70 exec("return_value = parser.values.%s" % opt.dest) 71 return return_value 72 73# Adding script options 74parser = optparse.OptionParser() 75Options.addCommonOptions(parser) 76Options.addSEOptions(parser) 77 78parser.add_option("--cpu-only-mode", action="store_true", default=False, 79 help="APU mode. Used to take care of problems in "\ 80 "Ruby.py while running APU protocols") 81parser.add_option("-k", "--kernel-files", 82 help="file(s) containing GPU kernel code (colon separated)") 83parser.add_option("-u", "--num-compute-units", type="int", default=1, 84 help="number of GPU compute units"), 85parser.add_option("--num-cp", type="int", default=0, 86 help="Number of GPU Command Processors (CP)") 87parser.add_option("--benchmark-root", help="Root of benchmark directory tree") 88 89# not super important now, but to avoid putting the number 4 everywhere, make 90# it an option/knob 91parser.add_option("--cu-per-sqc", type="int", default=4, help="number of CUs" \ 92 "sharing an SQC (icache, and thus icache TLB)") 93parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \ 94 "per CU") 95parser.add_option("--wf-size", type="int", default=64, 96 help="Wavefront size(in workitems)") 97parser.add_option("--sp-bypass-path-length", type="int", default=4, \ 98 help="Number of stages of bypass path in vector ALU for Single Precision ops") 99parser.add_option("--dp-bypass-path-length", type="int", default=4, \ 100 help="Number of stages of bypass path in vector ALU for Double Precision ops") 101# issue period per SIMD unit: number of cycles before issuing another vector 102parser.add_option("--issue-period", type="int", default=4, \ 103 help="Number of cycles per vector instruction issue period") 104parser.add_option("--glbmem-wr-bus-width", type="int", default=32, \ 105 help="VGPR to Coalescer (Global Memory) data bus width in bytes") 106parser.add_option("--glbmem-rd-bus-width", type="int", default=32, \ 107 help="Coalescer to VGPR (Global Memory) data bus width in bytes") 108# Currently we only support 1 local memory pipe 109parser.add_option("--shr-mem-pipes-per-cu", type="int", default=1, \ 110 help="Number of Shared Memory pipelines per CU") 111# Currently we only support 1 global memory pipe 112parser.add_option("--glb-mem-pipes-per-cu", type="int", default=1, \ 113 help="Number of Global Memory pipelines per CU") 114parser.add_option("--wfs-per-simd", type="int", default=10, help="Number of " \ 115 "WF slots per SIMD") 116 117parser.add_option("--vreg-file-size", type="int", default=2048, 118 help="number of physical vector registers per SIMD") 119parser.add_option("--bw-scalor", type="int", default=0, 120 help="bandwidth scalor for scalability analysis") 121parser.add_option("--CPUClock", type="string", default="2GHz", 122 help="CPU clock") 123parser.add_option("--GPUClock", type="string", default="1GHz", 124 help="GPU clock") 125parser.add_option("--cpu-voltage", action="store", type="string", 126 default='1.0V', 127 help = """CPU voltage domain""") 128parser.add_option("--gpu-voltage", action="store", type="string", 129 default='1.0V', 130 help = """CPU voltage domain""") 131parser.add_option("--CUExecPolicy", type="string", default="OLDEST-FIRST", 132 help="WF exec policy (OLDEST-FIRST, ROUND-ROBIN)") 133parser.add_option("--xact-cas-mode", action="store_true", 134 help="enable load_compare mode (transactional CAS)") 135parser.add_option("--SegFaultDebug",action="store_true", 136 help="checks for GPU seg fault before TLB access") 137parser.add_option("--FunctionalTLB",action="store_true", 138 help="Assumes TLB has no latency") 139parser.add_option("--LocalMemBarrier",action="store_true", 140 help="Barrier does not wait for writethroughs to complete") 141parser.add_option("--countPages", action="store_true", 142 help="Count Page Accesses and output in per-CU output files") 143parser.add_option("--TLB-prefetch", type="int", help = "prefetch depth for"\ 144 "TLBs") 145parser.add_option("--pf-type", type="string", help="type of prefetch: "\ 146 "PF_CU, PF_WF, PF_PHASE, PF_STRIDE") 147parser.add_option("--pf-stride", type="int", help="set prefetch stride") 148parser.add_option("--numLdsBanks", type="int", default=32, 149 help="number of physical banks per LDS module") 150parser.add_option("--ldsBankConflictPenalty", type="int", default=1, 151 help="number of cycles per LDS bank conflict") 152parser.add_option('--fast-forward-pseudo-op', action='store_true', 153 help = 'fast forward using kvm until the m5_switchcpu' 154 ' pseudo-op is encountered, then switch cpus. subsequent' 155 ' m5_switchcpu pseudo-ops will toggle back and forth') 156 157 158Ruby.define_options(parser) 159 160#add TLB options to the parser 161GPUTLBOptions.tlb_options(parser) 162 163(options, args) = parser.parse_args() 164 165# The GPU cache coherence protocols only work with the backing store 166setOption(parser, "--access-backing-store") 167 168# if benchmark root is specified explicitly, that overrides the search path 169if options.benchmark_root: 170 benchmark_path = [options.benchmark_root] 171else: 172 # Set default benchmark search path to current dir 173 benchmark_path = ['.'] 174 175########################## Sanity Check ######################## 176 177# Currently the gpu model requires ruby 178if buildEnv['PROTOCOL'] == 'None': 179 fatal("GPU model requires ruby") 180 181# Currently the gpu model requires only timing or detailed CPU 182if not (options.cpu_type == "timing" or 183 options.cpu_type == "detailed"): 184 fatal("GPU model requires timing or detailed CPU") 185 186# This file can support multiple compute units 187assert(options.num_compute_units >= 1) 188 189# Currently, the sqc (I-Cache of GPU) is shared by 190# multiple compute units(CUs). The protocol works just fine 191# even if sqc is not shared. Overriding this option here 192# so that the user need not explicitly set this (assuming 193# sharing sqc is the common usage) 194n_cu = options.num_compute_units 195num_sqc = int(math.ceil(float(n_cu) / options.cu_per_sqc)) 196options.num_sqc = num_sqc # pass this to Ruby 197 198########################## Creating the GPU system ######################## 199# shader is the GPU 200shader = Shader(n_wf = options.wfs_per_simd, 201 clk_domain = SrcClockDomain( 202 clock = options.GPUClock, 203 voltage_domain = VoltageDomain( 204 voltage = options.gpu_voltage))) 205 206# GPU_RfO(Read For Ownership) implements SC/TSO memory model. 207# Other GPU protocols implement release consistency at GPU side. 208# So, all GPU protocols other than GPU_RfO should make their writes 209# visible to the global memory and should read from global memory 210# during kernal boundary. The pipeline initiates(or do not initiate) 211# the acquire/release operation depending on this impl_kern_boundary_sync 212# flag. This flag=true means pipeline initiates a acquire/release operation 213# at kernel boundary. 214if buildEnv['PROTOCOL'] == 'GPU_RfO': 215 shader.impl_kern_boundary_sync = False 216else: 217 shader.impl_kern_boundary_sync = True 218 219# Switching off per-lane TLB by default 220per_lane = False 221if options.TLB_config == "perLane": 222 per_lane = True 223 224# List of compute units; one GPU can have multiple compute units 225compute_units = [] 226for i in xrange(n_cu): 227 compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane, 228 num_SIMDs = options.simds_per_cu, 229 wfSize = options.wf_size, 230 spbypass_pipe_length = options.sp_bypass_path_length, 231 dpbypass_pipe_length = options.dp_bypass_path_length, 232 issue_period = options.issue_period, 233 coalescer_to_vrf_bus_width = \ 234 options.glbmem_rd_bus_width, 235 vrf_to_coalescer_bus_width = \ 236 options.glbmem_wr_bus_width, 237 num_global_mem_pipes = \ 238 options.glb_mem_pipes_per_cu, 239 num_shared_mem_pipes = \ 240 options.shr_mem_pipes_per_cu, 241 n_wf = options.wfs_per_simd, 242 execPolicy = options.CUExecPolicy, 243 xactCasMode = options.xact_cas_mode, 244 debugSegFault = options.SegFaultDebug, 245 functionalTLB = options.FunctionalTLB, 246 localMemBarrier = options.LocalMemBarrier, 247 countPages = options.countPages, 248 localDataStore = \ 249 LdsState(banks = options.numLdsBanks, 250 bankConflictPenalty = \ 251 options.ldsBankConflictPenalty))) 252 wavefronts = [] 253 vrfs = [] 254 for j in xrange(options.simds_per_cu): 255 for k in xrange(shader.n_wf): 256 wavefronts.append(Wavefront(simdId = j, wf_slot_id = k, 257 wfSize = options.wf_size)) 258 vrfs.append(VectorRegisterFile(simd_id=j, 259 num_regs_per_simd=options.vreg_file_size)) 260 compute_units[-1].wavefronts = wavefronts 261 compute_units[-1].vector_register_file = vrfs 262 if options.TLB_prefetch: 263 compute_units[-1].prefetch_depth = options.TLB_prefetch 264 compute_units[-1].prefetch_prev_type = options.pf_type 265 266 # attach the LDS and the CU to the bus (actually a Bridge) 267 compute_units[-1].ldsPort = compute_units[-1].ldsBus.slave 268 compute_units[-1].ldsBus.master = compute_units[-1].localDataStore.cuPort 269 270# Attach compute units to GPU 271shader.CUs = compute_units 272 273########################## Creating the CPU system ######################## 274options.num_cpus = options.num_cpus 275 276# The shader core will be whatever is after the CPU cores are accounted for 277shader_idx = options.num_cpus 278 279# The command processor will be whatever is after the shader is accounted for 280cp_idx = shader_idx + 1 281cp_list = [] 282 283# List of CPUs 284cpu_list = [] 285 286CpuClass, mem_mode = Simulation.getCPUClass(options.cpu_type) 287if CpuClass == AtomicSimpleCPU: 288 fatal("AtomicSimpleCPU is not supported") 289if mem_mode != 'timing': 290 fatal("Only the timing memory mode is supported") 291shader.timing = True 292 293if options.fast_forward and options.fast_forward_pseudo_op: 294 fatal("Cannot fast-forward based both on the number of instructions and" 295 " on pseudo-ops") 296fast_forward = options.fast_forward or options.fast_forward_pseudo_op 297 298if fast_forward: 299 FutureCpuClass, future_mem_mode = CpuClass, mem_mode 300 301 CpuClass = X86KvmCPU 302 mem_mode = 'atomic_noncaching' 303 # Leave shader.timing untouched, because its value only matters at the 304 # start of the simulation and because we require switching cpus 305 # *before* the first kernel launch. 306 307 future_cpu_list = [] 308 309 # Initial CPUs to be used during fast-forwarding. 310 for i in xrange(options.num_cpus): 311 cpu = CpuClass(cpu_id = i, 312 clk_domain = SrcClockDomain( 313 clock = options.CPUClock, 314 voltage_domain = VoltageDomain( 315 voltage = options.cpu_voltage))) 316 cpu_list.append(cpu) 317 318 if options.fast_forward: 319 cpu.max_insts_any_thread = int(options.fast_forward) 320 321if fast_forward: 322 MainCpuClass = FutureCpuClass 323else: 324 MainCpuClass = CpuClass 325 326# CPs to be used throughout the simulation. 327for i in xrange(options.num_cp): 328 cp = MainCpuClass(cpu_id = options.num_cpus + i, 329 clk_domain = SrcClockDomain( 330 clock = options.CPUClock, 331 voltage_domain = VoltageDomain( 332 voltage = options.cpu_voltage))) 333 cp_list.append(cp) 334 335# Main CPUs (to be used after fast-forwarding if fast-forwarding is specified). 336for i in xrange(options.num_cpus): 337 cpu = MainCpuClass(cpu_id = i, 338 clk_domain = SrcClockDomain( 339 clock = options.CPUClock, 340 voltage_domain = VoltageDomain( 341 voltage = options.cpu_voltage))) 342 if fast_forward: 343 cpu.switched_out = True 344 future_cpu_list.append(cpu) 345 else: 346 cpu_list.append(cpu) 347 348########################## Creating the GPU dispatcher ######################## 349# Dispatcher dispatches work from host CPU to GPU 350host_cpu = cpu_list[0] 351dispatcher = GpuDispatcher() 352 353########################## Create and assign the workload ######################## 354# Check for rel_path in elements of base_list using test, returning 355# the first full path that satisfies test 356def find_path(base_list, rel_path, test): 357 for base in base_list: 358 if not base: 359 # base could be None if environment var not set 360 continue 361 full_path = os.path.join(base, rel_path) 362 if test(full_path): 363 return full_path 364 fatal("%s not found in %s" % (rel_path, base_list)) 365 366def find_file(base_list, rel_path): 367 return find_path(base_list, rel_path, os.path.isfile) 368 369executable = find_path(benchmark_path, options.cmd, os.path.exists) 370# it's common for a benchmark to be in a directory with the same 371# name as the executable, so we handle that automatically 372if os.path.isdir(executable): 373 benchmark_path = [executable] 374 executable = find_file(benchmark_path, options.cmd) 375if options.kernel_files: 376 kernel_files = [find_file(benchmark_path, f) 377 for f in options.kernel_files.split(':')] 378else: 379 # if kernel_files is not set, see if there's a unique .asm file 380 # in the same directory as the executable 381 kernel_path = os.path.dirname(executable) 382 kernel_files = glob.glob(os.path.join(kernel_path, '*.asm')) 383 if kernel_files: 384 print "Using GPU kernel code file(s)", ",".join(kernel_files) 385 else: 386 fatal("Can't locate kernel code (.asm) in " + kernel_path) 387 388# OpenCL driver 389driver = ClDriver(filename="hsa", codefile=kernel_files) 390for cpu in cpu_list: 391 cpu.workload = LiveProcess(executable = executable, 392 cmd = [options.cmd] + options.options.split(), 393 drivers = [driver]) 394for cp in cp_list: 395 cp.workload = host_cpu.workload 396 397if fast_forward: 398 for i in xrange(len(future_cpu_list)): 399 future_cpu_list[i].workload = cpu_list[i].workload 400 401########################## Create the overall system ######################## 402# List of CPUs that must be switched when moving between KVM and simulation 403if fast_forward: 404 switch_cpu_list = \ 405 [(cpu_list[i], future_cpu_list[i]) for i in xrange(options.num_cpus)] 406 407# Full list of processing cores in the system. Note that 408# dispatcher is also added to cpu_list although it is 409# not a processing element 410cpu_list = cpu_list + [shader] + cp_list + [dispatcher] 411 412# creating the overall system 413# notice the cpu list is explicitly added as a parameter to System 414system = System(cpu = cpu_list, 415 mem_ranges = [AddrRange(options.mem_size)], 416 cache_line_size = options.cacheline_size, 417 mem_mode = mem_mode) 418if fast_forward: 419 system.future_cpu = future_cpu_list 420system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 421system.clk_domain = SrcClockDomain(clock = options.sys_clock, 422 voltage_domain = system.voltage_domain) 423 424if fast_forward: 425 have_kvm_support = 'BaseKvmCPU' in globals() 426 if have_kvm_support and buildEnv['TARGET_ISA'] == "x86": 427 system.vm = KvmVM() 428 for i in xrange(len(host_cpu.workload)): 429 host_cpu.workload[i].useArchPT = True 430 host_cpu.workload[i].kvmInSE = True 431 else: 432 fatal("KvmCPU can only be used in SE mode with x86") 433 434# configure the TLB hierarchy 435GPUTLBConfig.config_tlb_hierarchy(options, system, shader_idx) 436 437# create Ruby system 438system.piobus = IOXBar(width=32, response_latency=0, 439 frontend_latency=0, forward_latency=0) 440Ruby.create_system(options, None, system) 441system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 442 voltage_domain = system.voltage_domain) 443 444# attach the CPU ports to Ruby 445for i in range(options.num_cpus): 446 ruby_port = system.ruby._cpu_ports[i] 447 448 # Create interrupt controller 449 system.cpu[i].createInterruptController() 450 451 # Connect cache port's to ruby 452 system.cpu[i].icache_port = ruby_port.slave 453 system.cpu[i].dcache_port = ruby_port.slave 454 455 ruby_port.mem_master_port = system.piobus.slave 456 if buildEnv['TARGET_ISA'] == "x86": 457 system.cpu[i].interrupts[0].pio = system.piobus.master 458 system.cpu[i].interrupts[0].int_master = system.piobus.slave 459 system.cpu[i].interrupts[0].int_slave = system.piobus.master 460 if fast_forward: 461 system.cpu[i].itb.walker.port = ruby_port.slave 462 system.cpu[i].dtb.walker.port = ruby_port.slave 463 464# attach CU ports to Ruby 465# Because of the peculiarities of the CP core, you may have 1 CPU but 2 466# sequencers and thus 2 _cpu_ports created. Your GPUs shouldn't be 467# hooked up until after the CP. To make this script generic, figure out 468# the index as below, but note that this assumes there is one sequencer 469# per compute unit and one sequencer per SQC for the math to work out 470# correctly. 471gpu_port_idx = len(system.ruby._cpu_ports) \ 472 - options.num_compute_units - options.num_sqc 473gpu_port_idx = gpu_port_idx - options.num_cp * 2 474 475wavefront_size = options.wf_size 476for i in xrange(n_cu): 477 # The pipeline issues wavefront_size number of uncoalesced requests 478 # in one GPU issue cycle. Hence wavefront_size mem ports. 479 for j in xrange(wavefront_size): 480 system.cpu[shader_idx].CUs[i].memory_port[j] = \ 481 system.ruby._cpu_ports[gpu_port_idx].slave[j] 482 gpu_port_idx += 1 483 484for i in xrange(n_cu): 485 if i > 0 and not i % options.cu_per_sqc: 486 print "incrementing idx on ", i 487 gpu_port_idx += 1 488 system.cpu[shader_idx].CUs[i].sqc_port = \ 489 system.ruby._cpu_ports[gpu_port_idx].slave 490gpu_port_idx = gpu_port_idx + 1 491 492# attach CP ports to Ruby 493for i in xrange(options.num_cp): 494 system.cpu[cp_idx].createInterruptController() 495 system.cpu[cp_idx].dcache_port = \ 496 system.ruby._cpu_ports[gpu_port_idx + i * 2].slave 497 system.cpu[cp_idx].icache_port = \ 498 system.ruby._cpu_ports[gpu_port_idx + i * 2 + 1].slave 499 system.cpu[cp_idx].interrupts[0].pio = system.piobus.master 500 system.cpu[cp_idx].interrupts[0].int_master = system.piobus.slave 501 system.cpu[cp_idx].interrupts[0].int_slave = system.piobus.master 502 cp_idx = cp_idx + 1 503 504# connect dispatcher to the system.piobus 505dispatcher.pio = system.piobus.master 506dispatcher.dma = system.piobus.slave 507 508################# Connect the CPU and GPU via GPU Dispatcher ################### 509# CPU rings the GPU doorbell to notify a pending task 510# using this interface. 511# And GPU uses this interface to notify the CPU of task completion 512# The communcation happens through emulated driver. 513 514# Note this implicit setting of the cpu_pointer, shader_pointer and tlb array 515# parameters must be after the explicit setting of the System cpu list 516if fast_forward: 517 shader.cpu_pointer = future_cpu_list[0] 518 dispatcher.cpu = future_cpu_list[0] 519else: 520 shader.cpu_pointer = host_cpu 521 dispatcher.cpu = host_cpu 522dispatcher.shader_pointer = shader 523dispatcher.cl_driver = driver 524 525########################## Start simulation ######################## 526 527root = Root(system=system, full_system=False) 528m5.ticks.setGlobalFrequency('1THz') 529if options.abs_max_tick: 530 maxtick = options.abs_max_tick 531else: 532 maxtick = m5.MaxTick 533 534# Benchmarks support work item annotations 535Simulation.setWorkCountOptions(system, options) 536 537# Checkpointing is not supported by APU model 538if (options.checkpoint_dir != None or 539 options.checkpoint_restore != None): 540 fatal("Checkpointing not supported by apu model") 541 542checkpoint_dir = None 543m5.instantiate(checkpoint_dir) 544 545# Map workload to this address space 546host_cpu.workload[0].map(0x10000000, 0x200000000, 4096) 547 548if options.fast_forward: 549 print "Switch at instruction count: %d" % \ 550 cpu_list[0].max_insts_any_thread 551 552exit_event = m5.simulate(maxtick) 553 554if options.fast_forward: 555 if exit_event.getCause() == "a thread reached the max instruction count": 556 m5.switchCpus(system, switch_cpu_list) 557 print "Switched CPUS @ tick %s" % (m5.curTick()) 558 m5.stats.reset() 559 exit_event = m5.simulate(maxtick - m5.curTick()) 560elif options.fast_forward_pseudo_op: 561 while exit_event.getCause() == "switchcpu": 562 # If we are switching *to* kvm, then the current stats are meaningful 563 # Note that we don't do any warmup by default 564 if type(switch_cpu_list[0][0]) == FutureCpuClass: 565 print "Dumping stats..." 566 m5.stats.dump() 567 m5.switchCpus(system, switch_cpu_list) 568 print "Switched CPUS @ tick %s" % (m5.curTick()) 569 m5.stats.reset() 570 # This lets us switch back and forth without keeping a counter 571 switch_cpu_list = [(x[1], x[0]) for x in switch_cpu_list] 572 exit_event = m5.simulate(maxtick - m5.curTick()) 573 574print "Ticks:", m5.curTick() 575print 'Exiting because ', exit_event.getCause() 576sys.exit(exit_event.getCode()) 577