apu_se.py revision 11662:004d34b65092 
1#
2#  Copyright (c) 2015 Advanced Micro Devices, Inc.
3#  All rights reserved.
4#
5#  For use for simulation and test purposes only
6#
7#  Redistribution and use in source and binary forms, with or without
8#  modification, are permitted provided that the following conditions are met:
9#
10#  1. Redistributions of source code must retain the above copyright notice,
11#  this list of conditions and the following disclaimer.
12#
13#  2. Redistributions in binary form must reproduce the above copyright notice,
14#  this list of conditions and the following disclaimer in the documentation
15#  and/or other materials provided with the distribution.
16#
17#  3. Neither the name of the copyright holder nor the names of its contributors
18#  may be used to endorse or promote products derived from this software
19#  without specific prior written permission.
20#
21#  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22#  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23#  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24#  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25#  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26#  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27#  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28#  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29#  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30#  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31#  POSSIBILITY OF SUCH DAMAGE.
32#
33#  Author: Sooraj Puthoor
34#
35
36import optparse, os, re
37import math
38import glob
39import inspect
40
41import m5
42from m5.objects import *
43from m5.util import addToPath
44
45addToPath('../ruby')
46addToPath('../network')
47addToPath('../common')
48addToPath('../topologies')
49
50import Options
51import Ruby
52import Network
53import Simulation
54import GPUTLBOptions, GPUTLBConfig
55
56########################## Script Options ########################
57def setOption(parser, opt_str, value = 1):
58    # check to make sure the option actually exists
59    if not parser.has_option(opt_str):
60        raise Exception("cannot find %s in list of possible options" % opt_str)
61
62    opt = parser.get_option(opt_str)
63    # set the value
64    exec("parser.values.%s = %s" % (opt.dest, value))
65
66def getOption(parser, opt_str):
67    # check to make sure the option actually exists
68    if not parser.has_option(opt_str):
69        raise Exception("cannot find %s in list of possible options" % opt_str)
70
71    opt = parser.get_option(opt_str)
72    # get the value
73    exec("return_value = parser.values.%s" % opt.dest)
74    return return_value
75
76# Adding script options
77parser = optparse.OptionParser()
78Options.addCommonOptions(parser)
79Options.addSEOptions(parser)
80
81parser.add_option("--cpu-only-mode", action="store_true", default=False,
82                  help="APU mode. Used to take care of problems in "\
83                       "Ruby.py while running APU protocols")
84parser.add_option("-k", "--kernel-files",
85                  help="file(s) containing GPU kernel code (colon separated)")
86parser.add_option("-u", "--num-compute-units", type="int", default=1,
87                  help="number of GPU compute units"),
88parser.add_option("--num-cp", type="int", default=0,
89                  help="Number of GPU Command Processors (CP)")
90parser.add_option("--benchmark-root", help="Root of benchmark directory tree")
91
92# not super important now, but to avoid putting the number 4 everywhere, make
93# it an option/knob
94parser.add_option("--cu-per-sqc", type="int", default=4, help="number of CUs" \
95                  "sharing an SQC (icache, and thus icache TLB)")
96parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \
97                  "per CU")
98parser.add_option("--wf-size", type="int", default=64,
99                  help="Wavefront size(in workitems)")
100parser.add_option("--sp-bypass-path-length", type="int", default=4, \
101                  help="Number of stages of bypass path in vector ALU for Single Precision ops")
102parser.add_option("--dp-bypass-path-length", type="int", default=4, \
103                  help="Number of stages of bypass path in vector ALU for Double Precision ops")
104# issue period per SIMD unit: number of cycles before issuing another vector
105parser.add_option("--issue-period", type="int", default=4, \
106                  help="Number of cycles per vector instruction issue period")
107parser.add_option("--glbmem-wr-bus-width", type="int", default=32, \
108                  help="VGPR to Coalescer (Global Memory) data bus width in bytes")
109parser.add_option("--glbmem-rd-bus-width", type="int", default=32, \
110                  help="Coalescer to VGPR (Global Memory) data bus width in bytes")
111# Currently we only support 1 local memory pipe
112parser.add_option("--shr-mem-pipes-per-cu", type="int", default=1, \
113                  help="Number of Shared Memory pipelines per CU")
114# Currently we only support 1 global memory pipe
115parser.add_option("--glb-mem-pipes-per-cu", type="int", default=1, \
116                  help="Number of Global Memory pipelines per CU")
117parser.add_option("--wfs-per-simd", type="int", default=10, help="Number of " \
118                  "WF slots per SIMD")
119
120parser.add_option("--vreg-file-size", type="int", default=2048,
121                  help="number of physical vector registers per SIMD")
122parser.add_option("--bw-scalor", type="int", default=0,
123                  help="bandwidth scalor for scalability analysis")
124parser.add_option("--CPUClock", type="string", default="2GHz",
125                  help="CPU clock")
126parser.add_option("--GPUClock", type="string", default="1GHz",
127                  help="GPU clock")
128parser.add_option("--cpu-voltage", action="store", type="string",
129                  default='1.0V',
130                  help = """CPU  voltage domain""")
131parser.add_option("--gpu-voltage", action="store", type="string",
132                  default='1.0V',
133                  help = """CPU  voltage domain""")
134parser.add_option("--CUExecPolicy", type="string", default="OLDEST-FIRST",
135                  help="WF exec policy (OLDEST-FIRST, ROUND-ROBIN)")
136parser.add_option("--xact-cas-mode", action="store_true",
137                  help="enable load_compare mode (transactional CAS)")
138parser.add_option("--SegFaultDebug",action="store_true",
139                 help="checks for GPU seg fault before TLB access")
140parser.add_option("--FunctionalTLB",action="store_true",
141                 help="Assumes TLB has no latency")
142parser.add_option("--LocalMemBarrier",action="store_true",
143                 help="Barrier does not wait for writethroughs to complete")
144parser.add_option("--countPages", action="store_true",
145                 help="Count Page Accesses and output in per-CU output files")
146parser.add_option("--TLB-prefetch", type="int", help = "prefetch depth for"\
147                  "TLBs")
148parser.add_option("--pf-type", type="string", help="type of prefetch: "\
149                  "PF_CU, PF_WF, PF_PHASE, PF_STRIDE")
150parser.add_option("--pf-stride", type="int", help="set prefetch stride")
151parser.add_option("--numLdsBanks", type="int", default=32,
152                  help="number of physical banks per LDS module")
153parser.add_option("--ldsBankConflictPenalty", type="int", default=1,
154                  help="number of cycles per LDS bank conflict")
155parser.add_option('--fast-forward-pseudo-op', action='store_true',
156                  help = 'fast forward using kvm until the m5_switchcpu'
157                  ' pseudo-op is encountered, then switch cpus. subsequent'
158                  ' m5_switchcpu pseudo-ops will toggle back and forth')
159
160
161Ruby.define_options(parser)
162Network.define_options(parser)
163
164#add TLB options to the parser
165GPUTLBOptions.tlb_options(parser)
166
167(options, args) = parser.parse_args()
168
169# The GPU cache coherence protocols only work with the backing store
170setOption(parser, "--access-backing-store")
171
172# if benchmark root is specified explicitly, that overrides the search path
173if options.benchmark_root:
174    benchmark_path = [options.benchmark_root]
175else:
176    # Set default benchmark search path to current dir
177    benchmark_path = ['.']
178
179########################## Sanity Check ########################
180
181# Currently the gpu model requires ruby
182if buildEnv['PROTOCOL'] == 'None':
183    fatal("GPU model requires ruby")
184
185# Currently the gpu model requires only timing or detailed CPU
186if not (options.cpu_type == "timing" or
187   options.cpu_type == "detailed"):
188    fatal("GPU model requires timing or detailed CPU")
189
190# This file can support multiple compute units
191assert(options.num_compute_units >= 1)
192
193# Currently, the sqc (I-Cache of GPU) is shared by
194# multiple compute units(CUs). The protocol works just fine
195# even if sqc is not shared. Overriding this option here
196# so that the user need not explicitly set this (assuming
197# sharing sqc is the common usage)
198n_cu = options.num_compute_units
199num_sqc = int(math.ceil(float(n_cu) / options.cu_per_sqc))
200options.num_sqc = num_sqc # pass this to Ruby
201
202########################## Creating the GPU system ########################
203# shader is the GPU
204shader = Shader(n_wf = options.wfs_per_simd,
205                clk_domain = SrcClockDomain(
206                    clock = options.GPUClock,
207                    voltage_domain = VoltageDomain(
208                        voltage = options.gpu_voltage)))
209
210# GPU_RfO(Read For Ownership) implements SC/TSO memory model.
211# Other GPU protocols implement release consistency at GPU side.
212# So, all GPU protocols other than GPU_RfO should make their writes
213# visible to the global memory and should read from global memory
214# during kernal boundary. The pipeline initiates(or do not initiate)
215# the acquire/release operation depending on this impl_kern_boundary_sync
216# flag. This flag=true means pipeline initiates a acquire/release operation
217# at kernel boundary.
218if buildEnv['PROTOCOL'] == 'GPU_RfO':
219    shader.impl_kern_boundary_sync = False
220else:
221    shader.impl_kern_boundary_sync = True
222
223# Switching off per-lane TLB by default
224per_lane = False
225if options.TLB_config == "perLane":
226    per_lane = True
227
228# List of compute units; one GPU can have multiple compute units
229compute_units = []
230for i in xrange(n_cu):
231    compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane,
232                                     num_SIMDs = options.simds_per_cu,
233                                     wfSize = options.wf_size,
234                                     spbypass_pipe_length = options.sp_bypass_path_length,
235                                     dpbypass_pipe_length = options.dp_bypass_path_length,
236                                     issue_period = options.issue_period,
237                                     coalescer_to_vrf_bus_width = \
238                                     options.glbmem_rd_bus_width,
239                                     vrf_to_coalescer_bus_width = \
240                                     options.glbmem_wr_bus_width,
241                                     num_global_mem_pipes = \
242                                     options.glb_mem_pipes_per_cu,
243                                     num_shared_mem_pipes = \
244                                     options.shr_mem_pipes_per_cu,
245                                     n_wf = options.wfs_per_simd,
246                                     execPolicy = options.CUExecPolicy,
247                                     xactCasMode = options.xact_cas_mode,
248                                     debugSegFault = options.SegFaultDebug,
249                                     functionalTLB = options.FunctionalTLB,
250                                     localMemBarrier = options.LocalMemBarrier,
251                                     countPages = options.countPages,
252                                     localDataStore = \
253                                     LdsState(banks = options.numLdsBanks,
254                                              bankConflictPenalty = \
255                                              options.ldsBankConflictPenalty)))
256    wavefronts = []
257    vrfs = []
258    for j in xrange(options.simds_per_cu):
259        for k in xrange(shader.n_wf):
260            wavefronts.append(Wavefront(simdId = j, wf_slot_id = k,
261                                        wfSize = options.wf_size))
262        vrfs.append(VectorRegisterFile(simd_id=j,
263                              num_regs_per_simd=options.vreg_file_size))
264    compute_units[-1].wavefronts = wavefronts
265    compute_units[-1].vector_register_file = vrfs
266    if options.TLB_prefetch:
267        compute_units[-1].prefetch_depth = options.TLB_prefetch
268        compute_units[-1].prefetch_prev_type = options.pf_type
269
270    # attach the LDS and the CU to the bus (actually a Bridge)
271    compute_units[-1].ldsPort = compute_units[-1].ldsBus.slave
272    compute_units[-1].ldsBus.master = compute_units[-1].localDataStore.cuPort
273
274# Attach compute units to GPU
275shader.CUs = compute_units
276
277########################## Creating the CPU system ########################
278options.num_cpus = options.num_cpus
279
280# The shader core will be whatever is after the CPU cores are accounted for
281shader_idx = options.num_cpus
282
283# The command processor will be whatever is after the shader is accounted for
284cp_idx = shader_idx + 1
285cp_list = []
286
287# List of CPUs
288cpu_list = []
289
290CpuClass, mem_mode = Simulation.getCPUClass(options.cpu_type)
291if CpuClass == AtomicSimpleCPU:
292    fatal("AtomicSimpleCPU is not supported")
293if mem_mode != 'timing':
294    fatal("Only the timing memory mode is supported")
295shader.timing = True
296
297if options.fast_forward and options.fast_forward_pseudo_op:
298    fatal("Cannot fast-forward based both on the number of instructions and"
299          " on pseudo-ops")
300fast_forward = options.fast_forward or options.fast_forward_pseudo_op
301
302if fast_forward:
303    FutureCpuClass, future_mem_mode = CpuClass, mem_mode
304
305    CpuClass = X86KvmCPU
306    mem_mode = 'atomic_noncaching'
307    # Leave shader.timing untouched, because its value only matters at the
308    # start of the simulation and because we require switching cpus
309    # *before* the first kernel launch.
310
311    future_cpu_list = []
312
313    # Initial CPUs to be used during fast-forwarding.
314    for i in xrange(options.num_cpus):
315        cpu = CpuClass(cpu_id = i,
316                       clk_domain = SrcClockDomain(
317                           clock = options.CPUClock,
318                           voltage_domain = VoltageDomain(
319                               voltage = options.cpu_voltage)))
320        cpu_list.append(cpu)
321
322        if options.fast_forward:
323            cpu.max_insts_any_thread = int(options.fast_forward)
324
325if fast_forward:
326    MainCpuClass = FutureCpuClass
327else:
328    MainCpuClass = CpuClass
329
330# CPs to be used throughout the simulation.
331for i in xrange(options.num_cp):
332    cp = MainCpuClass(cpu_id = options.num_cpus + i,
333                      clk_domain = SrcClockDomain(
334                          clock = options.CPUClock,
335                          voltage_domain = VoltageDomain(
336                              voltage = options.cpu_voltage)))
337    cp_list.append(cp)
338
339# Main CPUs (to be used after fast-forwarding if fast-forwarding is specified).
340for i in xrange(options.num_cpus):
341    cpu = MainCpuClass(cpu_id = i,
342                       clk_domain = SrcClockDomain(
343                           clock = options.CPUClock,
344                           voltage_domain = VoltageDomain(
345                               voltage = options.cpu_voltage)))
346    if fast_forward:
347        cpu.switched_out = True
348        future_cpu_list.append(cpu)
349    else:
350        cpu_list.append(cpu)
351
352########################## Creating the GPU dispatcher ########################
353# Dispatcher dispatches work from host CPU to GPU
354host_cpu = cpu_list[0]
355dispatcher = GpuDispatcher()
356
357########################## Create and assign the workload ########################
358# Check for rel_path in elements of base_list using test, returning
359# the first full path that satisfies test
360def find_path(base_list, rel_path, test):
361    for base in base_list:
362        if not base:
363            # base could be None if environment var not set
364            continue
365        full_path = os.path.join(base, rel_path)
366        if test(full_path):
367            return full_path
368    fatal("%s not found in %s" % (rel_path, base_list))
369
370def find_file(base_list, rel_path):
371    return find_path(base_list, rel_path, os.path.isfile)
372
373executable = find_path(benchmark_path, options.cmd, os.path.exists)
374# it's common for a benchmark to be in a directory with the same
375# name as the executable, so we handle that automatically
376if os.path.isdir(executable):
377    benchmark_path = [executable]
378    executable = find_file(benchmark_path, options.cmd)
379if options.kernel_files:
380    kernel_files = [find_file(benchmark_path, f)
381                    for f in options.kernel_files.split(':')]
382else:
383    # if kernel_files is not set, see if there's a unique .asm file
384    # in the same directory as the executable
385    kernel_path = os.path.dirname(executable)
386    kernel_files = glob.glob(os.path.join(kernel_path, '*.asm'))
387    if kernel_files:
388        print "Using GPU kernel code file(s)", ",".join(kernel_files)
389    else:
390        fatal("Can't locate kernel code (.asm) in " + kernel_path)
391
392# OpenCL driver
393driver = ClDriver(filename="hsa", codefile=kernel_files)
394for cpu in cpu_list:
395    cpu.workload = LiveProcess(executable = executable,
396                               cmd = [options.cmd] + options.options.split(),
397                               drivers = [driver])
398for cp in cp_list:
399    cp.workload = host_cpu.workload
400
401if fast_forward:
402    for i in xrange(len(future_cpu_list)):
403        future_cpu_list[i].workload = cpu_list[i].workload
404
405########################## Create the overall system ########################
406# List of CPUs that must be switched when moving between KVM and simulation
407if fast_forward:
408    switch_cpu_list = \
409        [(cpu_list[i], future_cpu_list[i]) for i in xrange(options.num_cpus)]
410
411# Full list of processing cores in the system. Note that
412# dispatcher is also added to cpu_list although it is
413# not a processing element
414cpu_list = cpu_list + [shader] + cp_list + [dispatcher]
415
416# creating the overall system
417# notice the cpu list is explicitly added as a parameter to System
418system = System(cpu = cpu_list,
419                mem_ranges = [AddrRange(options.mem_size)],
420                cache_line_size = options.cacheline_size,
421                mem_mode = mem_mode)
422if fast_forward:
423    system.future_cpu = future_cpu_list
424system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
425system.clk_domain = SrcClockDomain(clock =  options.sys_clock,
426                                   voltage_domain = system.voltage_domain)
427
428if fast_forward:
429    have_kvm_support = 'BaseKvmCPU' in globals()
430    if have_kvm_support and buildEnv['TARGET_ISA'] == "x86":
431        system.vm = KvmVM()
432        for i in xrange(len(host_cpu.workload)):
433            host_cpu.workload[i].useArchPT = True
434            host_cpu.workload[i].kvmInSE = True
435    else:
436        fatal("KvmCPU can only be used in SE mode with x86")
437
438# configure the TLB hierarchy
439GPUTLBConfig.config_tlb_hierarchy(options, system, shader_idx)
440
441# create Ruby system
442system.piobus = IOXBar(width=32, response_latency=0,
443                       frontend_latency=0, forward_latency=0)
444Ruby.create_system(options, None, system)
445system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
446                                    voltage_domain = system.voltage_domain)
447
448# attach the CPU ports to Ruby
449for i in range(options.num_cpus):
450    ruby_port = system.ruby._cpu_ports[i]
451
452    # Create interrupt controller
453    system.cpu[i].createInterruptController()
454
455    # Connect cache port's to ruby
456    system.cpu[i].icache_port = ruby_port.slave
457    system.cpu[i].dcache_port = ruby_port.slave
458
459    ruby_port.mem_master_port = system.piobus.slave
460    if buildEnv['TARGET_ISA'] == "x86":
461        system.cpu[i].interrupts[0].pio = system.piobus.master
462        system.cpu[i].interrupts[0].int_master = system.piobus.slave
463        system.cpu[i].interrupts[0].int_slave = system.piobus.master
464        if fast_forward:
465            system.cpu[i].itb.walker.port = ruby_port.slave
466            system.cpu[i].dtb.walker.port = ruby_port.slave
467
468# attach CU ports to Ruby
469# Because of the peculiarities of the CP core, you may have 1 CPU but 2
470# sequencers and thus 2 _cpu_ports created. Your GPUs shouldn't be
471# hooked up until after the CP. To make this script generic, figure out
472# the index as below, but note that this assumes there is one sequencer
473# per compute unit and one sequencer per SQC for the math to work out
474# correctly.
475gpu_port_idx = len(system.ruby._cpu_ports) \
476               - options.num_compute_units - options.num_sqc
477gpu_port_idx = gpu_port_idx - options.num_cp * 2
478
479wavefront_size = options.wf_size
480for i in xrange(n_cu):
481    # The pipeline issues wavefront_size number of uncoalesced requests
482    # in one GPU issue cycle. Hence wavefront_size mem ports.
483    for j in xrange(wavefront_size):
484        system.cpu[shader_idx].CUs[i].memory_port[j] = \
485                  system.ruby._cpu_ports[gpu_port_idx].slave[j]
486    gpu_port_idx += 1
487
488for i in xrange(n_cu):
489    if i > 0 and not i % options.cu_per_sqc:
490        print "incrementing idx on ", i
491        gpu_port_idx += 1
492    system.cpu[shader_idx].CUs[i].sqc_port = \
493            system.ruby._cpu_ports[gpu_port_idx].slave
494gpu_port_idx = gpu_port_idx + 1
495
496# attach CP ports to Ruby
497for i in xrange(options.num_cp):
498    system.cpu[cp_idx].createInterruptController()
499    system.cpu[cp_idx].dcache_port = \
500                system.ruby._cpu_ports[gpu_port_idx + i * 2].slave
501    system.cpu[cp_idx].icache_port = \
502                system.ruby._cpu_ports[gpu_port_idx + i * 2 + 1].slave
503    system.cpu[cp_idx].interrupts[0].pio = system.piobus.master
504    system.cpu[cp_idx].interrupts[0].int_master = system.piobus.slave
505    system.cpu[cp_idx].interrupts[0].int_slave = system.piobus.master
506    cp_idx = cp_idx + 1
507
508# connect dispatcher to the system.piobus
509dispatcher.pio = system.piobus.master
510dispatcher.dma = system.piobus.slave
511
512################# Connect the CPU and GPU via GPU Dispatcher ###################
513# CPU rings the GPU doorbell to notify a pending task
514# using this interface.
515# And GPU uses this interface to notify the CPU of task completion
516# The communcation happens through emulated driver.
517
518# Note this implicit setting of the cpu_pointer, shader_pointer and tlb array
519# parameters must be after the explicit setting of the System cpu list
520if fast_forward:
521    shader.cpu_pointer = future_cpu_list[0]
522    dispatcher.cpu = future_cpu_list[0]
523else:
524    shader.cpu_pointer = host_cpu
525    dispatcher.cpu = host_cpu
526dispatcher.shader_pointer = shader
527dispatcher.cl_driver = driver
528
529########################## Start simulation ########################
530
531root = Root(system=system, full_system=False)
532m5.ticks.setGlobalFrequency('1THz')
533if options.abs_max_tick:
534    maxtick = options.abs_max_tick
535else:
536    maxtick = m5.MaxTick
537
538# Benchmarks support work item annotations
539Simulation.setWorkCountOptions(system, options)
540
541# Checkpointing is not supported by APU model
542if (options.checkpoint_dir != None or
543    options.checkpoint_restore != None):
544    fatal("Checkpointing not supported by apu model")
545
546checkpoint_dir = None
547m5.instantiate(checkpoint_dir)
548
549# Map workload to this address space
550host_cpu.workload[0].map(0x10000000, 0x200000000, 4096)
551
552if options.fast_forward:
553    print "Switch at instruction count: %d" % \
554        cpu_list[0].max_insts_any_thread
555
556exit_event = m5.simulate(maxtick)
557
558if options.fast_forward:
559    if exit_event.getCause() == "a thread reached the max instruction count":
560        m5.switchCpus(system, switch_cpu_list)
561        print "Switched CPUS @ tick %s" % (m5.curTick())
562        m5.stats.reset()
563        exit_event = m5.simulate(maxtick - m5.curTick())
564elif options.fast_forward_pseudo_op:
565    while exit_event.getCause() == "switchcpu":
566        # If we are switching *to* kvm, then the current stats are meaningful
567        # Note that we don't do any warmup by default
568        if type(switch_cpu_list[0][0]) == FutureCpuClass:
569            print "Dumping stats..."
570            m5.stats.dump()
571        m5.switchCpus(system, switch_cpu_list)
572        print "Switched CPUS @ tick %s" % (m5.curTick())
573        m5.stats.reset()
574        # This lets us switch back and forth without keeping a counter
575        switch_cpu_list = [(x[1], x[0]) for x in switch_cpu_list]
576        exit_event = m5.simulate(maxtick - m5.curTick())
577
578print "Ticks:", m5.curTick()
579print 'Exiting because ', exit_event.getCause()
580sys.exit(exit_event.getCode())
581