apu_se.py revision 11308:7d8836fd043d
1# 2# Copyright (c) 2015 Advanced Micro Devices, Inc. 3# All rights reserved. 4# 5# For use for simulation and test purposes only 6# 7# Redistribution and use in source and binary forms, with or without 8# modification, are permitted provided that the following conditions are met: 9# 10# 1. Redistributions of source code must retain the above copyright notice, 11# this list of conditions and the following disclaimer. 12# 13# 2. Redistributions in binary form must reproduce the above copyright notice, 14# this list of conditions and the following disclaimer in the documentation 15# and/or other materials provided with the distribution. 16# 17# 3. Neither the name of the copyright holder nor the names of its contributors 18# may be used to endorse or promote products derived from this software 19# without specific prior written permission. 20# 21# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 25# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 31# POSSIBILITY OF SUCH DAMAGE. 32# 33# Author: Sooraj Puthoor 34# 35 36import optparse, os, re 37import math 38import glob 39import inspect 40 41import m5 42from m5.objects import * 43from m5.util import addToPath 44 45addToPath('../ruby') 46addToPath('../common') 47addToPath('../topologies') 48 49import Options 50import Ruby 51import Simulation 52import GPUTLBOptions, GPUTLBConfig 53 54########################## Script Options ######################## 55def setOption(parser, opt_str, value = 1): 56 # check to make sure the option actually exists 57 if not parser.has_option(opt_str): 58 raise Exception("cannot find %s in list of possible options" % opt_str) 59 60 opt = parser.get_option(opt_str) 61 # set the value 62 exec("parser.values.%s = %s" % (opt.dest, value)) 63 64def getOption(parser, opt_str): 65 # check to make sure the option actually exists 66 if not parser.has_option(opt_str): 67 raise Exception("cannot find %s in list of possible options" % opt_str) 68 69 opt = parser.get_option(opt_str) 70 # get the value 71 exec("return_value = parser.values.%s" % opt.dest) 72 return return_value 73 74# Adding script options 75parser = optparse.OptionParser() 76Options.addCommonOptions(parser) 77Options.addSEOptions(parser) 78 79parser.add_option("--cpu-only-mode", action="store_true", default=False, 80 help="APU mode. Used to take care of problems in "\ 81 "Ruby.py while running APU protocols") 82parser.add_option("-k", "--kernel-files", 83 help="file(s) containing GPU kernel code (colon separated)") 84parser.add_option("-u", "--num-compute-units", type="int", default=1, 85 help="number of GPU compute units"), 86parser.add_option("--num-cp", type="int", default=0, 87 help="Number of GPU Command Processors (CP)") 88parser.add_option("--benchmark-root", help="Root of benchmark directory tree") 89 90# not super important now, but to avoid putting the number 4 everywhere, make 91# it an option/knob 92parser.add_option("--cu-per-sqc", type="int", default=4, help="number of CUs" \ 93 "sharing an SQC (icache, and thus icache TLB)") 94parser.add_option("--simds-per-cu", type="int", default=4, help="SIMD units" \ 95 "per CU") 96parser.add_option("--wf-size", type="int", default=64, 97 help="Wavefront size(in workitems)") 98parser.add_option("--sp-bypass-path-length", type="int", default=4, \ 99 help="Number of stages of bypass path in vector ALU for Single Precision ops") 100parser.add_option("--dp-bypass-path-length", type="int", default=4, \ 101 help="Number of stages of bypass path in vector ALU for Double Precision ops") 102# issue period per SIMD unit: number of cycles before issuing another vector 103parser.add_option("--issue-period", type="int", default=4, \ 104 help="Number of cycles per vector instruction issue period") 105parser.add_option("--glbmem-wr-bus-width", type="int", default=32, \ 106 help="VGPR to Coalescer (Global Memory) data bus width in bytes") 107parser.add_option("--glbmem-rd-bus-width", type="int", default=32, \ 108 help="Coalescer to VGPR (Global Memory) data bus width in bytes") 109# Currently we only support 1 local memory pipe 110parser.add_option("--shr-mem-pipes-per-cu", type="int", default=1, \ 111 help="Number of Shared Memory pipelines per CU") 112# Currently we only support 1 global memory pipe 113parser.add_option("--glb-mem-pipes-per-cu", type="int", default=1, \ 114 help="Number of Global Memory pipelines per CU") 115parser.add_option("--wfs-per-simd", type="int", default=10, help="Number of " \ 116 "WF slots per SIMD") 117 118parser.add_option("--vreg-file-size", type="int", default=2048, 119 help="number of physical vector registers per SIMD") 120parser.add_option("--bw-scalor", type="int", default=0, 121 help="bandwidth scalor for scalability analysis") 122parser.add_option("--CPUClock", type="string", default="2GHz", 123 help="CPU clock") 124parser.add_option("--GPUClock", type="string", default="1GHz", 125 help="GPU clock") 126parser.add_option("--cpu-voltage", action="store", type="string", 127 default='1.0V', 128 help = """CPU voltage domain""") 129parser.add_option("--gpu-voltage", action="store", type="string", 130 default='1.0V', 131 help = """CPU voltage domain""") 132parser.add_option("--CUExecPolicy", type="string", default="OLDEST-FIRST", 133 help="WF exec policy (OLDEST-FIRST, ROUND-ROBIN)") 134parser.add_option("--xact-cas-mode", action="store_true", 135 help="enable load_compare mode (transactional CAS)") 136parser.add_option("--SegFaultDebug",action="store_true", 137 help="checks for GPU seg fault before TLB access") 138parser.add_option("--FunctionalTLB",action="store_true", 139 help="Assumes TLB has no latency") 140parser.add_option("--LocalMemBarrier",action="store_true", 141 help="Barrier does not wait for writethroughs to complete") 142parser.add_option("--countPages", action="store_true", 143 help="Count Page Accesses and output in per-CU output files") 144parser.add_option("--TLB-prefetch", type="int", help = "prefetch depth for"\ 145 "TLBs") 146parser.add_option("--pf-type", type="string", help="type of prefetch: "\ 147 "PF_CU, PF_WF, PF_PHASE, PF_STRIDE") 148parser.add_option("--pf-stride", type="int", help="set prefetch stride") 149parser.add_option("--numLdsBanks", type="int", default=32, 150 help="number of physical banks per LDS module") 151parser.add_option("--ldsBankConflictPenalty", type="int", default=1, 152 help="number of cycles per LDS bank conflict") 153 154 155Ruby.define_options(parser) 156 157#add TLB options to the parser 158GPUTLBOptions.tlb_options(parser) 159 160(options, args) = parser.parse_args() 161 162# The GPU cache coherence protocols only work with the backing store 163setOption(parser, "--access-backing-store") 164 165# if benchmark root is specified explicitly, that overrides the search path 166if options.benchmark_root: 167 benchmark_path = [options.benchmark_root] 168else: 169 # Set default benchmark search path to current dir 170 benchmark_path = ['.'] 171 172########################## Sanity Check ######################## 173 174# Currently the gpu model requires ruby 175if buildEnv['PROTOCOL'] == 'None': 176 fatal("GPU model requires ruby") 177 178# Currently the gpu model requires only timing or detailed CPU 179if not (options.cpu_type == "timing" or 180 options.cpu_type == "detailed"): 181 fatal("GPU model requires timing or detailed CPU") 182 183# This file can support multiple compute units 184assert(options.num_compute_units >= 1) 185 186# Currently, the sqc (I-Cache of GPU) is shared by 187# multiple compute units(CUs). The protocol works just fine 188# even if sqc is not shared. Overriding this option here 189# so that the user need not explicitly set this (assuming 190# sharing sqc is the common usage) 191n_cu = options.num_compute_units 192num_sqc = int(math.ceil(float(n_cu) / options.cu_per_sqc)) 193options.num_sqc = num_sqc # pass this to Ruby 194 195########################## Creating the GPU system ######################## 196# shader is the GPU 197shader = Shader(n_wf = options.wfs_per_simd, 198 clk_domain = SrcClockDomain( 199 clock = options.GPUClock, 200 voltage_domain = VoltageDomain( 201 voltage = options.gpu_voltage))) 202 203# GPU_RfO(Read For Ownership) implements SC/TSO memory model. 204# Other GPU protocols implement release consistency at GPU side. 205# So, all GPU protocols other than GPU_RfO should make their writes 206# visible to the global memory and should read from global memory 207# during kernal boundary. The pipeline initiates(or do not initiate) 208# the acquire/release operation depending on this impl_kern_boundary_sync 209# flag. This flag=true means pipeline initiates a acquire/release operation 210# at kernel boundary. 211if buildEnv['PROTOCOL'] == 'GPU_RfO': 212 shader.impl_kern_boundary_sync = False 213else: 214 shader.impl_kern_boundary_sync = True 215 216# Switching off per-lane TLB by default 217per_lane = False 218if options.TLB_config == "perLane": 219 per_lane = True 220 221# List of compute units; one GPU can have multiple compute units 222compute_units = [] 223for i in xrange(n_cu): 224 compute_units.append(ComputeUnit(cu_id = i, perLaneTLB = per_lane, 225 num_SIMDs = options.simds_per_cu, 226 wfSize = options.wf_size, 227 spbypass_pipe_length = options.sp_bypass_path_length, 228 dpbypass_pipe_length = options.dp_bypass_path_length, 229 issue_period = options.issue_period, 230 coalescer_to_vrf_bus_width = \ 231 options.glbmem_rd_bus_width, 232 vrf_to_coalescer_bus_width = \ 233 options.glbmem_wr_bus_width, 234 num_global_mem_pipes = \ 235 options.glb_mem_pipes_per_cu, 236 num_shared_mem_pipes = \ 237 options.shr_mem_pipes_per_cu, 238 n_wf = options.wfs_per_simd, 239 execPolicy = options.CUExecPolicy, 240 xactCasMode = options.xact_cas_mode, 241 debugSegFault = options.SegFaultDebug, 242 functionalTLB = options.FunctionalTLB, 243 localMemBarrier = options.LocalMemBarrier, 244 countPages = options.countPages, 245 localDataStore = \ 246 LdsState(banks = options.numLdsBanks, 247 bankConflictPenalty = \ 248 options.ldsBankConflictPenalty))) 249 wavefronts = [] 250 vrfs = [] 251 for j in xrange(options.simds_per_cu): 252 for k in xrange(shader.n_wf): 253 wavefronts.append(Wavefront(simdId = j, wf_slot_id = k)) 254 vrfs.append(VectorRegisterFile(simd_id=j, 255 num_regs_per_simd=options.vreg_file_size)) 256 compute_units[-1].wavefronts = wavefronts 257 compute_units[-1].vector_register_file = vrfs 258 if options.TLB_prefetch: 259 compute_units[-1].prefetch_depth = options.TLB_prefetch 260 compute_units[-1].prefetch_prev_type = options.pf_type 261 262 # attach the LDS and the CU to the bus (actually a Bridge) 263 compute_units[-1].ldsPort = compute_units[-1].ldsBus.slave 264 compute_units[-1].ldsBus.master = compute_units[-1].localDataStore.cuPort 265 266# Attach compute units to GPU 267shader.CUs = compute_units 268 269########################## Creating the CPU system ######################## 270options.num_cpus = options.num_cpus 271 272# The shader core will be whatever is after the CPU cores are accounted for 273shader_idx = options.num_cpus 274 275# The command processor will be whatever is after the shader is accounted for 276cp_idx = shader_idx + 1 277cp_list = [] 278 279# List of CPUs 280cpu_list = [] 281 282# We only support timing mode for shader and memory 283shader.timing = True 284mem_mode = 'timing' 285 286# create the cpus 287for i in range(options.num_cpus): 288 cpu = None 289 if options.cpu_type == "detailed": 290 cpu = DerivO3CPU(cpu_id=i, 291 clk_domain = SrcClockDomain( 292 clock = options.CPUClock, 293 voltage_domain = VoltageDomain( 294 voltage = options.cpu_voltage))) 295 elif options.cpu_type == "timing": 296 cpu = TimingSimpleCPU(cpu_id=i, 297 clk_domain = SrcClockDomain( 298 clock = options.CPUClock, 299 voltage_domain = VoltageDomain( 300 voltage = options.cpu_voltage))) 301 else: 302 fatal("Atomic CPU not supported/tested") 303 cpu_list.append(cpu) 304 305# create the command processors 306for i in xrange(options.num_cp): 307 cp = None 308 if options.cpu_type == "detailed": 309 cp = DerivO3CPU(cpu_id = options.num_cpus + i, 310 clk_domain = SrcClockDomain( 311 clock = options.CPUClock, 312 voltage_domain = VoltageDomain( 313 voltage = options.cpu_voltage))) 314 elif options.cpu_type == 'timing': 315 cp = TimingSimpleCPU(cpu_id=options.num_cpus + i, 316 clk_domain = SrcClockDomain( 317 clock = options.CPUClock, 318 voltage_domain = VoltageDomain( 319 voltage = options.cpu_voltage))) 320 else: 321 fatal("Atomic CPU not supported/tested") 322 cp_list = cp_list + [cp] 323 324########################## Creating the GPU dispatcher ######################## 325# Dispatcher dispatches work from host CPU to GPU 326host_cpu = cpu_list[0] 327dispatcher = GpuDispatcher() 328 329########################## Create and assign the workload ######################## 330# Check for rel_path in elements of base_list using test, returning 331# the first full path that satisfies test 332def find_path(base_list, rel_path, test): 333 for base in base_list: 334 if not base: 335 # base could be None if environment var not set 336 continue 337 full_path = os.path.join(base, rel_path) 338 if test(full_path): 339 return full_path 340 fatal("%s not found in %s" % (rel_path, base_list)) 341 342def find_file(base_list, rel_path): 343 return find_path(base_list, rel_path, os.path.isfile) 344 345executable = find_path(benchmark_path, options.cmd, os.path.exists) 346# it's common for a benchmark to be in a directory with the same 347# name as the executable, so we handle that automatically 348if os.path.isdir(executable): 349 benchmark_path = [executable] 350 executable = find_file(benchmark_path, options.cmd) 351if options.kernel_files: 352 kernel_files = [find_file(benchmark_path, f) 353 for f in options.kernel_files.split(':')] 354else: 355 # if kernel_files is not set, see if there's a unique .asm file 356 # in the same directory as the executable 357 kernel_path = os.path.dirname(executable) 358 kernel_files = glob.glob(os.path.join(kernel_path, '*.asm')) 359 if kernel_files: 360 print "Using GPU kernel code file(s)", ",".join(kernel_files) 361 else: 362 fatal("Can't locate kernel code (.asm) in " + kernel_path) 363 364# OpenCL driver 365driver = ClDriver(filename="hsa", codefile=kernel_files) 366for cpu in cpu_list: 367 cpu.workload = LiveProcess(executable = executable, 368 cmd = [options.cmd] + options.options.split(), 369 drivers = [driver]) 370for cp in cp_list: 371 cp.workload = host_cpu.workload 372 373########################## Create the overall system ######################## 374# Full list of processing cores in the system. Note that 375# dispatcher is also added to cpu_list although it is 376# not a processing element 377cpu_list = cpu_list + [shader] + cp_list + [dispatcher] 378 379# creating the overall system 380# notice the cpu list is explicitly added as a parameter to System 381system = System(cpu = cpu_list, 382 mem_ranges = [AddrRange(options.mem_size)], 383 cache_line_size = options.cacheline_size, 384 mem_mode = mem_mode) 385system.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 386system.clk_domain = SrcClockDomain(clock = options.sys_clock, 387 voltage_domain = system.voltage_domain) 388 389# configure the TLB hierarchy 390GPUTLBConfig.config_tlb_hierarchy(options, system, shader_idx) 391 392# create Ruby system 393system.piobus = IOXBar(width=32, response_latency=0, 394 frontend_latency=0, forward_latency=0) 395Ruby.create_system(options, None, system) 396system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 397 voltage_domain = system.voltage_domain) 398 399# attach the CPU ports to Ruby 400for i in range(options.num_cpus): 401 ruby_port = system.ruby._cpu_ports[i] 402 403 # Create interrupt controller 404 system.cpu[i].createInterruptController() 405 406 # Connect cache port's to ruby 407 system.cpu[i].icache_port = ruby_port.slave 408 system.cpu[i].dcache_port = ruby_port.slave 409 410 ruby_port.mem_master_port = system.piobus.slave 411 if buildEnv['TARGET_ISA'] == "x86": 412 system.cpu[i].interrupts[0].pio = system.piobus.master 413 system.cpu[i].interrupts[0].int_master = system.piobus.slave 414 system.cpu[i].interrupts[0].int_slave = system.piobus.master 415 416# attach CU ports to Ruby 417# Because of the peculiarities of the CP core, you may have 1 CPU but 2 418# sequencers and thus 2 _cpu_ports created. Your GPUs shouldn't be 419# hooked up until after the CP. To make this script generic, figure out 420# the index as below, but note that this assumes there is one sequencer 421# per compute unit and one sequencer per SQC for the math to work out 422# correctly. 423gpu_port_idx = len(system.ruby._cpu_ports) \ 424 - options.num_compute_units - options.num_sqc 425gpu_port_idx = gpu_port_idx - options.num_cp * 2 426 427wavefront_size = options.wf_size 428for i in xrange(n_cu): 429 # The pipeline issues wavefront_size number of uncoalesced requests 430 # in one GPU issue cycle. Hence wavefront_size mem ports. 431 for j in xrange(wavefront_size): 432 system.cpu[shader_idx].CUs[i].memory_port[j] = \ 433 system.ruby._cpu_ports[gpu_port_idx].slave[j] 434 gpu_port_idx += 1 435 436for i in xrange(n_cu): 437 if i > 0 and not i % options.cu_per_sqc: 438 print "incrementing idx on ", i 439 gpu_port_idx += 1 440 system.cpu[shader_idx].CUs[i].sqc_port = \ 441 system.ruby._cpu_ports[gpu_port_idx].slave 442gpu_port_idx = gpu_port_idx + 1 443 444# attach CP ports to Ruby 445for i in xrange(options.num_cp): 446 system.cpu[cp_idx].createInterruptController() 447 system.cpu[cp_idx].dcache_port = \ 448 system.ruby._cpu_ports[gpu_port_idx + i * 2].slave 449 system.cpu[cp_idx].icache_port = \ 450 system.ruby._cpu_ports[gpu_port_idx + i * 2 + 1].slave 451 system.cpu[cp_idx].interrupts[0].pio = system.piobus.master 452 system.cpu[cp_idx].interrupts[0].int_master = system.piobus.slave 453 system.cpu[cp_idx].interrupts[0].int_slave = system.piobus.master 454 cp_idx = cp_idx + 1 455 456# connect dispatcher to the system.piobus 457dispatcher.pio = system.piobus.master 458dispatcher.dma = system.piobus.slave 459 460################# Connect the CPU and GPU via GPU Dispatcher ################### 461# CPU rings the GPU doorbell to notify a pending task 462# using this interface. 463# And GPU uses this interface to notify the CPU of task completion 464# The communcation happens through emulated driver. 465 466# Note this implicit setting of the cpu_pointer, shader_pointer and tlb array 467# parameters must be after the explicit setting of the System cpu list 468shader.cpu_pointer = host_cpu 469dispatcher.cpu = host_cpu 470dispatcher.shader_pointer = shader 471dispatcher.cl_driver = driver 472 473########################## Start simulation ######################## 474 475root = Root(system=system, full_system=False) 476m5.ticks.setGlobalFrequency('1THz') 477if options.abs_max_tick: 478 maxtick = options.abs_max_tick 479else: 480 maxtick = m5.MaxTick 481 482# Benchmarks support work item annotations 483Simulation.setWorkCountOptions(system, options) 484 485# Checkpointing is not supported by APU model 486if (options.checkpoint_dir != None or 487 options.checkpoint_restore != None): 488 fatal("Checkpointing not supported by apu model") 489 490checkpoint_dir = None 491m5.instantiate(checkpoint_dir) 492 493# Map workload to this address space 494host_cpu.workload[0].map(0x10000000, 0x200000000, 4096) 495 496exit_event = m5.simulate(maxtick) 497print "Ticks:", m5.curTick() 498print 'Exiting because ', exit_event.getCause() 499sys.exit(exit_event.getCode()) 500