sweep.py revision 13774
1# Copyright (c) 2014-2015, 2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Andreas Hansson 37 38from __future__ import print_function 39from __future__ import absolute_import 40 41import math 42import optparse 43 44import m5 45from m5.objects import * 46from m5.util import addToPath 47from m5.stats import periodicStatDump 48 49addToPath('../') 50 51from common import MemConfig 52 53# this script is helpful to sweep the efficiency of a specific memory 54# controller configuration, by varying the number of banks accessed, 55# and the sequential stride size (how many bytes per activate), and 56# observe what bus utilisation (bandwidth) is achieved 57 58parser = optparse.OptionParser() 59 60dram_generators = { 61 "DRAM" : lambda x: x.createDram, 62 "DRAM_ROTATE" : lambda x: x.createDramRot, 63} 64 65# Use a single-channel DDR3-1600 x64 (8x8 topology) by default 66parser.add_option("--mem-type", type="choice", default="DDR3_1600_8x8", 67 choices=MemConfig.mem_names(), 68 help = "type of memory to use") 69 70parser.add_option("--mem-ranks", "-r", type="int", default=1, 71 help = "Number of ranks to iterate across") 72 73parser.add_option("--rd_perc", type="int", default=100, 74 help = "Percentage of read commands") 75 76parser.add_option("--mode", type="choice", default="DRAM", 77 choices=dram_generators.keys(), 78 help = "DRAM: Random traffic; \ 79 DRAM_ROTATE: Traffic rotating across banks and ranks") 80 81parser.add_option("--addr_map", type="int", default=1, 82 help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo") 83 84(options, args) = parser.parse_args() 85 86if args: 87 print("Error: script doesn't take any positional arguments") 88 sys.exit(1) 89 90# at the moment we stay with the default open-adaptive page policy, 91# and address mapping 92 93# start with the system itself, using a multi-layer 2.0 GHz 94# crossbar, delivering 64 bytes / 3 cycles (one header cycle) 95# which amounts to 42.7 GByte/s per layer and thus per port 96system = System(membus = IOXBar(width = 32)) 97system.clk_domain = SrcClockDomain(clock = '2.0GHz', 98 voltage_domain = 99 VoltageDomain(voltage = '1V')) 100 101# we are fine with 256 MB memory for now 102mem_range = AddrRange('256MB') 103system.mem_ranges = [mem_range] 104 105# do not worry about reserving space for the backing store 106system.mmap_using_noreserve = True 107 108# force a single channel to match the assumptions in the DRAM traffic 109# generator 110options.mem_channels = 1 111options.external_memory_system = 0 112options.tlm_memory = 0 113options.elastic_trace_en = 0 114MemConfig.config_mem(options, system) 115 116# the following assumes that we are using the native DRAM 117# controller, check to be sure 118if not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl): 119 fatal("This script assumes the memory is a DRAMCtrl subclass") 120 121# there is no point slowing things down by saving any data 122system.mem_ctrls[0].null = True 123 124# Set the address mapping based on input argument 125# Default to RoRaBaCoCh 126if options.addr_map == 0: 127 system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh" 128elif options.addr_map == 1: 129 system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh" 130else: 131 fatal("Did not specify a valid address map argument") 132 133# stay in each state for 0.25 ms, long enough to warm things up, and 134# short enough to avoid hitting a refresh 135period = 250000000 136 137# stay in each state as long as the dump/reset period, use the entire 138# range, issue transactions of the right DRAM burst size, and match 139# the DRAM maximum bandwidth to ensure that it is saturated 140 141# get the number of banks 142nbr_banks = system.mem_ctrls[0].banks_per_rank.value 143 144# determine the burst length in bytes 145burst_size = int((system.mem_ctrls[0].devices_per_rank.value * 146 system.mem_ctrls[0].device_bus_width.value * 147 system.mem_ctrls[0].burst_length.value) / 8) 148 149# next, get the page size in bytes 150page_size = system.mem_ctrls[0].devices_per_rank.value * \ 151 system.mem_ctrls[0].device_rowbuffer_size.value 152 153# match the maximum bandwidth of the memory, the parameter is in seconds 154# and we need it in ticks (ps) 155itt = system.mem_ctrls[0].tBURST.value * 1000000000000 156 157# assume we start at 0 158max_addr = mem_range.end 159 160# use min of the page size and 512 bytes as that should be more than 161# enough 162max_stride = min(512, page_size) 163 164# create a traffic generator, and point it to the file we just created 165system.tgen = PyTrafficGen() 166 167# add a communication monitor 168system.monitor = CommMonitor() 169 170# connect the traffic generator to the bus via a communication monitor 171system.tgen.port = system.monitor.slave 172system.monitor.master = system.membus.slave 173 174# connect the system port even if it is not used in this example 175system.system_port = system.membus.slave 176 177# every period, dump and reset all stats 178periodicStatDump(period) 179 180# run Forrest, run! 181root = Root(full_system = False, system = system) 182root.system.mem_mode = 'timing' 183 184m5.instantiate() 185 186def trace(): 187 generator = dram_generators[options.mode](system.tgen) 188 for bank in range(1, nbr_banks + 1): 189 for stride_size in range(burst_size, max_stride + 1, burst_size): 190 num_seq_pkts = int(math.ceil(float(stride_size) / burst_size)) 191 yield generator(period, 192 0, max_addr, burst_size, int(itt), int(itt), 193 options.rd_perc, 0, 194 num_seq_pkts, page_size, nbr_banks, bank, 195 options.addr_map, options.mem_ranks) 196 yield system.tgen.createExit(0) 197 198system.tgen.start(trace()) 199 200m5.simulate() 201 202print("DRAM sweep with burst: %d, banks: %d, max stride: %d" % 203 (burst_size, nbr_banks, max_stride)) 204