sweep.py revision 11682
111663Stushar@ece.gatech.edu# Copyright (c) 2014-2015 ARM Limited 211663Stushar@ece.gatech.edu# All rights reserved. 311663Stushar@ece.gatech.edu# 411663Stushar@ece.gatech.edu# The license below extends only to copyright in the software and shall 511663Stushar@ece.gatech.edu# not be construed as granting a license to any other intellectual 611663Stushar@ece.gatech.edu# property including but not limited to intellectual property relating 711663Stushar@ece.gatech.edu# to a hardware implementation of the functionality of the software 811663Stushar@ece.gatech.edu# licensed hereunder. You may use the software subject to the license 911663Stushar@ece.gatech.edu# terms below provided that you ensure that this notice is replicated 1011663Stushar@ece.gatech.edu# unmodified and in its entirety in all distributions of the software, 1111663Stushar@ece.gatech.edu# modified or unmodified, in source code or in binary form. 1211663Stushar@ece.gatech.edu# 1311663Stushar@ece.gatech.edu# Redistribution and use in source and binary forms, with or without 1411663Stushar@ece.gatech.edu# modification, are permitted provided that the following conditions are 1511663Stushar@ece.gatech.edu# met: redistributions of source code must retain the above copyright 1611663Stushar@ece.gatech.edu# notice, this list of conditions and the following disclaimer; 1711663Stushar@ece.gatech.edu# redistributions in binary form must reproduce the above copyright 1811663Stushar@ece.gatech.edu# notice, this list of conditions and the following disclaimer in the 1911663Stushar@ece.gatech.edu# documentation and/or other materials provided with the distribution; 2011663Stushar@ece.gatech.edu# neither the name of the copyright holders nor the names of its 2111663Stushar@ece.gatech.edu# contributors may be used to endorse or promote products derived from 2211663Stushar@ece.gatech.edu# this software without specific prior written permission. 2311663Stushar@ece.gatech.edu# 2411663Stushar@ece.gatech.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2511663Stushar@ece.gatech.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2611663Stushar@ece.gatech.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2711663Stushar@ece.gatech.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2811663Stushar@ece.gatech.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2911663Stushar@ece.gatech.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3011663Stushar@ece.gatech.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3111663Stushar@ece.gatech.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3211663Stushar@ece.gatech.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3311663Stushar@ece.gatech.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3411663Stushar@ece.gatech.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3511663Stushar@ece.gatech.edu# 3611663Stushar@ece.gatech.edu# Authors: Andreas Hansson 3711663Stushar@ece.gatech.edu 3811663Stushar@ece.gatech.eduimport optparse 3911663Stushar@ece.gatech.edu 4011663Stushar@ece.gatech.eduimport m5 4111663Stushar@ece.gatech.edufrom m5.objects import * 4211663Stushar@ece.gatech.edufrom m5.util import addToPath 4311663Stushar@ece.gatech.edufrom m5.internal.stats import periodicStatDump 4411663Stushar@ece.gatech.edu 4511663Stushar@ece.gatech.eduaddToPath('../') 4611663Stushar@ece.gatech.edu 4711663Stushar@ece.gatech.edufrom common import MemConfig 4811663Stushar@ece.gatech.edu 4911663Stushar@ece.gatech.edu# this script is helpful to sweep the efficiency of a specific memory 5011663Stushar@ece.gatech.edu# controller configuration, by varying the number of banks accessed, 5111663Stushar@ece.gatech.edu# and the sequential stride size (how many bytes per activate), and 5211663Stushar@ece.gatech.edu# observe what bus utilisation (bandwidth) is achieved 5311663Stushar@ece.gatech.edu 5411663Stushar@ece.gatech.eduparser = optparse.OptionParser() 5511663Stushar@ece.gatech.edu 5611663Stushar@ece.gatech.edu# Use a single-channel DDR3-1600 x64 by default 5711663Stushar@ece.gatech.eduparser.add_option("--mem-type", type="choice", default="DDR3_1600_x64", 5811663Stushar@ece.gatech.edu choices=MemConfig.mem_names(), 5911663Stushar@ece.gatech.edu help = "type of memory to use") 6011663Stushar@ece.gatech.edu 6111663Stushar@ece.gatech.eduparser.add_option("--mem-ranks", "-r", type="int", default=1, 6211663Stushar@ece.gatech.edu help = "Number of ranks to iterate across") 6311663Stushar@ece.gatech.edu 6411663Stushar@ece.gatech.eduparser.add_option("--rd_perc", type="int", default=100, 6511663Stushar@ece.gatech.edu help = "Percentage of read commands") 6611663Stushar@ece.gatech.edu 6711663Stushar@ece.gatech.eduparser.add_option("--mode", type="choice", default="DRAM", 6811663Stushar@ece.gatech.edu choices=["DRAM", "DRAM_ROTATE"], 6911663Stushar@ece.gatech.edu help = "DRAM: Random traffic; \ 7011663Stushar@ece.gatech.edu DRAM_ROTATE: Traffic rotating across banks and ranks") 7111663Stushar@ece.gatech.edu 7211663Stushar@ece.gatech.eduparser.add_option("--addr_map", type="int", default=1, 7311663Stushar@ece.gatech.edu help = "0: RoCoRaBaCh; 1: RoRaBaCoCh/RoRaBaChCo") 7411663Stushar@ece.gatech.edu 7511663Stushar@ece.gatech.edu(options, args) = parser.parse_args() 7611663Stushar@ece.gatech.edu 7711663Stushar@ece.gatech.eduif args: 7811663Stushar@ece.gatech.edu print "Error: script doesn't take any positional arguments" 7911663Stushar@ece.gatech.edu sys.exit(1) 8011663Stushar@ece.gatech.edu 8111663Stushar@ece.gatech.edu# at the moment we stay with the default open-adaptive page policy, 8211663Stushar@ece.gatech.edu# and address mapping 8311663Stushar@ece.gatech.edu 8411663Stushar@ece.gatech.edu# start with the system itself, using a multi-layer 2.0 GHz 8511663Stushar@ece.gatech.edu# crossbar, delivering 64 bytes / 3 cycles (one header cycle) 8611663Stushar@ece.gatech.edu# which amounts to 42.7 GByte/s per layer and thus per port 8711663Stushar@ece.gatech.edusystem = System(membus = IOXBar(width = 32)) 8811663Stushar@ece.gatech.edusystem.clk_domain = SrcClockDomain(clock = '2.0GHz', 8911663Stushar@ece.gatech.edu voltage_domain = 9011663Stushar@ece.gatech.edu VoltageDomain(voltage = '1V')) 9111663Stushar@ece.gatech.edu 9211663Stushar@ece.gatech.edu# we are fine with 256 MB memory for now 9311663Stushar@ece.gatech.edumem_range = AddrRange('256MB') 9411663Stushar@ece.gatech.edusystem.mem_ranges = [mem_range] 9511663Stushar@ece.gatech.edu 9611663Stushar@ece.gatech.edu# do not worry about reserving space for the backing store 9711663Stushar@ece.gatech.edusystem.mmap_using_noreserve = True 9811663Stushar@ece.gatech.edu 9911663Stushar@ece.gatech.edu# force a single channel to match the assumptions in the DRAM traffic 10011663Stushar@ece.gatech.edu# generator 10111663Stushar@ece.gatech.eduoptions.mem_channels = 1 10211663Stushar@ece.gatech.eduoptions.external_memory_system = 0 10311663Stushar@ece.gatech.eduoptions.tlm_memory = 0 10411663Stushar@ece.gatech.eduoptions.elastic_trace_en = 0 10511663Stushar@ece.gatech.eduMemConfig.config_mem(options, system) 10611663Stushar@ece.gatech.edu 10711663Stushar@ece.gatech.edu# the following assumes that we are using the native DRAM 10811663Stushar@ece.gatech.edu# controller, check to be sure 10911663Stushar@ece.gatech.eduif not isinstance(system.mem_ctrls[0], m5.objects.DRAMCtrl): 11011663Stushar@ece.gatech.edu fatal("This script assumes the memory is a DRAMCtrl subclass") 11111663Stushar@ece.gatech.edu 11211663Stushar@ece.gatech.edu# there is no point slowing things down by saving any data 11311663Stushar@ece.gatech.edusystem.mem_ctrls[0].null = True 11411663Stushar@ece.gatech.edu 11511663Stushar@ece.gatech.edu# Set the address mapping based on input argument 11611663Stushar@ece.gatech.edu# Default to RoRaBaCoCh 11711663Stushar@ece.gatech.eduif options.addr_map == 0: 11811663Stushar@ece.gatech.edu system.mem_ctrls[0].addr_mapping = "RoCoRaBaCh" 11911663Stushar@ece.gatech.eduelif options.addr_map == 1: 12011663Stushar@ece.gatech.edu system.mem_ctrls[0].addr_mapping = "RoRaBaCoCh" 12111663Stushar@ece.gatech.eduelse: 12211663Stushar@ece.gatech.edu fatal("Did not specify a valid address map argument") 12311663Stushar@ece.gatech.edu 12411663Stushar@ece.gatech.edu# stay in each state for 0.25 ms, long enough to warm things up, and 12511663Stushar@ece.gatech.edu# short enough to avoid hitting a refresh 12611663Stushar@ece.gatech.eduperiod = 250000000 12711663Stushar@ece.gatech.edu 12811663Stushar@ece.gatech.edu# this is where we go off piste, and print the traffic generator 12911663Stushar@ece.gatech.edu# configuration that we will later use, crazy but it works 13011663Stushar@ece.gatech.educfg_file_name = "configs/dram/sweep.cfg" 13111663Stushar@ece.gatech.educfg_file = open(cfg_file_name, 'w') 13211663Stushar@ece.gatech.edu 13311663Stushar@ece.gatech.edu# stay in each state as long as the dump/reset period, use the entire 13411663Stushar@ece.gatech.edu# range, issue transactions of the right DRAM burst size, and match 13511663Stushar@ece.gatech.edu# the DRAM maximum bandwidth to ensure that it is saturated 13611663Stushar@ece.gatech.edu 13711663Stushar@ece.gatech.edu# get the number of banks 13811663Stushar@ece.gatech.edunbr_banks = system.mem_ctrls[0].banks_per_rank.value 13911663Stushar@ece.gatech.edu 14011663Stushar@ece.gatech.edu# determine the burst length in bytes 14111663Stushar@ece.gatech.eduburst_size = int((system.mem_ctrls[0].devices_per_rank.value * 14211663Stushar@ece.gatech.edu system.mem_ctrls[0].device_bus_width.value * 14311663Stushar@ece.gatech.edu system.mem_ctrls[0].burst_length.value) / 8) 14411663Stushar@ece.gatech.edu 14511663Stushar@ece.gatech.edu# next, get the page size in bytes 14611663Stushar@ece.gatech.edupage_size = system.mem_ctrls[0].devices_per_rank.value * \ 14711663Stushar@ece.gatech.edu system.mem_ctrls[0].device_rowbuffer_size.value 14811663Stushar@ece.gatech.edu 14911663Stushar@ece.gatech.edu# match the maximum bandwidth of the memory, the parameter is in seconds 15011663Stushar@ece.gatech.edu# and we need it in ticks (ps) 15111663Stushar@ece.gatech.eduitt = system.mem_ctrls[0].tBURST.value * 1000000000000 15211663Stushar@ece.gatech.edu 15311663Stushar@ece.gatech.edu# assume we start at 0 15411663Stushar@ece.gatech.edumax_addr = mem_range.end 15511663Stushar@ece.gatech.edu 15611663Stushar@ece.gatech.edu# use min of the page size and 512 bytes as that should be more than 15711663Stushar@ece.gatech.edu# enough 15811663Stushar@ece.gatech.edumax_stride = min(512, page_size) 15911663Stushar@ece.gatech.edu 16011663Stushar@ece.gatech.edu# now we create the state by iterating over the stride size from burst 16111663Stushar@ece.gatech.edu# size to the max stride, and from using only a single bank up to the 16211663Stushar@ece.gatech.edu# number of banks available 16311663Stushar@ece.gatech.edunxt_state = 0 16411663Stushar@ece.gatech.edufor bank in range(1, nbr_banks + 1): 165 for stride_size in range(burst_size, max_stride + 1, burst_size): 166 cfg_file.write("STATE %d %d %s %d 0 %d %d " 167 "%d %d %d %d %d %d %d %d %d\n" % 168 (nxt_state, period, options.mode, options.rd_perc, 169 max_addr, burst_size, itt, itt, 0, stride_size, 170 page_size, nbr_banks, bank, options.addr_map, 171 options.mem_ranks)) 172 nxt_state = nxt_state + 1 173 174cfg_file.write("INIT 0\n") 175 176# go through the states one by one 177for state in range(1, nxt_state): 178 cfg_file.write("TRANSITION %d %d 1\n" % (state - 1, state)) 179 180cfg_file.write("TRANSITION %d %d 1\n" % (nxt_state - 1, nxt_state - 1)) 181 182cfg_file.close() 183 184# create a traffic generator, and point it to the file we just created 185system.tgen = TrafficGen(config_file = cfg_file_name) 186 187# add a communication monitor 188system.monitor = CommMonitor() 189 190# connect the traffic generator to the bus via a communication monitor 191system.tgen.port = system.monitor.slave 192system.monitor.master = system.membus.slave 193 194# connect the system port even if it is not used in this example 195system.system_port = system.membus.slave 196 197# every period, dump and reset all stats 198periodicStatDump(period) 199 200# run Forrest, run! 201root = Root(full_system = False, system = system) 202root.system.mem_mode = 'timing' 203 204m5.instantiate() 205m5.simulate(nxt_state * period) 206 207print "DRAM sweep with burst: %d, banks: %d, max stride: %d" % \ 208 (burst_size, nbr_banks, max_stride) 209