FSConfig.py revision 9826:014ff1fbff6d 
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
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11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
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18# modification, are permitted provided that the following conditions are
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20# notice, this list of conditions and the following disclaimer;
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28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import convert
45
46class CowIdeDisk(IdeDisk):
47    image = CowDiskImage(child=RawDiskImage(read_only=True),
48                         read_only=False)
49
50    def childImage(self, ci):
51        self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54    badaddr_responder = BadAddr()
55    default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59    IO_address_space_base = 0x80000000000
60    class BaseTsunami(Tsunami):
61        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63                            pci_func=0, pci_dev=0, pci_bus=0)
64
65    self = LinuxAlphaSystem()
66    if not mdesc:
67        # generic system
68        mdesc = SysConfig()
69    self.readfile = mdesc.script()
70    self.iobus = NoncoherentBus()
71    self.membus = MemBus()
72    # By default the bridge responds to all addresses above the I/O
73    # base address (including the PCI config space)
74    self.bridge = Bridge(delay='50ns',
75                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
76    self.mem_ranges = [AddrRange(mdesc.mem())]
77    self.bridge.master = self.iobus.slave
78    self.bridge.slave = self.membus.master
79    self.disk0 = CowIdeDisk(driveID='master')
80    self.disk2 = CowIdeDisk(driveID='master')
81    self.disk0.childImage(mdesc.disk())
82    self.disk2.childImage(disk('linux-bigswap2.img'))
83    self.tsunami = BaseTsunami()
84    self.tsunami.attachIO(self.iobus)
85    self.tsunami.ide.pio = self.iobus.master
86    self.tsunami.ide.config = self.iobus.master
87    self.tsunami.ide.dma = self.iobus.slave
88    self.tsunami.ethernet.pio = self.iobus.master
89    self.tsunami.ethernet.config = self.iobus.master
90    self.tsunami.ethernet.dma = self.iobus.slave
91    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
92                                               read_only = True))
93    self.intrctrl = IntrControl()
94    self.mem_mode = mem_mode
95    self.terminal = Terminal()
96    self.kernel = binary('vmlinux')
97    self.pal = binary('ts_osfpal')
98    self.console = binary('console')
99    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
100
101    self.system_port = self.membus.slave
102
103    return self
104
105def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
106    class BaseTsunami(Tsunami):
107        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
108        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
109                            pci_func=0, pci_dev=0, pci_bus=0)
110    self = LinuxAlphaSystem()
111    self.mem_ranges = [AddrRange(mdesc.mem())]
112    if not mdesc:
113        # generic system
114        mdesc = SysConfig()
115    self.readfile = mdesc.script()
116
117    # Create pio bus to connect all device pio ports to rubymem's pio port
118    self.piobus = NoncoherentBus()
119
120    self.disk0 = CowIdeDisk(driveID='master')
121    self.disk2 = CowIdeDisk(driveID='master')
122    self.disk0.childImage(mdesc.disk())
123    self.disk2.childImage(disk('linux-bigswap2.img'))
124    self.tsunami = BaseTsunami()
125    self.tsunami.attachIO(self.piobus)
126    self.tsunami.ide.pio = self.piobus.master
127    self.tsunami.ide.config = self.piobus.master
128    self.tsunami.ethernet.pio = self.piobus.master
129    self.tsunami.ethernet.config = self.piobus.master
130
131    #
132    # Store the dma devices for later connection to dma ruby ports.
133    # Append an underscore to dma_devices to avoid the SimObjectVector check.
134    #
135    self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
136
137    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
138                                               read_only = True))
139    self.intrctrl = IntrControl()
140    self.mem_mode = mem_mode
141    self.terminal = Terminal()
142    self.kernel = binary('vmlinux')
143    self.pal = binary('ts_osfpal')
144    self.console = binary('console')
145    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
146
147    return self
148
149def makeSparcSystem(mem_mode, mdesc = None):
150    # Constants from iob.cc and uart8250.cc
151    iob_man_addr = 0x9800000000
152    uart_pio_size = 8
153
154    class CowMmDisk(MmDisk):
155        image = CowDiskImage(child=RawDiskImage(read_only=True),
156                             read_only=False)
157
158        def childImage(self, ci):
159            self.image.child.image_file = ci
160
161    self = SparcSystem()
162    if not mdesc:
163        # generic system
164        mdesc = SysConfig()
165    self.readfile = mdesc.script()
166    self.iobus = NoncoherentBus()
167    self.membus = MemBus()
168    self.bridge = Bridge(delay='50ns')
169    self.t1000 = T1000()
170    self.t1000.attachOnChipIO(self.membus)
171    self.t1000.attachIO(self.iobus)
172    self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
173                       AddrRange(Addr('2GB'), size ='256MB')]
174    self.bridge.master = self.iobus.slave
175    self.bridge.slave = self.membus.master
176    self.rom.port = self.membus.master
177    self.nvram.port = self.membus.master
178    self.hypervisor_desc.port = self.membus.master
179    self.partition_desc.port = self.membus.master
180    self.intrctrl = IntrControl()
181    self.disk0 = CowMmDisk()
182    self.disk0.childImage(disk('disk.s10hw2'))
183    self.disk0.pio = self.iobus.master
184
185    # The puart0 and hvuart are placed on the IO bus, so create ranges
186    # for them. The remaining IO range is rather fragmented, so poke
187    # holes for the iob and partition descriptors etc.
188    self.bridge.ranges = \
189        [
190        AddrRange(self.t1000.puart0.pio_addr,
191                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
192        AddrRange(self.disk0.pio_addr,
193                  self.t1000.fake_jbi.pio_addr +
194                  self.t1000.fake_jbi.pio_size - 1),
195        AddrRange(self.t1000.fake_clk.pio_addr,
196                  iob_man_addr - 1),
197        AddrRange(self.t1000.fake_l2_1.pio_addr,
198                  self.t1000.fake_ssi.pio_addr +
199                  self.t1000.fake_ssi.pio_size - 1),
200        AddrRange(self.t1000.hvuart.pio_addr,
201                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
202        ]
203    self.reset_bin = binary('reset_new.bin')
204    self.hypervisor_bin = binary('q_new.bin')
205    self.openboot_bin = binary('openboot_new.bin')
206    self.nvram_bin = binary('nvram1')
207    self.hypervisor_desc_bin = binary('1up-hv.bin')
208    self.partition_desc_bin = binary('1up-md.bin')
209
210    self.system_port = self.membus.slave
211
212    return self
213
214def makeArmSystem(mem_mode, machine_type, mdesc = None,
215                  dtb_filename = None, bare_metal=False):
216    assert machine_type
217
218    if bare_metal:
219        self = ArmSystem()
220    else:
221        self = LinuxArmSystem()
222
223    if not mdesc:
224        # generic system
225        mdesc = SysConfig()
226
227    self.readfile = mdesc.script()
228    self.iobus = NoncoherentBus()
229    self.membus = MemBus()
230    self.membus.badaddr_responder.warn_access = "warn"
231    self.bridge = Bridge(delay='50ns')
232    self.bridge.master = self.iobus.slave
233    self.bridge.slave = self.membus.master
234
235    self.mem_mode = mem_mode
236
237    if machine_type == "RealView_PBX":
238        self.realview = RealViewPBX()
239    elif machine_type == "RealView_EB":
240        self.realview = RealViewEB()
241    elif machine_type == "VExpress_ELT":
242        self.realview = VExpress_ELT()
243    elif machine_type == "VExpress_EMM":
244        self.realview = VExpress_EMM()
245        self.load_addr_mask = 0xffffffff
246    else:
247        print "Unknown Machine Type"
248        sys.exit(1)
249
250    self.cf0 = CowIdeDisk(driveID='master')
251    self.cf0.childImage(mdesc.disk())
252    # default to an IDE controller rather than a CF one
253    # assuming we've got one
254    try:
255        self.realview.ide.disks = [self.cf0]
256    except:
257        self.realview.cf_ctrl.disks = [self.cf0]
258
259    if bare_metal:
260        # EOT character on UART will end the simulation
261        self.realview.uart.end_on_eot = True
262        self.mem_ranges = [AddrRange(mdesc.mem())]
263    else:
264        self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
265        if dtb_filename is not None:
266            self.dtb_filename = dtb_filename
267        self.machine_type = machine_type
268        if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
269            print "The currently selected ARM platforms doesn't support"
270            print " the amount of DRAM you've selected. Please try"
271            print " another platform"
272            sys.exit(1)
273
274        boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
275                     'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
276        self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
277                                     size = mdesc.mem())]
278        self.realview.setupBootLoader(self.membus, self, binary)
279        self.gic_cpu_addr = self.realview.gic.cpu_addr
280        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
281
282        if mdesc.disk().lower().count('android'):
283            boot_flags += " init=/init "
284        self.boot_osflags = boot_flags
285    self.realview.attachOnChipIO(self.membus, self.bridge)
286    self.realview.attachIO(self.iobus)
287    self.intrctrl = IntrControl()
288    self.terminal = Terminal()
289    self.vncserver = VncServer()
290
291    self.system_port = self.membus.slave
292
293    return self
294
295
296def makeLinuxMipsSystem(mem_mode, mdesc = None):
297    class BaseMalta(Malta):
298        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
299        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
300                            pci_func=0, pci_dev=0, pci_bus=0)
301
302    self = LinuxMipsSystem()
303    if not mdesc:
304        # generic system
305        mdesc = SysConfig()
306    self.readfile = mdesc.script()
307    self.iobus = NoncoherentBus()
308    self.membus = MemBus()
309    self.bridge = Bridge(delay='50ns')
310    self.mem_ranges = [AddrRange('1GB')]
311    self.bridge.master = self.iobus.slave
312    self.bridge.slave = self.membus.master
313    self.disk0 = CowIdeDisk(driveID='master')
314    self.disk2 = CowIdeDisk(driveID='master')
315    self.disk0.childImage(mdesc.disk())
316    self.disk2.childImage(disk('linux-bigswap2.img'))
317    self.malta = BaseMalta()
318    self.malta.attachIO(self.iobus)
319    self.malta.ide.pio = self.iobus.master
320    self.malta.ide.config = self.iobus.master
321    self.malta.ide.dma = self.iobus.slave
322    self.malta.ethernet.pio = self.iobus.master
323    self.malta.ethernet.config = self.iobus.master
324    self.malta.ethernet.dma = self.iobus.slave
325    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
326                                               read_only = True))
327    self.intrctrl = IntrControl()
328    self.mem_mode = mem_mode
329    self.terminal = Terminal()
330    self.kernel = binary('mips/vmlinux')
331    self.console = binary('mips/console')
332    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
333
334    self.system_port = self.membus.slave
335
336    return self
337
338def x86IOAddress(port):
339    IO_address_space_base = 0x8000000000000000
340    return IO_address_space_base + port
341
342def connectX86ClassicSystem(x86_sys, numCPUs):
343    # Constants similar to x86_traits.hh
344    IO_address_space_base = 0x8000000000000000
345    pci_config_address_space_base = 0xc000000000000000
346    interrupts_address_space_base = 0xa000000000000000
347    APIC_range_size = 1 << 12;
348
349    x86_sys.membus = MemBus()
350
351    # North Bridge
352    x86_sys.iobus = NoncoherentBus()
353    x86_sys.bridge = Bridge(delay='50ns')
354    x86_sys.bridge.master = x86_sys.iobus.slave
355    x86_sys.bridge.slave = x86_sys.membus.master
356    # Allow the bridge to pass through the IO APIC (two pages),
357    # everything in the IO address range up to the local APIC, and
358    # then the entire PCI address space and beyond
359    x86_sys.bridge.ranges = \
360        [
361        AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
362                  x86_sys.pc.south_bridge.io_apic.pio_addr +
363                  APIC_range_size - 1),
364        AddrRange(IO_address_space_base,
365                  interrupts_address_space_base - 1),
366        AddrRange(pci_config_address_space_base,
367                  Addr.max)
368        ]
369
370    # Create a bridge from the IO bus to the memory bus to allow access to
371    # the local APIC (two pages)
372    x86_sys.apicbridge = Bridge(delay='50ns')
373    x86_sys.apicbridge.slave = x86_sys.iobus.master
374    x86_sys.apicbridge.master = x86_sys.membus.slave
375    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
376                                           interrupts_address_space_base +
377                                           numCPUs * APIC_range_size
378                                           - 1)]
379
380    # connect the io bus
381    x86_sys.pc.attachIO(x86_sys.iobus)
382
383    x86_sys.system_port = x86_sys.membus.slave
384
385def connectX86RubySystem(x86_sys):
386    # North Bridge
387    x86_sys.piobus = NoncoherentBus()
388
389    # add the ide to the list of dma devices that later need to attach to
390    # dma controllers
391    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
392    x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
393
394
395def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
396                  Ruby = False):
397    if self == None:
398        self = X86System()
399
400    if not mdesc:
401        # generic system
402        mdesc = SysConfig()
403    self.readfile = mdesc.script()
404
405    self.mem_mode = mem_mode
406
407    # Physical memory
408    self.mem_ranges = [AddrRange(mdesc.mem())]
409
410    # Platform
411    self.pc = Pc()
412
413    # Create and connect the busses required by each memory system
414    if Ruby:
415        connectX86RubySystem(self)
416    else:
417        connectX86ClassicSystem(self, numCPUs)
418
419    self.intrctrl = IntrControl()
420
421    # Disks
422    disk0 = CowIdeDisk(driveID='master')
423    disk2 = CowIdeDisk(driveID='master')
424    disk0.childImage(mdesc.disk())
425    disk2.childImage(disk('linux-bigswap2.img'))
426    self.pc.south_bridge.ide.disks = [disk0, disk2]
427
428    # Add in a Bios information structure.
429    structures = [X86SMBiosBiosInformation()]
430    self.smbios_table.structures = structures
431
432    # Set up the Intel MP table
433    base_entries = []
434    ext_entries = []
435    for i in xrange(numCPUs):
436        bp = X86IntelMPProcessor(
437                local_apic_id = i,
438                local_apic_version = 0x14,
439                enable = True,
440                bootstrap = (i == 0))
441        base_entries.append(bp)
442    io_apic = X86IntelMPIOAPIC(
443            id = numCPUs,
444            version = 0x11,
445            enable = True,
446            address = 0xfec00000)
447    self.pc.south_bridge.io_apic.apic_id = io_apic.id
448    base_entries.append(io_apic)
449    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
450    base_entries.append(isa_bus)
451    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
452    base_entries.append(pci_bus)
453    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
454            subtractive_decode=True, parent_bus=1)
455    ext_entries.append(connect_busses)
456    pci_dev4_inta = X86IntelMPIOIntAssignment(
457            interrupt_type = 'INT',
458            polarity = 'ConformPolarity',
459            trigger = 'ConformTrigger',
460            source_bus_id = 1,
461            source_bus_irq = 0 + (4 << 2),
462            dest_io_apic_id = io_apic.id,
463            dest_io_apic_intin = 16)
464    base_entries.append(pci_dev4_inta)
465    def assignISAInt(irq, apicPin):
466        assign_8259_to_apic = X86IntelMPIOIntAssignment(
467                interrupt_type = 'ExtInt',
468                polarity = 'ConformPolarity',
469                trigger = 'ConformTrigger',
470                source_bus_id = 0,
471                source_bus_irq = irq,
472                dest_io_apic_id = io_apic.id,
473                dest_io_apic_intin = 0)
474        base_entries.append(assign_8259_to_apic)
475        assign_to_apic = X86IntelMPIOIntAssignment(
476                interrupt_type = 'INT',
477                polarity = 'ConformPolarity',
478                trigger = 'ConformTrigger',
479                source_bus_id = 0,
480                source_bus_irq = irq,
481                dest_io_apic_id = io_apic.id,
482                dest_io_apic_intin = apicPin)
483        base_entries.append(assign_to_apic)
484    assignISAInt(0, 2)
485    assignISAInt(1, 1)
486    for i in range(3, 15):
487        assignISAInt(i, i)
488    self.intel_mp_table.base_entries = base_entries
489    self.intel_mp_table.ext_entries = ext_entries
490
491def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
492                       Ruby = False):
493    self = LinuxX86System()
494
495    # Build up the x86 system and then specialize it for Linux
496    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
497
498    # We assume below that there's at least 1MB of memory. We'll require 2
499    # just to avoid corner cases.
500    phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
501    assert(phys_mem_size >= 0x200000)
502
503    self.e820_table.entries = \
504       [
505        # Mark the first megabyte of memory as reserved
506        X86E820Entry(addr = 0, size = '639kB', range_type = 1),
507        X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
508        # Mark the rest as available
509        X86E820Entry(addr = 0x100000,
510                size = '%dB' % (phys_mem_size - 0x100000),
511                range_type = 1)
512        ]
513
514    # Command line
515    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
516                        'root=/dev/hda1'
517    return self
518
519
520def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
521    self = Root(full_system = full_system)
522    self.testsys = testSystem
523    self.drivesys = driveSystem
524    self.etherlink = EtherLink()
525    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
526    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
527
528    if hasattr(testSystem, 'realview'):
529        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
530        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
531    elif hasattr(testSystem, 'tsunami'):
532        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
533        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
534    else:
535        fatal("Don't know how to connect these system together")
536
537    if dumpfile:
538        self.etherdump = EtherDump(file=dumpfile)
539        self.etherlink.dump = Parent.etherdump
540
541    return self
542