FSConfig.py revision 9707:1305bec2733f
12810SN/A# Copyright (c) 2010-2012 ARM Limited 29614Srene.dejong@arm.com# All rights reserved. 38856Sandreas.hansson@arm.com# 48856Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58856Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68856Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78856Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88856Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98856Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108856Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118856Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128856Sandreas.hansson@arm.com# 138856Sandreas.hansson@arm.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 142810SN/A# Copyright (c) 2006-2008 The Regents of The University of Michigan 152810SN/A# All rights reserved. 162810SN/A# 172810SN/A# Redistribution and use in source and binary forms, with or without 182810SN/A# modification, are permitted provided that the following conditions are 192810SN/A# met: redistributions of source code must retain the above copyright 202810SN/A# notice, this list of conditions and the following disclaimer; 212810SN/A# redistributions in binary form must reproduce the above copyright 222810SN/A# notice, this list of conditions and the following disclaimer in the 232810SN/A# documentation and/or other materials provided with the distribution; 242810SN/A# neither the name of the copyright holders nor the names of its 252810SN/A# contributors may be used to endorse or promote products derived from 262810SN/A# this software without specific prior written permission. 272810SN/A# 282810SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A# 402810SN/A# Authors: Kevin Lim 412810SN/A 422810SN/Afrom m5.objects import * 432810SN/Afrom Benchmarks import * 442810SN/Afrom m5.util import convert 452810SN/A 462810SN/Aclass CowIdeDisk(IdeDisk): 472810SN/A image = CowDiskImage(child=RawDiskImage(read_only=True), 488232Snate@binkert.org read_only=False) 499152Satgutier@umich.edu 509795Sandreas.hansson@arm.com def childImage(self, ci): 519795Sandreas.hansson@arm.com self.image.child.image_file = ci 5210263Satgutier@umich.edu 535338Sstever@gmail.comclass MemBus(CoherentBus): 549795Sandreas.hansson@arm.com badaddr_responder = BadAddr() 555338Sstever@gmail.com default = Self.badaddr_responder.pio 568786Sgblack@eecs.umich.edu 572810SN/A 582810SN/Adef makeLinuxAlphaSystem(mem_mode, MemClass, mdesc = None): 592810SN/A IO_address_space_base = 0x80000000000 608856Sandreas.hansson@arm.com class BaseTsunami(Tsunami): 618856Sandreas.hansson@arm.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 628856Sandreas.hansson@arm.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 638922Swilliam.wang@arm.com pci_func=0, pci_dev=0, pci_bus=0) 648914Sandreas.hansson@arm.com 658856Sandreas.hansson@arm.com self = LinuxAlphaSystem() 668856Sandreas.hansson@arm.com if not mdesc: 674475SN/A # generic system 6811053Sandreas.hansson@arm.com mdesc = SysConfig() 695034SN/A self.readfile = mdesc.script() 7010360Sandreas.hansson@arm.com self.iobus = NoncoherentBus() 7110622Smitch.hayenga@arm.com self.membus = MemBus() 7210622Smitch.hayenga@arm.com # By default the bridge responds to all addresses above the I/O 734628SN/A # base address (including the PCI config space) 7411053Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns', 7510693SMarco.Balboni@ARM.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 7610693SMarco.Balboni@ARM.com self.physmem = MemClass(range = AddrRange(mdesc.mem())) 7710693SMarco.Balboni@ARM.com self.mem_ranges = [self.physmem.range] 789263Smrinmoy.ghosh@arm.com self.bridge.master = self.iobus.slave 795034SN/A self.bridge.slave = self.membus.master 8011331Sandreas.hansson@arm.com self.physmem.port = self.membus.master 8110884Sandreas.hansson@arm.com self.disk0 = CowIdeDisk(driveID='master') 824626SN/A self.disk2 = CowIdeDisk(driveID='master') 8310360Sandreas.hansson@arm.com self.disk0.childImage(mdesc.disk()) 844626SN/A self.disk2.childImage(disk('linux-bigswap2.img')) 855034SN/A self.tsunami = BaseTsunami() 868883SAli.Saidi@ARM.com self.tsunami.attachIO(self.iobus) 878833Sdam.sunwoo@arm.com self.tsunami.ide.pio = self.iobus.master 884458SN/A self.tsunami.ide.config = self.iobus.master 8911331Sandreas.hansson@arm.com self.tsunami.ide.dma = self.iobus.slave 9011331Sandreas.hansson@arm.com self.tsunami.ethernet.pio = self.iobus.master 912810SN/A self.tsunami.ethernet.config = self.iobus.master 922810SN/A self.tsunami.ethernet.dma = self.iobus.slave 933013SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 948856Sandreas.hansson@arm.com read_only = True)) 952810SN/A self.intrctrl = IntrControl() 963013SN/A self.mem_mode = mem_mode 9710714Sandreas.hansson@arm.com self.terminal = Terminal() 982810SN/A self.kernel = binary('vmlinux') 999614Srene.dejong@arm.com self.pal = binary('ts_osfpal') 1009614Srene.dejong@arm.com self.console = binary('console') 1019614Srene.dejong@arm.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 10210345SCurtis.Dunham@arm.com 10310714Sandreas.hansson@arm.com self.system_port = self.membus.slave 10410345SCurtis.Dunham@arm.com 1059614Srene.dejong@arm.com return self 1062810SN/A 1072810SN/Adef makeLinuxAlphaRubySystem(mem_mode, MemClass, mdesc = None): 1082810SN/A class BaseTsunami(Tsunami): 1098856Sandreas.hansson@arm.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1102810SN/A ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1113013SN/A pci_func=0, pci_dev=0, pci_bus=0) 11210714Sandreas.hansson@arm.com 1133013SN/A physmem = MemClass(range = AddrRange(mdesc.mem())) 1148856Sandreas.hansson@arm.com self = LinuxAlphaSystem(physmem = physmem) 11510714Sandreas.hansson@arm.com self.mem_ranges = [self.physmem.range] 1168922Swilliam.wang@arm.com if not mdesc: 1172897SN/A # generic system 1182810SN/A mdesc = SysConfig() 1192810SN/A self.readfile = mdesc.script() 12010344Sandreas.hansson@arm.com 12110344Sandreas.hansson@arm.com # Create pio bus to connect all device pio ports to rubymem's pio port 12210344Sandreas.hansson@arm.com self.piobus = NoncoherentBus() 12310714Sandreas.hansson@arm.com 12410344Sandreas.hansson@arm.com # 12510344Sandreas.hansson@arm.com # Pio functional accesses from devices need direct access to memory 12610344Sandreas.hansson@arm.com # RubyPort currently does support functional accesses. Therefore provide 12710713Sandreas.hansson@arm.com # the piobus a direct connection to physical memory 12810344Sandreas.hansson@arm.com # 1292844SN/A self.piobus.master = physmem.port 1302810SN/A 1312858SN/A self.disk0 = CowIdeDisk(driveID='master') 1322858SN/A self.disk2 = CowIdeDisk(driveID='master') 1338856Sandreas.hansson@arm.com self.disk0.childImage(mdesc.disk()) 1348922Swilliam.wang@arm.com self.disk2.childImage(disk('linux-bigswap2.img')) 1358711Sandreas.hansson@arm.com self.tsunami = BaseTsunami() 13611331Sandreas.hansson@arm.com self.tsunami.attachIO(self.piobus) 1372858SN/A self.tsunami.ide.pio = self.piobus.master 1382858SN/A self.tsunami.ide.config = self.piobus.master 1399294Sandreas.hansson@arm.com self.tsunami.ethernet.pio = self.piobus.master 1409294Sandreas.hansson@arm.com self.tsunami.ethernet.config = self.piobus.master 1418922Swilliam.wang@arm.com 1428922Swilliam.wang@arm.com # 1438922Swilliam.wang@arm.com # Store the dma devices for later connection to dma ruby ports. 1448922Swilliam.wang@arm.com # Append an underscore to dma_devices to avoid the SimObjectVector check. 1458922Swilliam.wang@arm.com # 1468922Swilliam.wang@arm.com self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 1478922Swilliam.wang@arm.com 1488922Swilliam.wang@arm.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1499294Sandreas.hansson@arm.com read_only = True)) 1509294Sandreas.hansson@arm.com self.intrctrl = IntrControl() 1518922Swilliam.wang@arm.com self.mem_mode = mem_mode 1528922Swilliam.wang@arm.com self.terminal = Terminal() 1538922Swilliam.wang@arm.com self.kernel = binary('vmlinux') 1548922Swilliam.wang@arm.com self.pal = binary('ts_osfpal') 1558922Swilliam.wang@arm.com self.console = binary('console') 1568922Swilliam.wang@arm.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1578922Swilliam.wang@arm.com 1584628SN/A return self 15910821Sandreas.hansson@arm.com 16010821Sandreas.hansson@arm.comdef makeSparcSystem(mem_mode, MemClass, mdesc = None): 16110821Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 16210821Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 16310821Sandreas.hansson@arm.com uart_pio_size = 8 16410821Sandreas.hansson@arm.com 16510821Sandreas.hansson@arm.com class CowMmDisk(MmDisk): 16610821Sandreas.hansson@arm.com image = CowDiskImage(child=RawDiskImage(read_only=True), 16710821Sandreas.hansson@arm.com read_only=False) 16810821Sandreas.hansson@arm.com 16910821Sandreas.hansson@arm.com def childImage(self, ci): 1702858SN/A self.image.child.image_file = ci 1712810SN/A 1722810SN/A self = SparcSystem() 1732810SN/A if not mdesc: 1742810SN/A # generic system 1752810SN/A mdesc = SysConfig() 1764022SN/A self.readfile = mdesc.script() 1774022SN/A self.iobus = NoncoherentBus() 1784022SN/A self.membus = MemBus() 1792810SN/A self.bridge = Bridge(delay='50ns') 1802810SN/A self.t1000 = T1000() 1818833Sdam.sunwoo@arm.com self.t1000.attachOnChipIO(self.membus) 1822810SN/A self.t1000.attachIO(self.iobus) 1832810SN/A self.physmem = MemClass(range = AddrRange(Addr('1MB'), size = '64MB')) 1842810SN/A self.physmem2 = MemClass(range = AddrRange(Addr('2GB'), size ='256MB')) 1852810SN/A self.mem_ranges = [self.physmem.range, self.physmem2.range] 1868833Sdam.sunwoo@arm.com self.bridge.master = self.iobus.slave 1878833Sdam.sunwoo@arm.com self.bridge.slave = self.membus.master 1888833Sdam.sunwoo@arm.com self.physmem.port = self.membus.master 1892810SN/A self.physmem2.port = self.membus.master 1902810SN/A self.rom.port = self.membus.master 1914871SN/A self.nvram.port = self.membus.master 1924871SN/A self.hypervisor_desc.port = self.membus.master 1934871SN/A self.partition_desc.port = self.membus.master 1944871SN/A self.intrctrl = IntrControl() 19510885Sandreas.hansson@arm.com self.disk0 = CowMmDisk() 19610885Sandreas.hansson@arm.com self.disk0.childImage(disk('disk.s10hw2')) 1974871SN/A self.disk0.pio = self.iobus.master 1984871SN/A 1994871SN/A # The puart0 and hvuart are placed on the IO bus, so create ranges 2004871SN/A # for them. The remaining IO range is rather fragmented, so poke 2014871SN/A # holes for the iob and partition descriptors etc. 2022810SN/A self.bridge.ranges = \ 2032810SN/A [ 2042810SN/A AddrRange(self.t1000.puart0.pio_addr, 2058833Sdam.sunwoo@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 2062810SN/A AddrRange(self.disk0.pio_addr, 2074871SN/A self.t1000.fake_jbi.pio_addr + 2088833Sdam.sunwoo@arm.com self.t1000.fake_jbi.pio_size - 1), 2098833Sdam.sunwoo@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 2108833Sdam.sunwoo@arm.com iob_man_addr - 1), 2112810SN/A AddrRange(self.t1000.fake_l2_1.pio_addr, 2122810SN/A self.t1000.fake_ssi.pio_addr + 2132810SN/A self.t1000.fake_ssi.pio_size - 1), 2142810SN/A AddrRange(self.t1000.hvuart.pio_addr, 2158833Sdam.sunwoo@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 2162810SN/A ] 2174871SN/A self.reset_bin = binary('reset_new.bin') 2188833Sdam.sunwoo@arm.com self.hypervisor_bin = binary('q_new.bin') 2198833Sdam.sunwoo@arm.com self.openboot_bin = binary('openboot_new.bin') 2208833Sdam.sunwoo@arm.com self.nvram_bin = binary('nvram1') 2212810SN/A self.hypervisor_desc_bin = binary('1up-hv.bin') 2222810SN/A self.partition_desc_bin = binary('1up-md.bin') 2234022SN/A 2244022SN/A self.system_port = self.membus.slave 2254022SN/A 2262810SN/A return self 2272810SN/A 2288833Sdam.sunwoo@arm.comdef makeArmSystem(mem_mode, machine_type, MemClass, mdesc = None, 2292810SN/A dtb_filename = None, bare_metal=False): 2302810SN/A assert machine_type 2312810SN/A 2322810SN/A if bare_metal: 2338833Sdam.sunwoo@arm.com self = ArmSystem() 2348833Sdam.sunwoo@arm.com else: 2358833Sdam.sunwoo@arm.com self = LinuxArmSystem() 2362810SN/A 2372810SN/A if not mdesc: 2382810SN/A # generic system 2392810SN/A mdesc = SysConfig() 2402810SN/A 2418833Sdam.sunwoo@arm.com self.readfile = mdesc.script() 2422810SN/A self.iobus = NoncoherentBus() 2434871SN/A self.membus = MemBus() 2448833Sdam.sunwoo@arm.com self.membus.badaddr_responder.warn_access = "warn" 2458833Sdam.sunwoo@arm.com self.bridge = Bridge(delay='50ns') 2468833Sdam.sunwoo@arm.com self.bridge.master = self.iobus.slave 2472810SN/A self.bridge.slave = self.membus.master 2482810SN/A 2492810SN/A self.mem_mode = mem_mode 2502810SN/A 2518833Sdam.sunwoo@arm.com if machine_type == "RealView_PBX": 2522810SN/A self.realview = RealViewPBX() 2534871SN/A elif machine_type == "RealView_EB": 2548833Sdam.sunwoo@arm.com self.realview = RealViewEB() 2558833Sdam.sunwoo@arm.com elif machine_type == "VExpress_ELT": 2568833Sdam.sunwoo@arm.com self.realview = VExpress_ELT() 2572810SN/A elif machine_type == "VExpress_EMM": 2582810SN/A self.realview = VExpress_EMM() 2594022SN/A self.load_addr_mask = 0xffffffff 2604022SN/A else: 2614022SN/A print "Unknown Machine Type" 2622810SN/A sys.exit(1) 2632810SN/A 2648833Sdam.sunwoo@arm.com self.cf0 = CowIdeDisk(driveID='master') 2652810SN/A self.cf0.childImage(mdesc.disk()) 2662810SN/A # default to an IDE controller rather than a CF one 2672810SN/A # assuming we've got one 2682810SN/A try: 2698833Sdam.sunwoo@arm.com self.realview.ide.disks = [self.cf0] 2708833Sdam.sunwoo@arm.com except: 2718833Sdam.sunwoo@arm.com self.realview.cf_ctrl.disks = [self.cf0] 2722810SN/A 2732810SN/A if bare_metal: 2742810SN/A # EOT character on UART will end the simulation 2752810SN/A self.realview.uart.end_on_eot = True 2762810SN/A self.physmem = MemClass(range = AddrRange(Addr(mdesc.mem()))) 2778833Sdam.sunwoo@arm.com self.mem_ranges = [self.physmem.range] 2782810SN/A else: 2794871SN/A self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 2808833Sdam.sunwoo@arm.com if dtb_filename is not None: 2818833Sdam.sunwoo@arm.com self.dtb_filename = dtb_filename 2828833Sdam.sunwoo@arm.com self.machine_type = machine_type 2832810SN/A if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 2842810SN/A print "The currently selected ARM platforms doesn't support" 2852810SN/A print " the amount of DRAM you've selected. Please try" 2862810SN/A print " another platform" 2878833Sdam.sunwoo@arm.com sys.exit(1) 2882810SN/A 2894871SN/A boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 2908833Sdam.sunwoo@arm.com 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 2918833Sdam.sunwoo@arm.com 2928833Sdam.sunwoo@arm.com self.physmem = MemClass(range = AddrRange(self.realview.mem_start_addr, 2932810SN/A size = mdesc.mem()), 2942810SN/A conf_table_reported = True) 2954022SN/A self.mem_ranges = [self.physmem.range] 2964022SN/A self.realview.setupBootLoader(self.membus, self, binary) 2974022SN/A self.gic_cpu_addr = self.realview.gic.cpu_addr 2982810SN/A self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2992810SN/A 3002810SN/A if mdesc.disk().lower().count('android'): 3012810SN/A boot_flags += " init=/init " 3022810SN/A self.boot_osflags = boot_flags 3032810SN/A 3048833Sdam.sunwoo@arm.com self.physmem.port = self.membus.master 3052810SN/A self.realview.attachOnChipIO(self.membus, self.bridge) 3068833Sdam.sunwoo@arm.com self.realview.attachIO(self.iobus) 3078833Sdam.sunwoo@arm.com self.intrctrl = IntrControl() 3088833Sdam.sunwoo@arm.com self.terminal = Terminal() 3092810SN/A self.vncserver = VncServer() 3102810SN/A 3112810SN/A self.system_port = self.membus.slave 3122810SN/A 3132810SN/A return self 3148833Sdam.sunwoo@arm.com 3152810SN/A 3162810SN/Adef makeLinuxMipsSystem(mem_mode, MemClass, mdesc = None): 3178833Sdam.sunwoo@arm.com class BaseMalta(Malta): 3188833Sdam.sunwoo@arm.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3198833Sdam.sunwoo@arm.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3202810SN/A pci_func=0, pci_dev=0, pci_bus=0) 3212810SN/A 3222810SN/A self = LinuxMipsSystem() 3232810SN/A if not mdesc: 3248833Sdam.sunwoo@arm.com # generic system 3252810SN/A mdesc = SysConfig() 3262810SN/A self.readfile = mdesc.script() 3278833Sdam.sunwoo@arm.com self.iobus = NoncoherentBus() 3288833Sdam.sunwoo@arm.com self.membus = MemBus() 3298833Sdam.sunwoo@arm.com self.bridge = Bridge(delay='50ns') 3302810SN/A self.physmem = MemClass(range = AddrRange('1GB')) 3312810SN/A self.mem_ranges = [self.physmem.range] 3324022SN/A self.bridge.master = self.iobus.slave 3334022SN/A self.bridge.slave = self.membus.master 3344022SN/A self.physmem.port = self.membus.master 3352810SN/A self.disk0 = CowIdeDisk(driveID='master') 3362810SN/A self.disk2 = CowIdeDisk(driveID='master') 3372810SN/A self.disk0.childImage(mdesc.disk()) 3382810SN/A self.disk2.childImage(disk('linux-bigswap2.img')) 3392810SN/A self.malta = BaseMalta() 3402810SN/A self.malta.attachIO(self.iobus) 3418833Sdam.sunwoo@arm.com self.malta.ide.pio = self.iobus.master 3422810SN/A self.malta.ide.config = self.iobus.master 3438833Sdam.sunwoo@arm.com self.malta.ide.dma = self.iobus.slave 3448833Sdam.sunwoo@arm.com self.malta.ethernet.pio = self.iobus.master 3458833Sdam.sunwoo@arm.com self.malta.ethernet.config = self.iobus.master 3462810SN/A self.malta.ethernet.dma = self.iobus.slave 3472810SN/A self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3482810SN/A read_only = True)) 3492810SN/A self.intrctrl = IntrControl() 3502810SN/A self.mem_mode = mem_mode 3518833Sdam.sunwoo@arm.com self.terminal = Terminal() 3522810SN/A self.kernel = binary('mips/vmlinux') 3532810SN/A self.console = binary('mips/console') 3548833Sdam.sunwoo@arm.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 3558833Sdam.sunwoo@arm.com 3568833Sdam.sunwoo@arm.com self.system_port = self.membus.slave 3572810SN/A 3582810SN/A return self 3592810SN/A 3602810SN/Adef x86IOAddress(port): 3618833Sdam.sunwoo@arm.com IO_address_space_base = 0x8000000000000000 3622810SN/A return IO_address_space_base + port 3632810SN/A 3648833Sdam.sunwoo@arm.comdef connectX86ClassicSystem(x86_sys, numCPUs): 3658833Sdam.sunwoo@arm.com # Constants similar to x86_traits.hh 3668833Sdam.sunwoo@arm.com IO_address_space_base = 0x8000000000000000 3672810SN/A pci_config_address_space_base = 0xc000000000000000 3682810SN/A interrupts_address_space_base = 0xa000000000000000 3694022SN/A APIC_range_size = 1 << 12; 3704022SN/A 3714022SN/A x86_sys.membus = MemBus() 3722810SN/A x86_sys.physmem.port = x86_sys.membus.master 3732810SN/A 3742810SN/A # North Bridge 3752810SN/A x86_sys.iobus = NoncoherentBus() 3762810SN/A x86_sys.bridge = Bridge(delay='50ns') 3772810SN/A x86_sys.bridge.master = x86_sys.iobus.slave 3782810SN/A x86_sys.bridge.slave = x86_sys.membus.master 3792810SN/A # Allow the bridge to pass through the IO APIC (two pages), 3808833Sdam.sunwoo@arm.com # everything in the IO address range up to the local APIC, and 3818833Sdam.sunwoo@arm.com # then the entire PCI address space and beyond 3828833Sdam.sunwoo@arm.com x86_sys.bridge.ranges = \ 3838833Sdam.sunwoo@arm.com [ 3842810SN/A AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 3852810SN/A x86_sys.pc.south_bridge.io_apic.pio_addr + 3862810SN/A APIC_range_size - 1), 3872810SN/A AddrRange(IO_address_space_base, 3882810SN/A interrupts_address_space_base - 1), 3898833Sdam.sunwoo@arm.com AddrRange(pci_config_address_space_base, 3902810SN/A Addr.max) 3912810SN/A ] 3928833Sdam.sunwoo@arm.com 3938833Sdam.sunwoo@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 3948833Sdam.sunwoo@arm.com # the local APIC (two pages) 3952810SN/A x86_sys.apicbridge = Bridge(delay='50ns') 3962810SN/A x86_sys.apicbridge.slave = x86_sys.iobus.master 3972810SN/A x86_sys.apicbridge.master = x86_sys.membus.slave 3982810SN/A x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 3998833Sdam.sunwoo@arm.com interrupts_address_space_base + 4002810SN/A numCPUs * APIC_range_size 4012810SN/A - 1)] 4028833Sdam.sunwoo@arm.com 4038833Sdam.sunwoo@arm.com # connect the io bus 4048833Sdam.sunwoo@arm.com x86_sys.pc.attachIO(x86_sys.iobus) 4052810SN/A 4062810SN/A x86_sys.system_port = x86_sys.membus.slave 4072810SN/A 4082810SN/Adef connectX86RubySystem(x86_sys): 4092810SN/A # North Bridge 4102810SN/A x86_sys.piobus = NoncoherentBus() 4112810SN/A 4122810SN/A # 4132810SN/A # Pio functional accesses from devices need direct access to memory 4142810SN/A # RubyPort currently does support functional accesses. Therefore provide 4152810SN/A # the piobus a direct connection to physical memory 4162810SN/A # 4172810SN/A x86_sys.piobus.master = x86_sys.physmem.port 4182810SN/A # add the ide to the list of dma devices that later need to attach to 4192810SN/A # dma controllers 4202810SN/A x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 4212810SN/A x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) 4222810SN/A 4232810SN/A 4242810SN/Adef makeX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, self = None, 4252810SN/A Ruby = False): 4262810SN/A if self == None: 4272810SN/A self = X86System() 4282810SN/A 4292810SN/A if not mdesc: 4302810SN/A # generic system 4312810SN/A mdesc = SysConfig() 4322810SN/A self.readfile = mdesc.script() 4332810SN/A 4342810SN/A self.mem_mode = mem_mode 4352810SN/A 4362810SN/A # Physical memory 4372810SN/A self.physmem = MemClass(range = AddrRange(mdesc.mem())) 4382810SN/A self.mem_ranges = [self.physmem.range] 4392810SN/A 4402810SN/A # Platform 4412826SN/A self.pc = Pc() 4424626SN/A 4438833Sdam.sunwoo@arm.com # Create and connect the busses required by each memory system 4444626SN/A if Ruby: 4454626SN/A connectX86RubySystem(self) 4468833Sdam.sunwoo@arm.com else: 4474626SN/A connectX86ClassicSystem(self, numCPUs) 4488833Sdam.sunwoo@arm.com 4498833Sdam.sunwoo@arm.com self.intrctrl = IntrControl() 4508833Sdam.sunwoo@arm.com 4514626SN/A # Disks 4524626SN/A disk0 = CowIdeDisk(driveID='master') 4534626SN/A disk2 = CowIdeDisk(driveID='master') 4544626SN/A disk0.childImage(mdesc.disk()) 4554626SN/A disk2.childImage(disk('linux-bigswap2.img')) 4564626SN/A self.pc.south_bridge.ide.disks = [disk0, disk2] 4574626SN/A 4584626SN/A # Add in a Bios information structure. 4598833Sdam.sunwoo@arm.com structures = [X86SMBiosBiosInformation()] 4604626SN/A self.smbios_table.structures = structures 4614626SN/A 4624626SN/A # Set up the Intel MP table 4634626SN/A base_entries = [] 4648833Sdam.sunwoo@arm.com ext_entries = [] 4658833Sdam.sunwoo@arm.com for i in xrange(numCPUs): 4668833Sdam.sunwoo@arm.com bp = X86IntelMPProcessor( 4674626SN/A local_apic_id = i, 4684626SN/A local_apic_version = 0x14, 4694626SN/A enable = True, 4704626SN/A bootstrap = (i == 0)) 4714626SN/A base_entries.append(bp) 4728833Sdam.sunwoo@arm.com io_apic = X86IntelMPIOAPIC( 4734626SN/A id = numCPUs, 4744871SN/A version = 0x11, 4758833Sdam.sunwoo@arm.com enable = True, 4768833Sdam.sunwoo@arm.com address = 0xfec00000) 4778833Sdam.sunwoo@arm.com self.pc.south_bridge.io_apic.apic_id = io_apic.id 4784626SN/A base_entries.append(io_apic) 4794626SN/A isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 4804626SN/A base_entries.append(isa_bus) 4814626SN/A pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 4828833Sdam.sunwoo@arm.com base_entries.append(pci_bus) 4834626SN/A connect_busses = X86IntelMPBusHierarchy(bus_id=0, 4844871SN/A subtractive_decode=True, parent_bus=1) 4858833Sdam.sunwoo@arm.com ext_entries.append(connect_busses) 4868833Sdam.sunwoo@arm.com pci_dev4_inta = X86IntelMPIOIntAssignment( 4878833Sdam.sunwoo@arm.com interrupt_type = 'INT', 4884626SN/A polarity = 'ConformPolarity', 4894626SN/A trigger = 'ConformTrigger', 4904626SN/A source_bus_id = 1, 4914626SN/A source_bus_irq = 0 + (4 << 2), 4924626SN/A dest_io_apic_id = io_apic.id, 4934626SN/A dest_io_apic_intin = 16) 4944626SN/A base_entries.append(pci_dev4_inta) 4958833Sdam.sunwoo@arm.com def assignISAInt(irq, apicPin): 4964626SN/A assign_8259_to_apic = X86IntelMPIOIntAssignment( 4974626SN/A interrupt_type = 'ExtInt', 4984626SN/A polarity = 'ConformPolarity', 4994626SN/A trigger = 'ConformTrigger', 5008833Sdam.sunwoo@arm.com source_bus_id = 0, 5018833Sdam.sunwoo@arm.com source_bus_irq = irq, 5028833Sdam.sunwoo@arm.com dest_io_apic_id = io_apic.id, 5034626SN/A dest_io_apic_intin = 0) 5044626SN/A base_entries.append(assign_8259_to_apic) 5054626SN/A assign_to_apic = X86IntelMPIOIntAssignment( 5064626SN/A interrupt_type = 'INT', 5074626SN/A polarity = 'ConformPolarity', 5088833Sdam.sunwoo@arm.com trigger = 'ConformTrigger', 5094626SN/A source_bus_id = 0, 5104871SN/A source_bus_irq = irq, 5118833Sdam.sunwoo@arm.com dest_io_apic_id = io_apic.id, 5128833Sdam.sunwoo@arm.com dest_io_apic_intin = apicPin) 5138833Sdam.sunwoo@arm.com base_entries.append(assign_to_apic) 5144626SN/A assignISAInt(0, 2) 5154626SN/A assignISAInt(1, 1) 5164626SN/A for i in range(3, 15): 5174626SN/A assignISAInt(i, i) 5188833Sdam.sunwoo@arm.com self.intel_mp_table.base_entries = base_entries 5194626SN/A self.intel_mp_table.ext_entries = ext_entries 5204871SN/A 5218833Sdam.sunwoo@arm.comdef makeLinuxX86System(mem_mode, MemClass, numCPUs = 1, mdesc = None, 5228833Sdam.sunwoo@arm.com Ruby = False): 5238833Sdam.sunwoo@arm.com self = LinuxX86System() 5244626SN/A 5254626SN/A # Build up the x86 system and then specialize it for Linux 5264626SN/A makeX86System(mem_mode, MemClass, numCPUs, mdesc, self, Ruby) 5274626SN/A 5284626SN/A # We assume below that there's at least 1MB of memory. We'll require 2 5294626SN/A # just to avoid corner cases. 5304626SN/A phys_mem_size = sum(map(lambda mem: mem.range.size(), 5318833Sdam.sunwoo@arm.com self.memories.unproxy(self))) 5324626SN/A assert(phys_mem_size >= 0x200000) 5334626SN/A 5344626SN/A self.e820_table.entries = \ 5354626SN/A [ 5368833Sdam.sunwoo@arm.com # Mark the first megabyte of memory as reserved 5378833Sdam.sunwoo@arm.com X86E820Entry(addr = 0, size = '639kB', range_type = 1), 5388833Sdam.sunwoo@arm.com X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 5394626SN/A # Mark the rest as available 5404626SN/A X86E820Entry(addr = 0x100000, 5414626SN/A size = '%dB' % (phys_mem_size - 0x100000), 5424626SN/A range_type = 1) 5434626SN/A ] 5448833Sdam.sunwoo@arm.com 5454626SN/A # Command line 5464871SN/A self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 5478833Sdam.sunwoo@arm.com 'root=/dev/hda1' 5488833Sdam.sunwoo@arm.com return self 5498833Sdam.sunwoo@arm.com 5504626SN/A 5514626SN/Adef makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 5524626SN/A self = Root(full_system = full_system) 5534626SN/A self.testsys = testSystem 5548833Sdam.sunwoo@arm.com self.drivesys = driveSystem 5554626SN/A self.etherlink = EtherLink() 5564871SN/A self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5574871SN/A self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5588833Sdam.sunwoo@arm.com 5598833Sdam.sunwoo@arm.com if hasattr(testSystem, 'realview'): 5608833Sdam.sunwoo@arm.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 5614626SN/A self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 5624626SN/A elif hasattr(testSystem, 'tsunami'): 5634626SN/A self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5644626SN/A self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5654626SN/A else: 5664626SN/A fatal("Don't know how to connect these system together") 5674626SN/A 5688833Sdam.sunwoo@arm.com if dumpfile: 5694626SN/A self.etherdump = EtherDump(file=dumpfile) 5704626SN/A self.etherlink.dump = Parent.etherdump 5714626SN/A 5724626SN/A return self 5738833Sdam.sunwoo@arm.com