FSConfig.py revision 9622:d351a723eb02
19793Sakash.bagdia@arm.com# Copyright (c) 2010-2012 ARM Limited 28706Sandreas.hansson@arm.com# All rights reserved. 38706Sandreas.hansson@arm.com# 48706Sandreas.hansson@arm.com# The license below extends only to copyright in the software and shall 58706Sandreas.hansson@arm.com# not be construed as granting a license to any other intellectual 68706Sandreas.hansson@arm.com# property including but not limited to intellectual property relating 78706Sandreas.hansson@arm.com# to a hardware implementation of the functionality of the software 88706Sandreas.hansson@arm.com# licensed hereunder. You may use the software subject to the license 98706Sandreas.hansson@arm.com# terms below provided that you ensure that this notice is replicated 108706Sandreas.hansson@arm.com# unmodified and in its entirety in all distributions of the software, 118706Sandreas.hansson@arm.com# modified or unmodified, in source code or in binary form. 128706Sandreas.hansson@arm.com# 135369Ssaidi@eecs.umich.edu# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 143005Sstever@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 153005Sstever@eecs.umich.edu# All rights reserved. 163005Sstever@eecs.umich.edu# 173005Sstever@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 183005Sstever@eecs.umich.edu# modification, are permitted provided that the following conditions are 193005Sstever@eecs.umich.edu# met: redistributions of source code must retain the above copyright 203005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 213005Sstever@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 223005Sstever@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 233005Sstever@eecs.umich.edu# documentation and/or other materials provided with the distribution; 243005Sstever@eecs.umich.edu# neither the name of the copyright holders nor the names of its 253005Sstever@eecs.umich.edu# contributors may be used to endorse or promote products derived from 263005Sstever@eecs.umich.edu# this software without specific prior written permission. 273005Sstever@eecs.umich.edu# 283005Sstever@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293005Sstever@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303005Sstever@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313005Sstever@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323005Sstever@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333005Sstever@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343005Sstever@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353005Sstever@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363005Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373005Sstever@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383005Sstever@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 393005Sstever@eecs.umich.edu# 403005Sstever@eecs.umich.edu# Authors: Kevin Lim 412710SN/A 422710SN/Afrom m5.objects import * 433005Sstever@eecs.umich.edufrom Benchmarks import * 442889SN/Afrom m5.util import convert 456654Snate@binkert.org 466654Snate@binkert.orgclass CowIdeDisk(IdeDisk): 479907Snilay@cs.wisc.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 486654Snate@binkert.org read_only=False) 492667SN/A 506654Snate@binkert.org def childImage(self, ci): 516654Snate@binkert.org self.image.child.image_file = ci 526654Snate@binkert.org 535457Ssaidi@eecs.umich.educlass MemBus(CoherentBus): 5411670Sandreas.hansson@arm.com badaddr_responder = BadAddr() 556654Snate@binkert.org default = Self.badaddr_responder.pio 5611670Sandreas.hansson@arm.com 5711670Sandreas.hansson@arm.com 588169SLisa.Hsu@amd.comdef makeLinuxAlphaSystem(mem_mode, mdesc = None): 598920Snilay@cs.wisc.edu IO_address_space_base = 0x80000000000 603395Shsul@eecs.umich.edu class BaseTsunami(Tsunami): 616981SLisa.Hsu@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 6211251Sradhika.jagtap@ARM.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 639836Sandreas.hansson@arm.com pci_func=0, pci_dev=0, pci_bus=0) 643448Shsul@eecs.umich.edu 655369Ssaidi@eecs.umich.edu self = LinuxAlphaSystem() 663394Shsul@eecs.umich.edu if not mdesc: 6710555Salexandru.dutu@amd.com # generic system 6810555Salexandru.dutu@amd.com mdesc = SysConfig() 6910555Salexandru.dutu@amd.com self.readfile = mdesc.script() 7010555Salexandru.dutu@amd.com self.iobus = NoncoherentBus() 7110555Salexandru.dutu@amd.com self.membus = MemBus() 7210555Salexandru.dutu@amd.com # By default the bridge responds to all addresses above the I/O 7310555Salexandru.dutu@amd.com # base address (including the PCI config space) 749197Snilay@cs.wisc.edu self.bridge = Bridge(delay='50ns', 759197Snilay@cs.wisc.edu ranges = [AddrRange(IO_address_space_base, Addr.max)]) 769197Snilay@cs.wisc.edu self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem())) 779197Snilay@cs.wisc.edu self.mem_ranges = [self.physmem.range] 789197Snilay@cs.wisc.edu self.bridge.master = self.iobus.slave 799197Snilay@cs.wisc.edu self.bridge.slave = self.membus.master 809197Snilay@cs.wisc.edu self.physmem.port = self.membus.master 819197Snilay@cs.wisc.edu self.disk0 = CowIdeDisk(driveID='master') 829197Snilay@cs.wisc.edu self.disk2 = CowIdeDisk(driveID='master') 839197Snilay@cs.wisc.edu self.disk0.childImage(mdesc.disk()) 849197Snilay@cs.wisc.edu self.disk2.childImage(disk('linux-bigswap2.img')) 859197Snilay@cs.wisc.edu self.tsunami = BaseTsunami() 869197Snilay@cs.wisc.edu self.tsunami.attachIO(self.iobus) 879197Snilay@cs.wisc.edu self.tsunami.ide.pio = self.iobus.master 889197Snilay@cs.wisc.edu self.tsunami.ide.config = self.iobus.master 899197Snilay@cs.wisc.edu self.tsunami.ide.dma = self.iobus.slave 909197Snilay@cs.wisc.edu self.tsunami.ethernet.pio = self.iobus.master 919197Snilay@cs.wisc.edu self.tsunami.ethernet.config = self.iobus.master 929197Snilay@cs.wisc.edu self.tsunami.ethernet.dma = self.iobus.slave 939197Snilay@cs.wisc.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 949197Snilay@cs.wisc.edu read_only = True)) 959197Snilay@cs.wisc.edu self.intrctrl = IntrControl() 969197Snilay@cs.wisc.edu self.mem_mode = mem_mode 979907Snilay@cs.wisc.edu self.terminal = Terminal() 989197Snilay@cs.wisc.edu self.kernel = binary('vmlinux') 9910803Sbrandon.potter@amd.com self.pal = binary('ts_osfpal') 10010803Sbrandon.potter@amd.com self.console = binary('console') 10110803Sbrandon.potter@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 10210803Sbrandon.potter@amd.com 1039197Snilay@cs.wisc.edu self.system_port = self.membus.slave 1049217Snilay@cs.wisc.edu 1059197Snilay@cs.wisc.edu return self 1069197Snilay@cs.wisc.edu 1079197Snilay@cs.wisc.edudef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 1089197Snilay@cs.wisc.edu class BaseTsunami(Tsunami): 1099197Snilay@cs.wisc.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1109197Snilay@cs.wisc.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1119197Snilay@cs.wisc.edu pci_func=0, pci_dev=0, pci_bus=0) 1129197Snilay@cs.wisc.edu 1139197Snilay@cs.wisc.edu physmem = SimpleDDR3(range = AddrRange(mdesc.mem())) 1149197Snilay@cs.wisc.edu self = LinuxAlphaSystem(physmem = physmem) 1159197Snilay@cs.wisc.edu self.mem_ranges = [self.physmem.range] 1169197Snilay@cs.wisc.edu if not mdesc: 1179197Snilay@cs.wisc.edu # generic system 1189197Snilay@cs.wisc.edu mdesc = SysConfig() 11910650Sandreas.hansson@arm.com self.readfile = mdesc.script() 1209197Snilay@cs.wisc.edu 1219197Snilay@cs.wisc.edu # Create pio bus to connect all device pio ports to rubymem's pio port 1229197Snilay@cs.wisc.edu self.piobus = NoncoherentBus() 1239197Snilay@cs.wisc.edu 1249197Snilay@cs.wisc.edu # 1252957SN/A # Pio functional accesses from devices need direct access to memory 1268920Snilay@cs.wisc.edu # RubyPort currently does support functional accesses. Therefore provide 1278920Snilay@cs.wisc.edu # the piobus a direct connection to physical memory 1282957SN/A # 1298862Snilay@cs.wisc.edu self.piobus.master = physmem.port 1308862Snilay@cs.wisc.edu 1318467Snilay@cs.wisc.edu self.disk0 = CowIdeDisk(driveID='master') 1322957SN/A self.disk2 = CowIdeDisk(driveID='master') 1332957SN/A self.disk0.childImage(mdesc.disk()) 1342957SN/A self.disk2.childImage(disk('linux-bigswap2.img')) 1352957SN/A self.tsunami = BaseTsunami() 1362957SN/A self.tsunami.attachIO(self.piobus) 1372957SN/A self.tsunami.ide.pio = self.piobus.master 1388167SLisa.Hsu@amd.com self.tsunami.ide.config = self.piobus.master 1399197Snilay@cs.wisc.edu self.tsunami.ethernet.pio = self.piobus.master 1408167SLisa.Hsu@amd.com self.tsunami.ethernet.config = self.piobus.master 1415369Ssaidi@eecs.umich.edu 1428167SLisa.Hsu@amd.com # 1438167SLisa.Hsu@amd.com # Store the dma devices for later connection to dma ruby ports. 1448167SLisa.Hsu@amd.com # Append an underscore to dma_devices to avoid the SimObjectVector check. 1458167SLisa.Hsu@amd.com # 1468167SLisa.Hsu@amd.com self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 1478167SLisa.Hsu@amd.com 1488167SLisa.Hsu@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1498168SLisa.Hsu@amd.com read_only = True)) 15010037SARM gem5 Developers self.intrctrl = IntrControl() 15110037SARM gem5 Developers self.mem_mode = mem_mode 15210037SARM gem5 Developers self.terminal = Terminal() 15310037SARM gem5 Developers self.kernel = binary('vmlinux') 15410037SARM gem5 Developers self.pal = binary('ts_osfpal') 1558168SLisa.Hsu@amd.com self.console = binary('console') 15610037SARM gem5 Developers self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 15710037SARM gem5 Developers 1588167SLisa.Hsu@amd.com return self 1598167SLisa.Hsu@amd.com 16010118Snilay@cs.wisc.edudef makeSparcSystem(mem_mode, mdesc = None): 16110118Snilay@cs.wisc.edu # Constants from iob.cc and uart8250.cc 1625369Ssaidi@eecs.umich.edu iob_man_addr = 0x9800000000 1638920Snilay@cs.wisc.edu uart_pio_size = 8 1649197Snilay@cs.wisc.edu 1658920Snilay@cs.wisc.edu class CowMmDisk(MmDisk): 1668920Snilay@cs.wisc.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1678920Snilay@cs.wisc.edu read_only=False) 1685369Ssaidi@eecs.umich.edu 1695369Ssaidi@eecs.umich.edu def childImage(self, ci): 1708718Snilay@cs.wisc.edu self.image.child.image_file = ci 1719197Snilay@cs.wisc.edu 1729197Snilay@cs.wisc.edu self = SparcSystem() 1739197Snilay@cs.wisc.edu if not mdesc: 1749197Snilay@cs.wisc.edu # generic system 1759197Snilay@cs.wisc.edu mdesc = SysConfig() 1763005Sstever@eecs.umich.edu self.readfile = mdesc.script() 1773395Shsul@eecs.umich.edu self.iobus = NoncoherentBus() 1783395Shsul@eecs.umich.edu self.membus = MemBus() 1799793Sakash.bagdia@arm.com self.bridge = Bridge(delay='50ns') 1809836Sandreas.hansson@arm.com self.t1000 = T1000() 1819815SAndreas Hansson <andreas.hansson> self.t1000.attachOnChipIO(self.membus) 1829793Sakash.bagdia@arm.com self.t1000.attachIO(self.iobus) 18311147Smitch.hayenga@arm.com self.physmem = SimpleDDR3(range = AddrRange(Addr('1MB'), size = '64MB'), 18411147Smitch.hayenga@arm.com zero = True) 18511147Smitch.hayenga@arm.com self.physmem2 = SimpleDDR3(range = AddrRange(Addr('2GB'), size ='256MB'), 1869827Sakash.bagdia@arm.com zero = True) 1879827Sakash.bagdia@arm.com self.mem_ranges = [self.physmem.range, self.physmem2.range] 1889827Sakash.bagdia@arm.com self.bridge.master = self.iobus.slave 1899827Sakash.bagdia@arm.com self.bridge.slave = self.membus.master 1909827Sakash.bagdia@arm.com self.physmem.port = self.membus.master 1919827Sakash.bagdia@arm.com self.physmem2.port = self.membus.master 1929827Sakash.bagdia@arm.com self.rom.port = self.membus.master 1939827Sakash.bagdia@arm.com self.nvram.port = self.membus.master 1949827Sakash.bagdia@arm.com self.hypervisor_desc.port = self.membus.master 1959827Sakash.bagdia@arm.com self.partition_desc.port = self.membus.master 1969793Sakash.bagdia@arm.com self.intrctrl = IntrControl() 1979827Sakash.bagdia@arm.com self.disk0 = CowMmDisk() 1989827Sakash.bagdia@arm.com self.disk0.childImage(disk('disk.s10hw2')) 1999827Sakash.bagdia@arm.com self.disk0.pio = self.iobus.master 2009793Sakash.bagdia@arm.com 20111251Sradhika.jagtap@ARM.com # The puart0 and hvuart are placed on the IO bus, so create ranges 20211251Sradhika.jagtap@ARM.com # for them. The remaining IO range is rather fragmented, so poke 20311251Sradhika.jagtap@ARM.com # holes for the iob and partition descriptors etc. 20411251Sradhika.jagtap@ARM.com self.bridge.ranges = \ 20511251Sradhika.jagtap@ARM.com [ 2069793Sakash.bagdia@arm.com AddrRange(self.t1000.puart0.pio_addr, 2079793Sakash.bagdia@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 2089793Sakash.bagdia@arm.com AddrRange(self.disk0.pio_addr, 2099793Sakash.bagdia@arm.com self.t1000.fake_jbi.pio_addr + 2103395Shsul@eecs.umich.edu self.t1000.fake_jbi.pio_size - 1), 21110555Salexandru.dutu@amd.com AddrRange(self.t1000.fake_clk.pio_addr, 21210555Salexandru.dutu@amd.com iob_man_addr - 1), 21310555Salexandru.dutu@amd.com AddrRange(self.t1000.fake_l2_1.pio_addr, 21410555Salexandru.dutu@amd.com self.t1000.fake_ssi.pio_addr + 21510555Salexandru.dutu@amd.com self.t1000.fake_ssi.pio_size - 1), 21610555Salexandru.dutu@amd.com AddrRange(self.t1000.hvuart.pio_addr, 21710555Salexandru.dutu@amd.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 21810555Salexandru.dutu@amd.com ] 21910555Salexandru.dutu@amd.com self.reset_bin = binary('reset_new.bin') 2208926Sandreas.hansson@arm.com self.hypervisor_bin = binary('q_new.bin') 2219317Sandreas.hansson@arm.com self.openboot_bin = binary('openboot_new.bin') 2229317Sandreas.hansson@arm.com self.nvram_bin = binary('nvram1') 2239317Sandreas.hansson@arm.com self.hypervisor_desc_bin = binary('1up-hv.bin') 2249317Sandreas.hansson@arm.com self.partition_desc_bin = binary('1up-md.bin') 2259317Sandreas.hansson@arm.com 2268926Sandreas.hansson@arm.com self.system_port = self.membus.slave 2279647Sdam.sunwoo@arm.com 2289647Sdam.sunwoo@arm.com return self 2299647Sdam.sunwoo@arm.com 2309647Sdam.sunwoo@arm.comdef makeArmSystem(mem_mode, machine_type, mdesc = None, dtb_filename = None, 2319647Sdam.sunwoo@arm.com bare_metal=False): 2329647Sdam.sunwoo@arm.com assert machine_type 2339647Sdam.sunwoo@arm.com 2343395Shsul@eecs.umich.edu if bare_metal: 2359197Snilay@cs.wisc.edu self = ArmSystem() 2369197Snilay@cs.wisc.edu else: 2379197Snilay@cs.wisc.edu self = LinuxArmSystem() 2388957Sjayneel@cs.wisc.edu 2398957Sjayneel@cs.wisc.edu if not mdesc: 2408957Sjayneel@cs.wisc.edu # generic system 2413005Sstever@eecs.umich.edu mdesc = SysConfig() 2424968Sacolyte@umich.edu 2439006Sandreas.hansson@arm.com self.readfile = mdesc.script() 2444968Sacolyte@umich.edu self.iobus = NoncoherentBus() 2459647Sdam.sunwoo@arm.com self.membus = MemBus() 24610381Sdam.sunwoo@arm.com self.membus.badaddr_responder.warn_access = "warn" 2479647Sdam.sunwoo@arm.com self.bridge = Bridge(delay='50ns') 2488887Sgeoffrey.blake@arm.com self.bridge.master = self.iobus.slave 2498887Sgeoffrey.blake@arm.com self.bridge.slave = self.membus.master 2508887Sgeoffrey.blake@arm.com 2519384SAndreas.Sandberg@arm.com self.mem_mode = mem_mode 2529384SAndreas.Sandberg@arm.com 2538887Sgeoffrey.blake@arm.com if machine_type == "RealView_PBX": 25411088Snilay@cs.wisc.edu self.realview = RealViewPBX() 25511088Snilay@cs.wisc.edu elif machine_type == "RealView_EB": 2568896Snilay@cs.wisc.edu self.realview = RealViewEB() 2578896Snilay@cs.wisc.edu elif machine_type == "VExpress_ELT": 25810519Snilay@cs.wisc.edu self.realview = VExpress_ELT() 25910120Snilay@cs.wisc.edu elif machine_type == "VExpress_EMM": 2608896Snilay@cs.wisc.edu self.realview = VExpress_EMM() 26110300Scastilloe@unican.es self.load_addr_mask = 0xffffffff 26210300Scastilloe@unican.es else: 2638896Snilay@cs.wisc.edu print "Unknown Machine Type" 26410120Snilay@cs.wisc.edu sys.exit(1) 2658896Snilay@cs.wisc.edu 2668896Snilay@cs.wisc.edu self.cf0 = CowIdeDisk(driveID='master') 2679268Smalek.musleh@gmail.com self.cf0.childImage(mdesc.disk()) 2689268Smalek.musleh@gmail.com # default to an IDE controller rather than a CF one 2698896Snilay@cs.wisc.edu # assuming we've got one 2708896Snilay@cs.wisc.edu try: 2718896Snilay@cs.wisc.edu self.realview.ide.disks = [self.cf0] 2728896Snilay@cs.wisc.edu except: 2738896Snilay@cs.wisc.edu self.realview.cf_ctrl.disks = [self.cf0] 2749222Shestness@cs.wisc.edu 27511150Smitch.hayenga@arm.com if bare_metal: 27611150Smitch.hayenga@arm.com # EOT character on UART will end the simulation 27711150Smitch.hayenga@arm.com self.realview.uart.end_on_eot = True 2789222Shestness@cs.wisc.edu self.physmem = SimpleDDR3(range = AddrRange(Addr(mdesc.mem())), 2799222Shestness@cs.wisc.edu zero = True) 2808887Sgeoffrey.blake@arm.com self.mem_ranges = [self.physmem.range] 28110150Snilay@cs.wisc.edu else: 28210720Sandreas.hansson@arm.com self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 2838887Sgeoffrey.blake@arm.com if dtb_filename is not None: 2848887Sgeoffrey.blake@arm.com self.dtb_filename = dtb_filename 2859836Sandreas.hansson@arm.com self.machine_type = machine_type 2868887Sgeoffrey.blake@arm.com if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 2878801Sgblack@eecs.umich.edu print "The currently selected ARM platforms doesn't support" 2883481Shsul@eecs.umich.edu print " the amount of DRAM you've selected. Please try" 289 print " another platform" 290 sys.exit(1) 291 292 boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 293 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 294 295 self.physmem = SimpleDDR3(range = 296 AddrRange(self.realview.mem_start_addr, 297 size = mdesc.mem()), 298 conf_table_reported = True) 299 self.mem_ranges = [self.physmem.range] 300 self.realview.setupBootLoader(self.membus, self, binary) 301 self.gic_cpu_addr = self.realview.gic.cpu_addr 302 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 303 304 if mdesc.disk().lower().count('android'): 305 boot_flags += " init=/init " 306 self.boot_osflags = boot_flags 307 308 self.physmem.port = self.membus.master 309 self.realview.attachOnChipIO(self.membus, self.bridge) 310 self.realview.attachIO(self.iobus) 311 self.intrctrl = IntrControl() 312 self.terminal = Terminal() 313 self.vncserver = VncServer() 314 315 self.system_port = self.membus.slave 316 317 return self 318 319 320def makeLinuxMipsSystem(mem_mode, mdesc = None): 321 class BaseMalta(Malta): 322 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 323 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 324 pci_func=0, pci_dev=0, pci_bus=0) 325 326 self = LinuxMipsSystem() 327 if not mdesc: 328 # generic system 329 mdesc = SysConfig() 330 self.readfile = mdesc.script() 331 self.iobus = NoncoherentBus() 332 self.membus = MemBus() 333 self.bridge = Bridge(delay='50ns') 334 self.physmem = SimpleDDR3(range = AddrRange('1GB')) 335 self.mem_ranges = [self.physmem.range] 336 self.bridge.master = self.iobus.slave 337 self.bridge.slave = self.membus.master 338 self.physmem.port = self.membus.master 339 self.disk0 = CowIdeDisk(driveID='master') 340 self.disk2 = CowIdeDisk(driveID='master') 341 self.disk0.childImage(mdesc.disk()) 342 self.disk2.childImage(disk('linux-bigswap2.img')) 343 self.malta = BaseMalta() 344 self.malta.attachIO(self.iobus) 345 self.malta.ide.pio = self.iobus.master 346 self.malta.ide.config = self.iobus.master 347 self.malta.ide.dma = self.iobus.slave 348 self.malta.ethernet.pio = self.iobus.master 349 self.malta.ethernet.config = self.iobus.master 350 self.malta.ethernet.dma = self.iobus.slave 351 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 352 read_only = True)) 353 self.intrctrl = IntrControl() 354 self.mem_mode = mem_mode 355 self.terminal = Terminal() 356 self.kernel = binary('mips/vmlinux') 357 self.console = binary('mips/console') 358 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 359 360 self.system_port = self.membus.slave 361 362 return self 363 364def x86IOAddress(port): 365 IO_address_space_base = 0x8000000000000000 366 return IO_address_space_base + port 367 368def connectX86ClassicSystem(x86_sys, numCPUs): 369 # Constants similar to x86_traits.hh 370 IO_address_space_base = 0x8000000000000000 371 pci_config_address_space_base = 0xc000000000000000 372 interrupts_address_space_base = 0xa000000000000000 373 APIC_range_size = 1 << 12; 374 375 x86_sys.membus = MemBus() 376 x86_sys.physmem.port = x86_sys.membus.master 377 378 # North Bridge 379 x86_sys.iobus = NoncoherentBus() 380 x86_sys.bridge = Bridge(delay='50ns') 381 x86_sys.bridge.master = x86_sys.iobus.slave 382 x86_sys.bridge.slave = x86_sys.membus.master 383 # Allow the bridge to pass through the IO APIC (two pages), 384 # everything in the IO address range up to the local APIC, and 385 # then the entire PCI address space and beyond 386 x86_sys.bridge.ranges = \ 387 [ 388 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 389 x86_sys.pc.south_bridge.io_apic.pio_addr + 390 APIC_range_size - 1), 391 AddrRange(IO_address_space_base, 392 interrupts_address_space_base - 1), 393 AddrRange(pci_config_address_space_base, 394 Addr.max) 395 ] 396 397 # Create a bridge from the IO bus to the memory bus to allow access to 398 # the local APIC (two pages) 399 x86_sys.apicbridge = Bridge(delay='50ns') 400 x86_sys.apicbridge.slave = x86_sys.iobus.master 401 x86_sys.apicbridge.master = x86_sys.membus.slave 402 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 403 interrupts_address_space_base + 404 numCPUs * APIC_range_size 405 - 1)] 406 407 # connect the io bus 408 x86_sys.pc.attachIO(x86_sys.iobus) 409 410 x86_sys.system_port = x86_sys.membus.slave 411 412def connectX86RubySystem(x86_sys): 413 # North Bridge 414 x86_sys.piobus = NoncoherentBus() 415 416 # 417 # Pio functional accesses from devices need direct access to memory 418 # RubyPort currently does support functional accesses. Therefore provide 419 # the piobus a direct connection to physical memory 420 # 421 x86_sys.piobus.master = x86_sys.physmem.port 422 # add the ide to the list of dma devices that later need to attach to 423 # dma controllers 424 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 425 x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports) 426 427 428def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 429 if self == None: 430 self = X86System() 431 432 if not mdesc: 433 # generic system 434 mdesc = SysConfig() 435 self.readfile = mdesc.script() 436 437 self.mem_mode = mem_mode 438 439 # Physical memory 440 self.physmem = SimpleDDR3(range = AddrRange(mdesc.mem())) 441 self.mem_ranges = [self.physmem.range] 442 443 # Platform 444 self.pc = Pc() 445 446 # Create and connect the busses required by each memory system 447 if Ruby: 448 connectX86RubySystem(self) 449 else: 450 connectX86ClassicSystem(self, numCPUs) 451 452 self.intrctrl = IntrControl() 453 454 # Disks 455 disk0 = CowIdeDisk(driveID='master') 456 disk2 = CowIdeDisk(driveID='master') 457 disk0.childImage(mdesc.disk()) 458 disk2.childImage(disk('linux-bigswap2.img')) 459 self.pc.south_bridge.ide.disks = [disk0, disk2] 460 461 # Add in a Bios information structure. 462 structures = [X86SMBiosBiosInformation()] 463 self.smbios_table.structures = structures 464 465 # Set up the Intel MP table 466 base_entries = [] 467 ext_entries = [] 468 for i in xrange(numCPUs): 469 bp = X86IntelMPProcessor( 470 local_apic_id = i, 471 local_apic_version = 0x14, 472 enable = True, 473 bootstrap = (i == 0)) 474 base_entries.append(bp) 475 io_apic = X86IntelMPIOAPIC( 476 id = numCPUs, 477 version = 0x11, 478 enable = True, 479 address = 0xfec00000) 480 self.pc.south_bridge.io_apic.apic_id = io_apic.id 481 base_entries.append(io_apic) 482 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 483 base_entries.append(isa_bus) 484 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 485 base_entries.append(pci_bus) 486 connect_busses = X86IntelMPBusHierarchy(bus_id=0, 487 subtractive_decode=True, parent_bus=1) 488 ext_entries.append(connect_busses) 489 pci_dev4_inta = X86IntelMPIOIntAssignment( 490 interrupt_type = 'INT', 491 polarity = 'ConformPolarity', 492 trigger = 'ConformTrigger', 493 source_bus_id = 1, 494 source_bus_irq = 0 + (4 << 2), 495 dest_io_apic_id = io_apic.id, 496 dest_io_apic_intin = 16) 497 base_entries.append(pci_dev4_inta) 498 def assignISAInt(irq, apicPin): 499 assign_8259_to_apic = X86IntelMPIOIntAssignment( 500 interrupt_type = 'ExtInt', 501 polarity = 'ConformPolarity', 502 trigger = 'ConformTrigger', 503 source_bus_id = 0, 504 source_bus_irq = irq, 505 dest_io_apic_id = io_apic.id, 506 dest_io_apic_intin = 0) 507 base_entries.append(assign_8259_to_apic) 508 assign_to_apic = X86IntelMPIOIntAssignment( 509 interrupt_type = 'INT', 510 polarity = 'ConformPolarity', 511 trigger = 'ConformTrigger', 512 source_bus_id = 0, 513 source_bus_irq = irq, 514 dest_io_apic_id = io_apic.id, 515 dest_io_apic_intin = apicPin) 516 base_entries.append(assign_to_apic) 517 assignISAInt(0, 2) 518 assignISAInt(1, 1) 519 for i in range(3, 15): 520 assignISAInt(i, i) 521 self.intel_mp_table.base_entries = base_entries 522 self.intel_mp_table.ext_entries = ext_entries 523 524def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 525 self = LinuxX86System() 526 527 # Build up the x86 system and then specialize it for Linux 528 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 529 530 # We assume below that there's at least 1MB of memory. We'll require 2 531 # just to avoid corner cases. 532 phys_mem_size = sum(map(lambda mem: mem.range.size(), 533 self.memories.unproxy(self))) 534 assert(phys_mem_size >= 0x200000) 535 536 self.e820_table.entries = \ 537 [ 538 # Mark the first megabyte of memory as reserved 539 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 540 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 541 # Mark the rest as available 542 X86E820Entry(addr = 0x100000, 543 size = '%dB' % (phys_mem_size - 0x100000), 544 range_type = 1) 545 ] 546 547 # Command line 548 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 549 'root=/dev/hda1' 550 return self 551 552 553def makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 554 self = Root(full_system = full_system) 555 self.testsys = testSystem 556 self.drivesys = driveSystem 557 self.etherlink = EtherLink() 558 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 559 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 560 561 if hasattr(testSystem, 'realview'): 562 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 563 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 564 elif hasattr(testSystem, 'tsunami'): 565 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 566 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 567 else: 568 fatal("Don't know how to connect these system together") 569 570 if dumpfile: 571 self.etherdump = EtherDump(file=dumpfile) 572 self.etherlink.dump = Parent.etherdump 573 574 return self 575