FSConfig.py revision 9408 
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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9# terms below provided that you ensure that this notice is replicated
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11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
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18# modification, are permitted provided that the following conditions are
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28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import convert
45
46class CowIdeDisk(IdeDisk):
47    image = CowDiskImage(child=RawDiskImage(read_only=True),
48                         read_only=False)
49
50    def childImage(self, ci):
51        self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54    badaddr_responder = BadAddr()
55    default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59    IO_address_space_base = 0x80000000000
60    class BaseTsunami(Tsunami):
61        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63                            pci_func=0, pci_dev=0, pci_bus=0)
64
65    self = LinuxAlphaSystem()
66    if not mdesc:
67        # generic system
68        mdesc = SysConfig()
69    self.readfile = mdesc.script()
70    self.iobus = NoncoherentBus()
71    self.membus = MemBus()
72    # By default the bridge responds to all addresses above the I/O
73    # base address (including the PCI config space)
74    self.bridge = Bridge(delay='50ns',
75                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
76    self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
77    self.mem_ranges = [self.physmem.range]
78    self.bridge.master = self.iobus.slave
79    self.bridge.slave = self.membus.master
80    self.physmem.port = self.membus.master
81    self.disk0 = CowIdeDisk(driveID='master')
82    self.disk2 = CowIdeDisk(driveID='master')
83    self.disk0.childImage(mdesc.disk())
84    self.disk2.childImage(disk('linux-bigswap2.img'))
85    self.tsunami = BaseTsunami()
86    self.tsunami.attachIO(self.iobus)
87    self.tsunami.ide.pio = self.iobus.master
88    self.tsunami.ide.config = self.iobus.master
89    self.tsunami.ide.dma = self.iobus.slave
90    self.tsunami.ethernet.pio = self.iobus.master
91    self.tsunami.ethernet.config = self.iobus.master
92    self.tsunami.ethernet.dma = self.iobus.slave
93    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
94                                               read_only = True))
95    self.intrctrl = IntrControl()
96    self.mem_mode = mem_mode
97    self.terminal = Terminal()
98    self.kernel = binary('vmlinux')
99    self.pal = binary('ts_osfpal')
100    self.console = binary('console')
101    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
102
103    self.system_port = self.membus.slave
104
105    return self
106
107def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
108    class BaseTsunami(Tsunami):
109        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
110        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
111                            pci_func=0, pci_dev=0, pci_bus=0)
112
113    physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
114    self = LinuxAlphaSystem(physmem = physmem)
115    self.mem_ranges = [self.physmem.range]
116    if not mdesc:
117        # generic system
118        mdesc = SysConfig()
119    self.readfile = mdesc.script()
120
121    # Create pio bus to connect all device pio ports to rubymem's pio port
122    self.piobus = NoncoherentBus()
123
124    #
125    # Pio functional accesses from devices need direct access to memory
126    # RubyPort currently does support functional accesses.  Therefore provide
127    # the piobus a direct connection to physical memory
128    #
129    self.piobus.master = physmem.port
130
131    self.disk0 = CowIdeDisk(driveID='master')
132    self.disk2 = CowIdeDisk(driveID='master')
133    self.disk0.childImage(mdesc.disk())
134    self.disk2.childImage(disk('linux-bigswap2.img'))
135    self.tsunami = BaseTsunami()
136    self.tsunami.attachIO(self.piobus)
137    self.tsunami.ide.pio = self.piobus.master
138    self.tsunami.ide.config = self.piobus.master
139    self.tsunami.ethernet.pio = self.piobus.master
140    self.tsunami.ethernet.config = self.piobus.master
141
142    #
143    # Store the dma devices for later connection to dma ruby ports.
144    # Append an underscore to dma_devices to avoid the SimObjectVector check.
145    #
146    self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
147
148    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
149                                               read_only = True))
150    self.intrctrl = IntrControl()
151    self.mem_mode = mem_mode
152    self.terminal = Terminal()
153    self.kernel = binary('vmlinux')
154    self.pal = binary('ts_osfpal')
155    self.console = binary('console')
156    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
157
158    return self
159
160def makeSparcSystem(mem_mode, mdesc = None):
161    # Constants from iob.cc and uart8250.cc
162    iob_man_addr = 0x9800000000
163    uart_pio_size = 8
164
165    class CowMmDisk(MmDisk):
166        image = CowDiskImage(child=RawDiskImage(read_only=True),
167                             read_only=False)
168
169        def childImage(self, ci):
170            self.image.child.image_file = ci
171
172    self = SparcSystem()
173    if not mdesc:
174        # generic system
175        mdesc = SysConfig()
176    self.readfile = mdesc.script()
177    self.iobus = NoncoherentBus()
178    self.membus = MemBus()
179    self.bridge = Bridge(delay='50ns')
180    self.t1000 = T1000()
181    self.t1000.attachOnChipIO(self.membus)
182    self.t1000.attachIO(self.iobus)
183    self.physmem = SimpleDRAM(range = AddrRange(Addr('1MB'), size = '64MB'),
184                                zero = True)
185    self.physmem2 = SimpleDRAM(range = AddrRange(Addr('2GB'), size ='256MB'),
186                                 zero = True)
187    self.mem_ranges = [self.physmem.range, self.physmem2.range]
188    self.bridge.master = self.iobus.slave
189    self.bridge.slave = self.membus.master
190    self.physmem.port = self.membus.master
191    self.physmem2.port = self.membus.master
192    self.rom.port = self.membus.master
193    self.nvram.port = self.membus.master
194    self.hypervisor_desc.port = self.membus.master
195    self.partition_desc.port = self.membus.master
196    self.intrctrl = IntrControl()
197    self.disk0 = CowMmDisk()
198    self.disk0.childImage(disk('disk.s10hw2'))
199    self.disk0.pio = self.iobus.master
200
201    # The puart0 and hvuart are placed on the IO bus, so create ranges
202    # for them. The remaining IO range is rather fragmented, so poke
203    # holes for the iob and partition descriptors etc.
204    self.bridge.ranges = \
205        [
206        AddrRange(self.t1000.puart0.pio_addr,
207                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
208        AddrRange(self.disk0.pio_addr,
209                  self.t1000.fake_jbi.pio_addr +
210                  self.t1000.fake_jbi.pio_size - 1),
211        AddrRange(self.t1000.fake_clk.pio_addr,
212                  iob_man_addr - 1),
213        AddrRange(self.t1000.fake_l2_1.pio_addr,
214                  self.t1000.fake_ssi.pio_addr +
215                  self.t1000.fake_ssi.pio_size - 1),
216        AddrRange(self.t1000.hvuart.pio_addr,
217                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
218        ]
219    self.reset_bin = binary('reset_new.bin')
220    self.hypervisor_bin = binary('q_new.bin')
221    self.openboot_bin = binary('openboot_new.bin')
222    self.nvram_bin = binary('nvram1')
223    self.hypervisor_desc_bin = binary('1up-hv.bin')
224    self.partition_desc_bin = binary('1up-md.bin')
225
226    self.system_port = self.membus.slave
227
228    return self
229
230def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
231    assert machine_type
232
233    if bare_metal:
234        self = ArmSystem()
235    else:
236        self = LinuxArmSystem()
237
238    if not mdesc:
239        # generic system
240        mdesc = SysConfig()
241
242    self.readfile = mdesc.script()
243    self.iobus = NoncoherentBus()
244    self.membus = MemBus()
245    self.membus.badaddr_responder.warn_access = "warn"
246    self.bridge = Bridge(delay='50ns')
247    self.bridge.master = self.iobus.slave
248    self.bridge.slave = self.membus.master
249
250    self.mem_mode = mem_mode
251
252    if machine_type == "RealView_PBX":
253        self.realview = RealViewPBX()
254    elif machine_type == "RealView_EB":
255        self.realview = RealViewEB()
256    elif machine_type == "VExpress_ELT":
257        self.realview = VExpress_ELT()
258    elif machine_type == "VExpress_EMM":
259        self.realview = VExpress_EMM()
260        self.load_addr_mask = 0xffffffff
261    else:
262        print "Unknown Machine Type"
263        sys.exit(1)
264
265    self.cf0 = CowIdeDisk(driveID='master')
266    self.cf0.childImage(mdesc.disk())
267    # default to an IDE controller rather than a CF one
268    # assuming we've got one
269    try:
270        self.realview.ide.disks = [self.cf0]
271    except:
272        self.realview.cf_ctrl.disks = [self.cf0]
273
274    if bare_metal:
275        # EOT character on UART will end the simulation
276        self.realview.uart.end_on_eot = True
277        self.physmem = SimpleDRAM(range = AddrRange(Addr(mdesc.mem())),
278                                    zero = True)
279        self.mem_ranges = [self.physmem.range]
280    else:
281        self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
282        self.machine_type = machine_type
283        if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
284            print "The currently selected ARM platforms doesn't support"
285            print " the amount of DRAM you've selected. Please try"
286            print " another platform"
287            sys.exit(1)
288
289        boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
290                     'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
291
292        self.physmem = SimpleDRAM(range =
293                                    AddrRange(self.realview.mem_start_addr,
294                                              size = mdesc.mem()),
295                                    conf_table_reported = True)
296        self.mem_ranges = [self.physmem.range]
297        self.realview.setupBootLoader(self.membus, self, binary)
298        self.gic_cpu_addr = self.realview.gic.cpu_addr
299        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
300
301        if mdesc.disk().lower().count('android'):
302            boot_flags += " init=/init "
303        self.boot_osflags = boot_flags
304
305    self.physmem.port = self.membus.master
306    self.realview.attachOnChipIO(self.membus, self.bridge)
307    self.realview.attachIO(self.iobus)
308    self.intrctrl = IntrControl()
309    self.terminal = Terminal()
310    self.vncserver = VncServer()
311
312    self.system_port = self.membus.slave
313
314    return self
315
316
317def makeLinuxMipsSystem(mem_mode, mdesc = None):
318    class BaseMalta(Malta):
319        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
320        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
321                            pci_func=0, pci_dev=0, pci_bus=0)
322
323    self = LinuxMipsSystem()
324    if not mdesc:
325        # generic system
326        mdesc = SysConfig()
327    self.readfile = mdesc.script()
328    self.iobus = NoncoherentBus()
329    self.membus = MemBus()
330    self.bridge = Bridge(delay='50ns')
331    self.physmem = SimpleDRAM(range = AddrRange('1GB'))
332    self.mem_ranges = [self.physmem.range]
333    self.bridge.master = self.iobus.slave
334    self.bridge.slave = self.membus.master
335    self.physmem.port = self.membus.master
336    self.disk0 = CowIdeDisk(driveID='master')
337    self.disk2 = CowIdeDisk(driveID='master')
338    self.disk0.childImage(mdesc.disk())
339    self.disk2.childImage(disk('linux-bigswap2.img'))
340    self.malta = BaseMalta()
341    self.malta.attachIO(self.iobus)
342    self.malta.ide.pio = self.iobus.master
343    self.malta.ide.config = self.iobus.master
344    self.malta.ide.dma = self.iobus.slave
345    self.malta.ethernet.pio = self.iobus.master
346    self.malta.ethernet.config = self.iobus.master
347    self.malta.ethernet.dma = self.iobus.slave
348    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
349                                               read_only = True))
350    self.intrctrl = IntrControl()
351    self.mem_mode = mem_mode
352    self.terminal = Terminal()
353    self.kernel = binary('mips/vmlinux')
354    self.console = binary('mips/console')
355    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
356
357    self.system_port = self.membus.slave
358
359    return self
360
361def x86IOAddress(port):
362    IO_address_space_base = 0x8000000000000000
363    return IO_address_space_base + port
364
365def connectX86ClassicSystem(x86_sys, numCPUs):
366    # Constants similar to x86_traits.hh
367    IO_address_space_base = 0x8000000000000000
368    pci_config_address_space_base = 0xc000000000000000
369    interrupts_address_space_base = 0xa000000000000000
370    APIC_range_size = 1 << 12;
371
372    x86_sys.membus = MemBus()
373    x86_sys.physmem.port = x86_sys.membus.master
374
375    # North Bridge
376    x86_sys.iobus = NoncoherentBus()
377    x86_sys.bridge = Bridge(delay='50ns')
378    x86_sys.bridge.master = x86_sys.iobus.slave
379    x86_sys.bridge.slave = x86_sys.membus.master
380    # Allow the bridge to pass through the IO APIC (two pages),
381    # everything in the IO address range up to the local APIC, and
382    # then the entire PCI address space and beyond
383    x86_sys.bridge.ranges = \
384        [
385        AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
386                  x86_sys.pc.south_bridge.io_apic.pio_addr +
387                  APIC_range_size - 1),
388        AddrRange(IO_address_space_base,
389                  interrupts_address_space_base - 1),
390        AddrRange(pci_config_address_space_base,
391                  Addr.max)
392        ]
393
394    # Create a bridge from the IO bus to the memory bus to allow access to
395    # the local APIC (two pages)
396    x86_sys.apicbridge = Bridge(delay='50ns')
397    x86_sys.apicbridge.slave = x86_sys.iobus.master
398    x86_sys.apicbridge.master = x86_sys.membus.slave
399    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
400                                           interrupts_address_space_base +
401                                           numCPUs * APIC_range_size
402                                           - 1)]
403
404    # connect the io bus
405    x86_sys.pc.attachIO(x86_sys.iobus)
406
407    x86_sys.system_port = x86_sys.membus.slave
408
409def connectX86RubySystem(x86_sys):
410    # North Bridge
411    x86_sys.piobus = NoncoherentBus()
412
413    #
414    # Pio functional accesses from devices need direct access to memory
415    # RubyPort currently does support functional accesses.  Therefore provide
416    # the piobus a direct connection to physical memory
417    #
418    x86_sys.piobus.master = x86_sys.physmem.port
419    # add the ide to the list of dma devices that later need to attach to
420    # dma controllers
421    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
422    x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
423
424
425def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
426    if self == None:
427        self = X86System()
428
429    if not mdesc:
430        # generic system
431        mdesc = SysConfig()
432    self.readfile = mdesc.script()
433
434    self.mem_mode = mem_mode
435
436    # Physical memory
437    self.physmem = SimpleDRAM(range = AddrRange(mdesc.mem()))
438    self.mem_ranges = [self.physmem.range]
439
440    # Platform
441    self.pc = Pc()
442
443    # Create and connect the busses required by each memory system
444    if Ruby:
445        connectX86RubySystem(self)
446    else:
447        connectX86ClassicSystem(self, numCPUs)
448
449    self.intrctrl = IntrControl()
450
451    # Disks
452    disk0 = CowIdeDisk(driveID='master')
453    disk2 = CowIdeDisk(driveID='master')
454    disk0.childImage(mdesc.disk())
455    disk2.childImage(disk('linux-bigswap2.img'))
456    self.pc.south_bridge.ide.disks = [disk0, disk2]
457
458    # Add in a Bios information structure.
459    structures = [X86SMBiosBiosInformation()]
460    self.smbios_table.structures = structures
461
462    # Set up the Intel MP table
463    base_entries = []
464    ext_entries = []
465    for i in xrange(numCPUs):
466        bp = X86IntelMPProcessor(
467                local_apic_id = i,
468                local_apic_version = 0x14,
469                enable = True,
470                bootstrap = (i == 0))
471        base_entries.append(bp)
472    io_apic = X86IntelMPIOAPIC(
473            id = numCPUs,
474            version = 0x11,
475            enable = True,
476            address = 0xfec00000)
477    self.pc.south_bridge.io_apic.apic_id = io_apic.id
478    base_entries.append(io_apic)
479    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
480    base_entries.append(isa_bus)
481    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
482    base_entries.append(pci_bus)
483    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
484            subtractive_decode=True, parent_bus=1)
485    ext_entries.append(connect_busses)
486    pci_dev4_inta = X86IntelMPIOIntAssignment(
487            interrupt_type = 'INT',
488            polarity = 'ConformPolarity',
489            trigger = 'ConformTrigger',
490            source_bus_id = 1,
491            source_bus_irq = 0 + (4 << 2),
492            dest_io_apic_id = io_apic.id,
493            dest_io_apic_intin = 16)
494    base_entries.append(pci_dev4_inta)
495    def assignISAInt(irq, apicPin):
496        assign_8259_to_apic = X86IntelMPIOIntAssignment(
497                interrupt_type = 'ExtInt',
498                polarity = 'ConformPolarity',
499                trigger = 'ConformTrigger',
500                source_bus_id = 0,
501                source_bus_irq = irq,
502                dest_io_apic_id = io_apic.id,
503                dest_io_apic_intin = 0)
504        base_entries.append(assign_8259_to_apic)
505        assign_to_apic = X86IntelMPIOIntAssignment(
506                interrupt_type = 'INT',
507                polarity = 'ConformPolarity',
508                trigger = 'ConformTrigger',
509                source_bus_id = 0,
510                source_bus_irq = irq,
511                dest_io_apic_id = io_apic.id,
512                dest_io_apic_intin = apicPin)
513        base_entries.append(assign_to_apic)
514    assignISAInt(0, 2)
515    assignISAInt(1, 1)
516    for i in range(3, 15):
517        assignISAInt(i, i)
518    self.intel_mp_table.base_entries = base_entries
519    self.intel_mp_table.ext_entries = ext_entries
520
521def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
522    self = LinuxX86System()
523
524    # Build up the x86 system and then specialize it for Linux
525    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
526
527    # We assume below that there's at least 1MB of memory. We'll require 2
528    # just to avoid corner cases.
529    phys_mem_size = sum(map(lambda mem: mem.range.size(),
530                            self.memories.unproxy(self)))
531    assert(phys_mem_size >= 0x200000)
532
533    self.e820_table.entries = \
534       [
535        # Mark the first megabyte of memory as reserved
536        X86E820Entry(addr = 0, size = '1MB', range_type = 2),
537        # Mark the rest as available
538        X86E820Entry(addr = 0x100000,
539                size = '%dB' % (phys_mem_size - 0x100000),
540                range_type = 1)
541        ]
542
543    # Command line
544    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
545                        'root=/dev/hda1'
546    return self
547
548
549def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
550    self = Root(full_system = full_system)
551    self.testsys = testSystem
552    self.drivesys = driveSystem
553    self.etherlink = EtherLink()
554    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
555    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
556
557    if hasattr(testSystem, 'realview'):
558        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
559        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
560    elif hasattr(testSystem, 'tsunami'):
561        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
562        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
563    else:
564        fatal("Don't know how to connect these system together")
565
566    if dumpfile:
567        self.etherdump = EtherDump(file=dumpfile)
568        self.etherlink.dump = Parent.etherdump
569
570    return self
571