FSConfig.py revision 8713:2f1a3e335255 
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
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18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
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25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import convert
45
46class CowIdeDisk(IdeDisk):
47    image = CowDiskImage(child=RawDiskImage(read_only=True),
48                         read_only=False)
49
50    def childImage(self, ci):
51        self.image.child.image_file = ci
52
53class MemBus(Bus):
54    badaddr_responder = BadAddr()
55    default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59    IO_address_space_base = 0x80000000000
60    class BaseTsunami(Tsunami):
61        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63                            pci_func=0, pci_dev=0, pci_bus=0)
64
65    self = LinuxAlphaSystem()
66    if not mdesc:
67        # generic system
68        mdesc = SysConfig()
69    self.readfile = mdesc.script()
70    self.iobus = Bus(bus_id=0)
71    self.membus = MemBus(bus_id=1)
72    # By default the bridge responds to all addresses above the I/O
73    # base address (including the PCI config space)
74    self.bridge = Bridge(delay='50ns', nack_delay='4ns',
75                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
76    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
77    self.bridge.master = self.iobus.port
78    self.bridge.slave = self.membus.port
79    self.physmem.port = self.membus.port
80    self.disk0 = CowIdeDisk(driveID='master')
81    self.disk2 = CowIdeDisk(driveID='master')
82    self.disk0.childImage(mdesc.disk())
83    self.disk2.childImage(disk('linux-bigswap2.img'))
84    self.tsunami = BaseTsunami()
85    self.tsunami.attachIO(self.iobus)
86    self.tsunami.ide.pio = self.iobus.port
87    self.tsunami.ethernet.pio = self.iobus.port
88    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
89                                               read_only = True))
90    self.intrctrl = IntrControl()
91    self.mem_mode = mem_mode
92    self.terminal = Terminal()
93    self.kernel = binary('vmlinux')
94    self.pal = binary('ts_osfpal')
95    self.console = binary('console')
96    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
97
98    self.system_port = self.membus.port
99
100    return self
101
102def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
103    class BaseTsunami(Tsunami):
104        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
105        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
106                            pci_func=0, pci_dev=0, pci_bus=0)
107
108    physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
109    self = LinuxAlphaSystem(physmem = physmem)
110    if not mdesc:
111        # generic system
112        mdesc = SysConfig()
113    self.readfile = mdesc.script()
114
115    # Create pio bus to connect all device pio ports to rubymem's pio port
116    self.piobus = Bus(bus_id=0)
117
118    #
119    # Pio functional accesses from devices need direct access to memory
120    # RubyPort currently does support functional accesses.  Therefore provide
121    # the piobus a direct connection to physical memory
122    #
123    self.piobus.port = physmem.port
124
125    self.disk0 = CowIdeDisk(driveID='master')
126    self.disk2 = CowIdeDisk(driveID='master')
127    self.disk0.childImage(mdesc.disk())
128    self.disk2.childImage(disk('linux-bigswap2.img'))
129    self.tsunami = BaseTsunami()
130    self.tsunami.attachIO(self.piobus)
131    self.tsunami.ide.pio = self.piobus.port
132    self.tsunami.ethernet.pio = self.piobus.port
133
134    #
135    # Store the dma devices for later connection to dma ruby ports.
136    # Append an underscore to dma_devices to avoid the SimObjectVector check.
137    #
138    self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
139
140    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
141                                               read_only = True))
142    self.intrctrl = IntrControl()
143    self.mem_mode = mem_mode
144    self.terminal = Terminal()
145    self.kernel = binary('vmlinux')
146    self.pal = binary('ts_osfpal')
147    self.console = binary('console')
148    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
149
150    return self
151
152def makeSparcSystem(mem_mode, mdesc = None):
153    # Constants from iob.cc and uart8250.cc
154    iob_man_addr = 0x9800000000
155    uart_pio_size = 8
156
157    class CowMmDisk(MmDisk):
158        image = CowDiskImage(child=RawDiskImage(read_only=True),
159                             read_only=False)
160
161        def childImage(self, ci):
162            self.image.child.image_file = ci
163
164    self = SparcSystem()
165    if not mdesc:
166        # generic system
167        mdesc = SysConfig()
168    self.readfile = mdesc.script()
169    self.iobus = Bus(bus_id=0)
170    self.membus = MemBus(bus_id=1)
171    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
172    self.t1000 = T1000()
173    self.t1000.attachOnChipIO(self.membus)
174    self.t1000.attachIO(self.iobus)
175    self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
176    self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
177    self.bridge.master = self.iobus.port
178    self.bridge.slave = self.membus.port
179    self.physmem.port = self.membus.port
180    self.physmem2.port = self.membus.port
181    self.rom.port = self.membus.port
182    self.nvram.port = self.membus.port
183    self.hypervisor_desc.port = self.membus.port
184    self.partition_desc.port = self.membus.port
185    self.intrctrl = IntrControl()
186    self.disk0 = CowMmDisk()
187    self.disk0.childImage(disk('disk.s10hw2'))
188    self.disk0.pio = self.iobus.port
189
190    # The puart0 and hvuart are placed on the IO bus, so create ranges
191    # for them. The remaining IO range is rather fragmented, so poke
192    # holes for the iob and partition descriptors etc.
193    self.bridge.ranges = \
194        [
195        AddrRange(self.t1000.puart0.pio_addr,
196                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
197        AddrRange(self.disk0.pio_addr,
198                  self.t1000.fake_jbi.pio_addr +
199                  self.t1000.fake_jbi.pio_size - 1),
200        AddrRange(self.t1000.fake_clk.pio_addr,
201                  iob_man_addr - 1),
202        AddrRange(self.t1000.fake_l2_1.pio_addr,
203                  self.t1000.fake_ssi.pio_addr +
204                  self.t1000.fake_ssi.pio_size - 1),
205        AddrRange(self.t1000.hvuart.pio_addr,
206                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
207        ]
208    self.reset_bin = binary('reset_new.bin')
209    self.hypervisor_bin = binary('q_new.bin')
210    self.openboot_bin = binary('openboot_new.bin')
211    self.nvram_bin = binary('nvram1')
212    self.hypervisor_desc_bin = binary('1up-hv.bin')
213    self.partition_desc_bin = binary('1up-md.bin')
214
215    self.system_port = self.membus.port
216
217    return self
218
219def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
220    assert machine_type
221
222    if bare_metal:
223        self = ArmSystem()
224    else:
225        self = LinuxArmSystem()
226
227    if not mdesc:
228        # generic system
229        mdesc = SysConfig()
230
231    self.readfile = mdesc.script()
232    self.iobus = Bus(bus_id=0)
233    self.membus = MemBus(bus_id=1)
234    self.membus.badaddr_responder.warn_access = "warn"
235    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
236    self.bridge.master = self.iobus.port
237    self.bridge.slave = self.membus.port
238
239    self.mem_mode = mem_mode
240
241    if machine_type == "RealView_PBX":
242        self.realview = RealViewPBX()
243    elif machine_type == "RealView_EB":
244        self.realview = RealViewEB()
245    elif machine_type == "VExpress_ELT":
246        self.realview = VExpress_ELT()
247    else:
248        print "Unknown Machine Type"
249        sys.exit(1)
250
251    self.cf0 = CowIdeDisk(driveID='master')
252    self.cf0.childImage(mdesc.disk())
253    # default to an IDE controller rather than a CF one
254    # assuming we've got one
255    try:
256        self.realview.ide.disks = [self.cf0]
257    except:
258        self.realview.cf_ctrl.disks = [self.cf0]
259
260    if bare_metal:
261        # EOT character on UART will end the simulation
262        self.realview.uart.end_on_eot = True
263        self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
264                                      zero = True)
265    else:
266        self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
267        self.machine_type = machine_type
268        if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'):
269            print "The currently implemented ARM platforms only easily support 256MB of DRAM"
270            print "It might be possible to get some more by using 256MB@0x30000000, but this"
271            print "is untested and may require some heroics"
272
273        boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
274                     'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
275
276        self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())),
277                                      zero = True)
278        self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
279                                    size = '64MB'), zero = True)
280        self.nvmem.port = self.membus.port
281        self.boot_loader = binary('boot.arm')
282        self.boot_loader_mem = self.nvmem
283        self.gic_cpu_addr = self.realview.gic.cpu_addr
284        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
285
286        if mdesc.disk().lower().count('android'):
287            boot_flags += " init=/init "
288        self.boot_osflags = boot_flags
289
290    self.physmem.port = self.membus.port
291    self.realview.attachOnChipIO(self.membus, self.bridge)
292    self.realview.attachIO(self.iobus)
293    self.intrctrl = IntrControl()
294    self.terminal = Terminal()
295    self.vncserver = VncServer()
296
297    self.system_port = self.membus.port
298
299    return self
300
301
302def makeLinuxMipsSystem(mem_mode, mdesc = None):
303    class BaseMalta(Malta):
304        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
305        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
306                            pci_func=0, pci_dev=0, pci_bus=0)
307
308    self = LinuxMipsSystem()
309    if not mdesc:
310        # generic system
311        mdesc = SysConfig()
312    self.readfile = mdesc.script()
313    self.iobus = Bus(bus_id=0)
314    self.membus = MemBus(bus_id=1)
315    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
316    self.physmem = PhysicalMemory(range = AddrRange('1GB'))
317    self.bridge.master = self.iobus.port
318    self.bridge.slave = self.membus.port
319    self.physmem.port = self.membus.port
320    self.disk0 = CowIdeDisk(driveID='master')
321    self.disk2 = CowIdeDisk(driveID='master')
322    self.disk0.childImage(mdesc.disk())
323    self.disk2.childImage(disk('linux-bigswap2.img'))
324    self.malta = BaseMalta()
325    self.malta.attachIO(self.iobus)
326    self.malta.ide.pio = self.iobus.port
327    self.malta.ethernet.pio = self.iobus.port
328    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
329                                               read_only = True))
330    self.intrctrl = IntrControl()
331    self.mem_mode = mem_mode
332    self.terminal = Terminal()
333    self.kernel = binary('mips/vmlinux')
334    self.console = binary('mips/console')
335    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
336
337    self.system_port = self.membus.port
338
339    return self
340
341def x86IOAddress(port):
342    IO_address_space_base = 0x8000000000000000
343    return IO_address_space_base + port
344
345def connectX86ClassicSystem(x86_sys):
346    # Constants similar to x86_traits.hh
347    IO_address_space_base = 0x8000000000000000
348    pci_config_address_space_base = 0xc000000000000000
349    interrupts_address_space_base = 0xa000000000000000
350    APIC_range_size = 1 << 12;
351
352    x86_sys.membus = MemBus(bus_id=1)
353    x86_sys.physmem.port = x86_sys.membus.port
354
355    # North Bridge
356    x86_sys.iobus = Bus(bus_id=0)
357    x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
358    x86_sys.bridge.master = x86_sys.iobus.port
359    x86_sys.bridge.slave = x86_sys.membus.port
360    # Allow the bridge to pass through the IO APIC (two pages),
361    # everything in the IO address range up to the local APIC, and
362    # then the entire PCI address space and beyond
363    x86_sys.bridge.ranges = \
364        [
365        AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
366                  x86_sys.pc.south_bridge.io_apic.pio_addr +
367                  APIC_range_size - 1),
368        AddrRange(IO_address_space_base,
369                  interrupts_address_space_base - 1),
370        AddrRange(pci_config_address_space_base,
371                  Addr.max)
372        ]
373
374    # Create a bridge from the IO bus to the memory bus to allow access to
375    # the local APIC (two pages)
376    x86_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns')
377    x86_sys.iobridge.slave = x86_sys.iobus.port
378    x86_sys.iobridge.master = x86_sys.membus.port
379    x86_sys.iobridge.ranges = [AddrRange(interrupts_address_space_base,
380                                         interrupts_address_space_base +
381                                         APIC_range_size - 1)]
382
383    # connect the io bus
384    x86_sys.pc.attachIO(x86_sys.iobus)
385
386    x86_sys.system_port = x86_sys.membus.port
387
388def connectX86RubySystem(x86_sys):
389    # North Bridge
390    x86_sys.piobus = Bus(bus_id=0)
391
392    #
393    # Pio functional accesses from devices need direct access to memory
394    # RubyPort currently does support functional accesses.  Therefore provide
395    # the piobus a direct connection to physical memory
396    #
397    x86_sys.piobus.port = x86_sys.physmem.port
398
399    x86_sys.pc.attachIO(x86_sys.piobus)
400
401
402def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
403    if self == None:
404        self = X86System()
405
406    if not mdesc:
407        # generic system
408        mdesc = SysConfig()
409    self.readfile = mdesc.script()
410
411    self.mem_mode = mem_mode
412
413    # Physical memory
414    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
415
416    # Platform
417    self.pc = Pc()
418
419    # Create and connect the busses required by each memory system
420    if Ruby:
421        connectX86RubySystem(self)
422        # add the ide to the list of dma devices that later need to attach to
423        # dma controllers
424        self._dma_devices = [self.pc.south_bridge.ide]
425    else:
426        connectX86ClassicSystem(self)
427
428    self.intrctrl = IntrControl()
429
430    # Disks
431    disk0 = CowIdeDisk(driveID='master')
432    disk2 = CowIdeDisk(driveID='master')
433    disk0.childImage(mdesc.disk())
434    disk2.childImage(disk('linux-bigswap2.img'))
435    self.pc.south_bridge.ide.disks = [disk0, disk2]
436
437    # Add in a Bios information structure.
438    structures = [X86SMBiosBiosInformation()]
439    self.smbios_table.structures = structures
440
441    # Set up the Intel MP table
442    base_entries = []
443    ext_entries = []
444    for i in xrange(numCPUs):
445        bp = X86IntelMPProcessor(
446                local_apic_id = i,
447                local_apic_version = 0x14,
448                enable = True,
449                bootstrap = (i == 0))
450        base_entries.append(bp)
451    io_apic = X86IntelMPIOAPIC(
452            id = numCPUs,
453            version = 0x11,
454            enable = True,
455            address = 0xfec00000)
456    self.pc.south_bridge.io_apic.apic_id = io_apic.id
457    base_entries.append(io_apic)
458    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
459    base_entries.append(isa_bus)
460    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
461    base_entries.append(pci_bus)
462    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
463            subtractive_decode=True, parent_bus=1)
464    ext_entries.append(connect_busses)
465    pci_dev4_inta = X86IntelMPIOIntAssignment(
466            interrupt_type = 'INT',
467            polarity = 'ConformPolarity',
468            trigger = 'ConformTrigger',
469            source_bus_id = 1,
470            source_bus_irq = 0 + (4 << 2),
471            dest_io_apic_id = io_apic.id,
472            dest_io_apic_intin = 16)
473    base_entries.append(pci_dev4_inta)
474    def assignISAInt(irq, apicPin):
475        assign_8259_to_apic = X86IntelMPIOIntAssignment(
476                interrupt_type = 'ExtInt',
477                polarity = 'ConformPolarity',
478                trigger = 'ConformTrigger',
479                source_bus_id = 0,
480                source_bus_irq = irq,
481                dest_io_apic_id = io_apic.id,
482                dest_io_apic_intin = 0)
483        base_entries.append(assign_8259_to_apic)
484        assign_to_apic = X86IntelMPIOIntAssignment(
485                interrupt_type = 'INT',
486                polarity = 'ConformPolarity',
487                trigger = 'ConformTrigger',
488                source_bus_id = 0,
489                source_bus_irq = irq,
490                dest_io_apic_id = io_apic.id,
491                dest_io_apic_intin = apicPin)
492        base_entries.append(assign_to_apic)
493    assignISAInt(0, 2)
494    assignISAInt(1, 1)
495    for i in range(3, 15):
496        assignISAInt(i, i)
497    self.intel_mp_table.base_entries = base_entries
498    self.intel_mp_table.ext_entries = ext_entries
499
500def setWorkCountOptions(system, options):
501    if options.work_item_id != None:
502        system.work_item_id = options.work_item_id
503    if options.work_begin_cpu_id_exit != None:
504        system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
505    if options.work_end_exit_count != None:
506        system.work_end_exit_count = options.work_end_exit_count
507    if options.work_end_checkpoint_count != None:
508        system.work_end_ckpt_count = options.work_end_checkpoint_count
509    if options.work_begin_exit_count != None:
510        system.work_begin_exit_count = options.work_begin_exit_count
511    if options.work_begin_checkpoint_count != None:
512        system.work_begin_ckpt_count = options.work_begin_checkpoint_count
513    if options.work_cpus_checkpoint_count != None:
514        system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
515
516
517def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
518    self = LinuxX86System()
519
520    # Build up the x86 system and then specialize it for Linux
521    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
522
523    # We assume below that there's at least 1MB of memory. We'll require 2
524    # just to avoid corner cases.
525    assert(self.physmem.range.second.getValue() >= 0x200000)
526
527    self.e820_table.entries = \
528       [
529        # Mark the first megabyte of memory as reserved
530        X86E820Entry(addr = 0, size = '1MB', range_type = 2),
531        # Mark the rest as available
532        X86E820Entry(addr = 0x100000,
533                size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
534                range_type = 1)
535        ]
536
537    # Command line
538    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
539                        'root=/dev/hda1'
540    return self
541
542
543def makeDualRoot(testSystem, driveSystem, dumpfile):
544    self = Root()
545    self.testsys = testSystem
546    self.drivesys = driveSystem
547    self.etherlink = EtherLink()
548    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
549    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
550
551    if hasattr(testSystem, 'realview'):
552        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
553        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
554    elif hasattr(testSystem, 'tsunami'):
555        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
556        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
557    else:
558        fatal("Don't know how to connect these system together")
559
560    if dumpfile:
561        self.etherdump = EtherDump(file=dumpfile)
562        self.etherlink.dump = Parent.etherdump
563
564    return self
565
566def setMipsOptions(TestCPUClass):
567        #CP0 Configuration
568        TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
569        TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
570        TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
571        TestCPUClass.CoreParams.CP0_PRId_Revision = 0
572
573        #CP0 Interrupt Control
574        TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
575        TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
576
577        # Config Register
578        #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
579        #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
580        TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
581        TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
582        TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
583        TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
584        #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
585
586        #Config 1 Register
587        TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
588        TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
589        # ***VERY IMPORTANT***
590        # Remember to modify CP0_Config1 according to cache specs
591        # Examine file ../common/Cache.py
592        TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
593        TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
594        TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
595        TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
596        TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
597        TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
598        TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
599        TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
600        TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
601        TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
602        TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
603        TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
604        TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
605
606        #Config 2 Register
607        TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
608        TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
609        TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
610        TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
611        TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
612        TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
613        TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
614        TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
615        TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
616
617
618        #Config 3 Register
619        TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
620        TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
621        TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
622        TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
623        TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
624        TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
625        TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
626        TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
627        TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
628
629        #SRS Ctl - HSS
630        TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
631
632
633        #TestCPUClass.CoreParams.tlb = TLB()
634        #TestCPUClass.CoreParams.UnifiedTLB = 1
635