FSConfig.py revision 8524:1ddd1aa0e55b 
1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
15# All rights reserved.
16#
17# Redistribution and use in source and binary forms, with or without
18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
20# notice, this list of conditions and the following disclaimer;
21# redistributions in binary form must reproduce the above copyright
22# notice, this list of conditions and the following disclaimer in the
23# documentation and/or other materials provided with the distribution;
24# neither the name of the copyright holders nor the names of its
25# contributors may be used to endorse or promote products derived from
26# this software without specific prior written permission.
27#
28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44
45class CowIdeDisk(IdeDisk):
46    image = CowDiskImage(child=RawDiskImage(read_only=True),
47                         read_only=False)
48
49    def childImage(self, ci):
50        self.image.child.image_file = ci
51
52class MemBus(Bus):
53    badaddr_responder = BadAddr()
54    default = Self.badaddr_responder.pio
55
56
57def makeLinuxAlphaSystem(mem_mode, mdesc = None):
58    class BaseTsunami(Tsunami):
59        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
60        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
61                            pci_func=0, pci_dev=0, pci_bus=0)
62
63    self = LinuxAlphaSystem()
64    if not mdesc:
65        # generic system
66        mdesc = SysConfig()
67    self.readfile = mdesc.script()
68    self.iobus = Bus(bus_id=0)
69    self.membus = MemBus(bus_id=1)
70    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
71    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
72    self.bridge.side_a = self.iobus.port
73    self.bridge.side_b = self.membus.port
74    self.physmem.port = self.membus.port
75    self.disk0 = CowIdeDisk(driveID='master')
76    self.disk2 = CowIdeDisk(driveID='master')
77    self.disk0.childImage(mdesc.disk())
78    self.disk2.childImage(disk('linux-bigswap2.img'))
79    self.tsunami = BaseTsunami()
80    self.tsunami.attachIO(self.iobus)
81    self.tsunami.ide.pio = self.iobus.port
82    self.tsunami.ethernet.pio = self.iobus.port
83    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
84                                               read_only = True))
85    self.intrctrl = IntrControl()
86    self.mem_mode = mem_mode
87    self.terminal = Terminal()
88    self.kernel = binary('vmlinux')
89    self.pal = binary('ts_osfpal')
90    self.console = binary('console')
91    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
92
93    return self
94
95def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
96    class BaseTsunami(Tsunami):
97        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
98        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
99                            pci_func=0, pci_dev=0, pci_bus=0)
100
101    physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
102    self = LinuxAlphaSystem(physmem = physmem)
103    if not mdesc:
104        # generic system
105        mdesc = SysConfig()
106    self.readfile = mdesc.script()
107
108    # Create pio bus to connect all device pio ports to rubymem's pio port
109    self.piobus = Bus(bus_id=0)
110
111    #
112    # Pio functional accesses from devices need direct access to memory
113    # RubyPort currently does support functional accesses.  Therefore provide
114    # the piobus a direct connection to physical memory
115    #
116    self.piobus.port = physmem.port
117
118    self.disk0 = CowIdeDisk(driveID='master')
119    self.disk2 = CowIdeDisk(driveID='master')
120    self.disk0.childImage(mdesc.disk())
121    self.disk2.childImage(disk('linux-bigswap2.img'))
122    self.tsunami = BaseTsunami()
123    self.tsunami.attachIO(self.piobus)
124    self.tsunami.ide.pio = self.piobus.port
125    self.tsunami.ethernet.pio = self.piobus.port
126
127    #
128    # Store the dma devices for later connection to dma ruby ports.
129    # Append an underscore to dma_devices to avoid the SimObjectVector check.
130    #
131    self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
132
133    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
134                                               read_only = True))
135    self.intrctrl = IntrControl()
136    self.mem_mode = mem_mode
137    self.terminal = Terminal()
138    self.kernel = binary('vmlinux')
139    self.pal = binary('ts_osfpal')
140    self.console = binary('console')
141    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
142
143    return self
144
145def makeSparcSystem(mem_mode, mdesc = None):
146    class CowMmDisk(MmDisk):
147        image = CowDiskImage(child=RawDiskImage(read_only=True),
148                             read_only=False)
149
150        def childImage(self, ci):
151            self.image.child.image_file = ci
152
153    self = SparcSystem()
154    if not mdesc:
155        # generic system
156        mdesc = SysConfig()
157    self.readfile = mdesc.script()
158    self.iobus = Bus(bus_id=0)
159    self.membus = MemBus(bus_id=1)
160    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
161    self.t1000 = T1000()
162    self.t1000.attachOnChipIO(self.membus)
163    self.t1000.attachIO(self.iobus)
164    self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
165    self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
166    self.bridge.side_a = self.iobus.port
167    self.bridge.side_b = self.membus.port
168    self.physmem.port = self.membus.port
169    self.physmem2.port = self.membus.port
170    self.rom.port = self.membus.port
171    self.nvram.port = self.membus.port
172    self.hypervisor_desc.port = self.membus.port
173    self.partition_desc.port = self.membus.port
174    self.intrctrl = IntrControl()
175    self.disk0 = CowMmDisk()
176    self.disk0.childImage(disk('disk.s10hw2'))
177    self.disk0.pio = self.iobus.port
178    self.reset_bin = binary('reset_new.bin')
179    self.hypervisor_bin = binary('q_new.bin')
180    self.openboot_bin = binary('openboot_new.bin')
181    self.nvram_bin = binary('nvram1')
182    self.hypervisor_desc_bin = binary('1up-hv.bin')
183    self.partition_desc_bin = binary('1up-md.bin')
184
185    return self
186
187def makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False):
188    assert machine_type
189
190    if bare_metal:
191        self = ArmSystem()
192    else:
193        self = LinuxArmSystem()
194
195    if not mdesc:
196        # generic system
197        mdesc = SysConfig()
198
199    self.readfile = mdesc.script()
200    self.iobus = Bus(bus_id=0)
201    self.membus = MemBus(bus_id=1)
202    self.membus.badaddr_responder.warn_access = "warn"
203    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
204    self.bridge.side_a = self.iobus.port
205    self.bridge.side_b = self.membus.port
206
207    self.mem_mode = mem_mode
208
209    if machine_type == "RealView_PBX":
210        self.realview = RealViewPBX()
211    elif machine_type == "RealView_EB":
212        self.realview = RealViewEB()
213    elif machine_type == "VersatileExpress":
214        self.realview = VExpress()
215    else:
216        print "Unknown Machine Type"
217        sys.exit(1)
218
219    use_cf = False
220    if mdesc.disk()[-4:] == ".img":
221        use_cf = True
222        self.cf0 = CowIdeDisk(driveID='master')
223        self.cf0.childImage(mdesc.disk())
224        self.realview.cf_ctrl.disks = [self.cf0]
225
226    if bare_metal:
227        # EOT character on UART will end the simulation
228        self.realview.uart.end_on_eot = True
229        self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')),
230                                      zero = True)
231    else:
232        self.kernel = binary('vmlinux.arm')
233        self.machine_type = machine_type
234        boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
235                     'rw loglevel=8 '
236        if use_cf:
237            self.physmem = PhysicalMemory(range = AddrRange(Addr('256MB')),
238                                          zero = True)
239            boot_flags += "mem=256MB root=/dev/sda1 "
240            self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'),
241                                        size = '64MB'), zero = True)
242            self.nvmem.port = self.membus.port
243            self.boot_loader = binary('boot.arm')
244            self.boot_loader_mem = self.nvmem
245            self.gic_cpu_addr = self.realview.gic.cpu_addr
246            self.flags_addr = self.realview.realview_io.pio_addr + 0x30
247        else:
248            self.physmem = PhysicalMemory(range = AddrRange(Addr('128MB')),
249                                          zero = True)
250            self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'),
251                                          size = '128MB'),
252                                          file = disk(mdesc.disk()))
253            self.diskmem.port = self.membus.port
254            boot_flags +=  "mem=128MB slram=slram0,0x8000000,+0x8000000 " + \
255                            "mtdparts=slram0:- root=/dev/mtdblock0 "
256
257        if mdesc.disk().count('android'):
258            boot_flags += "init=/init "
259        self.boot_osflags = boot_flags
260
261    self.physmem.port = self.membus.port
262    self.realview.attachOnChipIO(self.membus)
263    self.realview.attachIO(self.iobus)
264
265    self.intrctrl = IntrControl()
266    self.terminal = Terminal()
267    self.vncserver = VncServer()
268
269    return self
270
271
272def makeLinuxMipsSystem(mem_mode, mdesc = None):
273    class BaseMalta(Malta):
274        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
275        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
276                            pci_func=0, pci_dev=0, pci_bus=0)
277
278    self = LinuxMipsSystem()
279    if not mdesc:
280        # generic system
281        mdesc = SysConfig()
282    self.readfile = mdesc.script()
283    self.iobus = Bus(bus_id=0)
284    self.membus = MemBus(bus_id=1)
285    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
286    self.physmem = PhysicalMemory(range = AddrRange('1GB'))
287    self.bridge.side_a = self.iobus.port
288    self.bridge.side_b = self.membus.port
289    self.physmem.port = self.membus.port
290    self.disk0 = CowIdeDisk(driveID='master')
291    self.disk2 = CowIdeDisk(driveID='master')
292    self.disk0.childImage(mdesc.disk())
293    self.disk2.childImage(disk('linux-bigswap2.img'))
294    self.malta = BaseMalta()
295    self.malta.attachIO(self.iobus)
296    self.malta.ide.pio = self.iobus.port
297    self.malta.ethernet.pio = self.iobus.port
298    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
299                                               read_only = True))
300    self.intrctrl = IntrControl()
301    self.mem_mode = mem_mode
302    self.terminal = Terminal()
303    self.kernel = binary('mips/vmlinux')
304    self.console = binary('mips/console')
305    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
306
307    return self
308
309def x86IOAddress(port):
310    IO_address_space_base = 0x8000000000000000
311    return IO_address_space_base + port
312
313def connectX86ClassicSystem(x86_sys):
314    x86_sys.membus = MemBus(bus_id=1)
315    x86_sys.physmem.port = x86_sys.membus.port
316
317    # North Bridge
318    x86_sys.iobus = Bus(bus_id=0)
319    x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns')
320    x86_sys.bridge.side_a = x86_sys.iobus.port
321    x86_sys.bridge.side_b = x86_sys.membus.port
322
323    # connect the io bus
324    x86_sys.pc.attachIO(x86_sys.iobus)
325
326def connectX86RubySystem(x86_sys):
327    # North Bridge
328    x86_sys.piobus = Bus(bus_id=0)
329
330    #
331    # Pio functional accesses from devices need direct access to memory
332    # RubyPort currently does support functional accesses.  Therefore provide
333    # the piobus a direct connection to physical memory
334    #
335    x86_sys.piobus.port = x86_sys.physmem.port
336
337    x86_sys.pc.attachIO(x86_sys.piobus)
338
339
340def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False):
341    if self == None:
342        self = X86System()
343
344    if not mdesc:
345        # generic system
346        mdesc = SysConfig()
347    self.readfile = mdesc.script()
348
349    self.mem_mode = mem_mode
350
351    # Physical memory
352    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
353
354    # Platform
355    self.pc = Pc()
356
357    # Create and connect the busses required by each memory system
358    if Ruby:
359        connectX86RubySystem(self)
360        # add the ide to the list of dma devices that later need to attach to
361        # dma controllers
362        self._dma_devices = [self.pc.south_bridge.ide]
363    else:
364        connectX86ClassicSystem(self)
365
366    self.intrctrl = IntrControl()
367
368    # Disks
369    disk0 = CowIdeDisk(driveID='master')
370    disk2 = CowIdeDisk(driveID='master')
371    disk0.childImage(mdesc.disk())
372    disk2.childImage(disk('linux-bigswap2.img'))
373    self.pc.south_bridge.ide.disks = [disk0, disk2]
374
375    # Add in a Bios information structure.
376    structures = [X86SMBiosBiosInformation()]
377    self.smbios_table.structures = structures
378
379    # Set up the Intel MP table
380    base_entries = []
381    ext_entries = []
382    for i in xrange(numCPUs):
383        bp = X86IntelMPProcessor(
384                local_apic_id = i,
385                local_apic_version = 0x14,
386                enable = True,
387                bootstrap = (i == 0))
388        base_entries.append(bp)
389    io_apic = X86IntelMPIOAPIC(
390            id = numCPUs,
391            version = 0x11,
392            enable = True,
393            address = 0xfec00000)
394    self.pc.south_bridge.io_apic.apic_id = io_apic.id
395    base_entries.append(io_apic)
396    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
397    base_entries.append(isa_bus)
398    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
399    base_entries.append(pci_bus)
400    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
401            subtractive_decode=True, parent_bus=1)
402    ext_entries.append(connect_busses)
403    pci_dev4_inta = X86IntelMPIOIntAssignment(
404            interrupt_type = 'INT',
405            polarity = 'ConformPolarity',
406            trigger = 'ConformTrigger',
407            source_bus_id = 1,
408            source_bus_irq = 0 + (4 << 2),
409            dest_io_apic_id = io_apic.id,
410            dest_io_apic_intin = 16)
411    base_entries.append(pci_dev4_inta)
412    def assignISAInt(irq, apicPin):
413        assign_8259_to_apic = X86IntelMPIOIntAssignment(
414                interrupt_type = 'ExtInt',
415                polarity = 'ConformPolarity',
416                trigger = 'ConformTrigger',
417                source_bus_id = 0,
418                source_bus_irq = irq,
419                dest_io_apic_id = io_apic.id,
420                dest_io_apic_intin = 0)
421        base_entries.append(assign_8259_to_apic)
422        assign_to_apic = X86IntelMPIOIntAssignment(
423                interrupt_type = 'INT',
424                polarity = 'ConformPolarity',
425                trigger = 'ConformTrigger',
426                source_bus_id = 0,
427                source_bus_irq = irq,
428                dest_io_apic_id = io_apic.id,
429                dest_io_apic_intin = apicPin)
430        base_entries.append(assign_to_apic)
431    assignISAInt(0, 2)
432    assignISAInt(1, 1)
433    for i in range(3, 15):
434        assignISAInt(i, i)
435    self.intel_mp_table.base_entries = base_entries
436    self.intel_mp_table.ext_entries = ext_entries
437
438def setWorkCountOptions(system, options):
439    if options.work_item_id != None:
440        system.work_item_id = options.work_item_id
441    if options.work_begin_cpu_id_exit != None:
442        system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit
443    if options.work_end_exit_count != None:
444        system.work_end_exit_count = options.work_end_exit_count
445    if options.work_end_checkpoint_count != None:
446        system.work_end_ckpt_count = options.work_end_checkpoint_count
447    if options.work_begin_exit_count != None:
448        system.work_begin_exit_count = options.work_begin_exit_count
449    if options.work_begin_checkpoint_count != None:
450        system.work_begin_ckpt_count = options.work_begin_checkpoint_count
451    if options.work_cpus_checkpoint_count != None:
452        system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count
453
454
455def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False):
456    self = LinuxX86System()
457
458    # Build up the x86 system and then specialize it for Linux
459    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
460
461    # We assume below that there's at least 1MB of memory. We'll require 2
462    # just to avoid corner cases.
463    assert(self.physmem.range.second.getValue() >= 0x200000)
464
465    self.e820_table.entries = \
466       [
467        # Mark the first megabyte of memory as reserved
468        X86E820Entry(addr = 0, size = '1MB', range_type = 2),
469        # Mark the rest as available
470        X86E820Entry(addr = 0x100000,
471                size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
472                range_type = 1)
473        ]
474
475    # Command line
476    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
477                        'root=/dev/hda1'
478    return self
479
480
481def makeDualRoot(testSystem, driveSystem, dumpfile):
482    self = Root()
483    self.testsys = testSystem
484    self.drivesys = driveSystem
485    self.etherlink = EtherLink()
486    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
487    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
488
489    if dumpfile:
490        self.etherdump = EtherDump(file=dumpfile)
491        self.etherlink.dump = Parent.etherdump
492
493    return self
494
495def setMipsOptions(TestCPUClass):
496        #CP0 Configuration
497        TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
498        TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
499        TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
500        TestCPUClass.CoreParams.CP0_PRId_Revision = 0
501
502        #CP0 Interrupt Control
503        TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
504        TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
505
506        # Config Register
507        #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
508        #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
509        TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
510        TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
511        TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
512        TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
513        #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
514
515        #Config 1 Register
516        TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
517        TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
518        # ***VERY IMPORTANT***
519        # Remember to modify CP0_Config1 according to cache specs
520        # Examine file ../common/Cache.py
521        TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
522        TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
523        TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
524        TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
525        TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
526        TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
527        TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
528        TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
529        TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
530        TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
531        TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
532        TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
533        TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
534
535        #Config 2 Register
536        TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
537        TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
538        TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
539        TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
540        TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
541        TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
542        TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
543        TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
544        TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
545
546
547        #Config 3 Register
548        TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
549        TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
550        TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
551        TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
552        TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
553        TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
554        TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
555        TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
556        TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
557
558        #SRS Ctl - HSS
559        TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
560
561
562        #TestCPUClass.CoreParams.tlb = TLB()
563        #TestCPUClass.CoreParams.UnifiedTLB = 1
564