FSConfig.py revision 7937
111507SCurtis.Dunham@arm.com# Copyright (c) 2010 ARM Limited 211507SCurtis.Dunham@arm.com# All rights reserved. 311960Sgabeblack@google.com# 411960Sgabeblack@google.com# The license below extends only to copyright in the software and shall 511960Sgabeblack@google.com# not be construed as granting a license to any other intellectual 611960Sgabeblack@google.com# property including but not limited to intellectual property relating 711960Sgabeblack@google.com# to a hardware implementation of the functionality of the software 811960Sgabeblack@google.com# licensed hereunder. You may use the software subject to the license 911960Sgabeblack@google.com# terms below provided that you ensure that this notice is replicated 1011960Sgabeblack@google.com# unmodified and in its entirety in all distributions of the software, 1111960Sgabeblack@google.com# modified or unmodified, in source code or in binary form. 1211960Sgabeblack@google.com# 1311960Sgabeblack@google.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 1411960Sgabeblack@google.com# Copyright (c) 2006-2008 The Regents of The University of Michigan 1511960Sgabeblack@google.com# All rights reserved. 1611960Sgabeblack@google.com# 1711960Sgabeblack@google.com# Redistribution and use in source and binary forms, with or without 1811960Sgabeblack@google.com# modification, are permitted provided that the following conditions are 1911960Sgabeblack@google.com# met: redistributions of source code must retain the above copyright 2011960Sgabeblack@google.com# notice, this list of conditions and the following disclaimer; 2111960Sgabeblack@google.com# redistributions in binary form must reproduce the above copyright 2211960Sgabeblack@google.com# notice, this list of conditions and the following disclaimer in the 2311960Sgabeblack@google.com# documentation and/or other materials provided with the distribution; 2411960Sgabeblack@google.com# neither the name of the copyright holders nor the names of its 2511960Sgabeblack@google.com# contributors may be used to endorse or promote products derived from 2611960Sgabeblack@google.com# this software without specific prior written permission. 2711960Sgabeblack@google.com# 2811960Sgabeblack@google.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911960Sgabeblack@google.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011960Sgabeblack@google.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111960Sgabeblack@google.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211960Sgabeblack@google.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311960Sgabeblack@google.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411960Sgabeblack@google.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511960Sgabeblack@google.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611960Sgabeblack@google.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711960Sgabeblack@google.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811960Sgabeblack@google.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911960Sgabeblack@google.com# 4011960Sgabeblack@google.com# Authors: Kevin Lim 4111960Sgabeblack@google.com 4211960Sgabeblack@google.comfrom m5.objects import * 4311960Sgabeblack@google.comfrom Benchmarks import * 4411960Sgabeblack@google.com 4511960Sgabeblack@google.comclass CowIdeDisk(IdeDisk): 4611960Sgabeblack@google.com image = CowDiskImage(child=RawDiskImage(read_only=True), 4711960Sgabeblack@google.com read_only=False) 4811960Sgabeblack@google.com 4911960Sgabeblack@google.com def childImage(self, ci): 5011960Sgabeblack@google.com self.image.child.image_file = ci 5111960Sgabeblack@google.com 5211960Sgabeblack@google.comclass MemBus(Bus): 5311960Sgabeblack@google.com badaddr_responder = BadAddr() 5411960Sgabeblack@google.com default = Self.badaddr_responder.pio 5511960Sgabeblack@google.com 5611960Sgabeblack@google.com 5711960Sgabeblack@google.comdef makeLinuxAlphaSystem(mem_mode, mdesc = None): 5811960Sgabeblack@google.com class BaseTsunami(Tsunami): 5911960Sgabeblack@google.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 6011960Sgabeblack@google.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 6111960Sgabeblack@google.com pci_func=0, pci_dev=0, pci_bus=0) 6211960Sgabeblack@google.com 6311960Sgabeblack@google.com self = LinuxAlphaSystem() 6411960Sgabeblack@google.com if not mdesc: 6511960Sgabeblack@google.com # generic system 6611960Sgabeblack@google.com mdesc = SysConfig() 6711960Sgabeblack@google.com self.readfile = mdesc.script() 6811960Sgabeblack@google.com self.iobus = Bus(bus_id=0) 6911960Sgabeblack@google.com self.membus = MemBus(bus_id=1) 7011960Sgabeblack@google.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 7111960Sgabeblack@google.com self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 7211960Sgabeblack@google.com self.bridge.side_a = self.iobus.port 7311960Sgabeblack@google.com self.bridge.side_b = self.membus.port 7411960Sgabeblack@google.com self.physmem.port = self.membus.port 7511960Sgabeblack@google.com self.disk0 = CowIdeDisk(driveID='master') 7611960Sgabeblack@google.com self.disk2 = CowIdeDisk(driveID='master') 7711960Sgabeblack@google.com self.disk0.childImage(mdesc.disk()) 7811960Sgabeblack@google.com self.disk2.childImage(disk('linux-bigswap2.img')) 7911960Sgabeblack@google.com self.tsunami = BaseTsunami() 8011960Sgabeblack@google.com self.tsunami.attachIO(self.iobus) 8111960Sgabeblack@google.com self.tsunami.ide.pio = self.iobus.port 8211960Sgabeblack@google.com self.tsunami.ethernet.pio = self.iobus.port 8311960Sgabeblack@google.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 8411960Sgabeblack@google.com read_only = True)) 8511960Sgabeblack@google.com self.intrctrl = IntrControl() 8611960Sgabeblack@google.com self.mem_mode = mem_mode 8711960Sgabeblack@google.com self.terminal = Terminal() 8811960Sgabeblack@google.com self.kernel = binary('vmlinux') 8911960Sgabeblack@google.com self.pal = binary('ts_osfpal') 9011960Sgabeblack@google.com self.console = binary('console') 9111960Sgabeblack@google.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 9211960Sgabeblack@google.com 9311960Sgabeblack@google.com return self 9411960Sgabeblack@google.com 9511960Sgabeblack@google.comdef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 9611960Sgabeblack@google.com class BaseTsunami(Tsunami): 9711960Sgabeblack@google.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 9811960Sgabeblack@google.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 9911960Sgabeblack@google.com pci_func=0, pci_dev=0, pci_bus=0) 10011960Sgabeblack@google.com 10111960Sgabeblack@google.com physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 10211960Sgabeblack@google.com self = LinuxAlphaSystem(physmem = physmem) 10311960Sgabeblack@google.com if not mdesc: 10411960Sgabeblack@google.com # generic system 10511960Sgabeblack@google.com mdesc = SysConfig() 10611960Sgabeblack@google.com self.readfile = mdesc.script() 10711960Sgabeblack@google.com 10811960Sgabeblack@google.com # Create pio bus to connect all device pio ports to rubymem's pio port 10911960Sgabeblack@google.com self.piobus = Bus(bus_id=0) 11011960Sgabeblack@google.com 11111960Sgabeblack@google.com # 11211960Sgabeblack@google.com # Pio functional accesses from devices need direct access to memory 11311960Sgabeblack@google.com # RubyPort currently does support functional accesses. Therefore provide 11411960Sgabeblack@google.com # the piobus a direct connection to physical memory 11511960Sgabeblack@google.com # 11611960Sgabeblack@google.com self.piobus.port = physmem.port 11711960Sgabeblack@google.com 11811960Sgabeblack@google.com self.disk0 = CowIdeDisk(driveID='master') 11911960Sgabeblack@google.com self.disk2 = CowIdeDisk(driveID='master') 12011960Sgabeblack@google.com self.disk0.childImage(mdesc.disk()) 12111960Sgabeblack@google.com self.disk2.childImage(disk('linux-bigswap2.img')) 12211960Sgabeblack@google.com self.tsunami = BaseTsunami() 12311960Sgabeblack@google.com self.tsunami.attachIO(self.piobus) 12411960Sgabeblack@google.com self.tsunami.ide.pio = self.piobus.port 12511960Sgabeblack@google.com self.tsunami.ethernet.pio = self.piobus.port 12611960Sgabeblack@google.com 12711960Sgabeblack@google.com # 12811960Sgabeblack@google.com # Store the dma devices for later connection to dma ruby ports. 12911960Sgabeblack@google.com # Append an underscore to dma_devices to avoid the SimObjectVector check. 13011960Sgabeblack@google.com # 13111960Sgabeblack@google.com self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet] 13211960Sgabeblack@google.com 13311960Sgabeblack@google.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 13411960Sgabeblack@google.com read_only = True)) 13511960Sgabeblack@google.com self.intrctrl = IntrControl() 13611960Sgabeblack@google.com self.mem_mode = mem_mode 13711960Sgabeblack@google.com self.terminal = Terminal() 13811960Sgabeblack@google.com self.kernel = binary('vmlinux') 13911960Sgabeblack@google.com self.pal = binary('ts_osfpal') 14011960Sgabeblack@google.com self.console = binary('console') 14111960Sgabeblack@google.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 14211960Sgabeblack@google.com 14311960Sgabeblack@google.com return self 14411960Sgabeblack@google.com 14511960Sgabeblack@google.comdef makeSparcSystem(mem_mode, mdesc = None): 14611960Sgabeblack@google.com class CowMmDisk(MmDisk): 14711960Sgabeblack@google.com image = CowDiskImage(child=RawDiskImage(read_only=True), 14811960Sgabeblack@google.com read_only=False) 14911960Sgabeblack@google.com 15011960Sgabeblack@google.com def childImage(self, ci): 15111960Sgabeblack@google.com self.image.child.image_file = ci 15211960Sgabeblack@google.com 15311960Sgabeblack@google.com self = SparcSystem() 15411960Sgabeblack@google.com if not mdesc: 15511960Sgabeblack@google.com # generic system 15611960Sgabeblack@google.com mdesc = SysConfig() 15711960Sgabeblack@google.com self.readfile = mdesc.script() 15811960Sgabeblack@google.com self.iobus = Bus(bus_id=0) 15911960Sgabeblack@google.com self.membus = MemBus(bus_id=1) 16011960Sgabeblack@google.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 16111960Sgabeblack@google.com self.t1000 = T1000() 16211960Sgabeblack@google.com self.t1000.attachOnChipIO(self.membus) 16311960Sgabeblack@google.com self.t1000.attachIO(self.iobus) 16411960Sgabeblack@google.com self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 16511960Sgabeblack@google.com self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 16611960Sgabeblack@google.com self.bridge.side_a = self.iobus.port 16711960Sgabeblack@google.com self.bridge.side_b = self.membus.port 16811960Sgabeblack@google.com self.physmem.port = self.membus.port 16911960Sgabeblack@google.com self.physmem2.port = self.membus.port 17011960Sgabeblack@google.com self.rom.port = self.membus.port 17111960Sgabeblack@google.com self.nvram.port = self.membus.port 17211960Sgabeblack@google.com self.hypervisor_desc.port = self.membus.port 17311960Sgabeblack@google.com self.partition_desc.port = self.membus.port 17411960Sgabeblack@google.com self.intrctrl = IntrControl() 17511960Sgabeblack@google.com self.disk0 = CowMmDisk() 17611960Sgabeblack@google.com self.disk0.childImage(disk('disk.s10hw2')) 17711960Sgabeblack@google.com self.disk0.pio = self.iobus.port 17811960Sgabeblack@google.com self.reset_bin = binary('reset_new.bin') 17911960Sgabeblack@google.com self.hypervisor_bin = binary('q_new.bin') 18011960Sgabeblack@google.com self.openboot_bin = binary('openboot_new.bin') 18111960Sgabeblack@google.com self.nvram_bin = binary('nvram1') 18211960Sgabeblack@google.com self.hypervisor_desc_bin = binary('1up-hv.bin') 18311960Sgabeblack@google.com self.partition_desc_bin = binary('1up-md.bin') 18411960Sgabeblack@google.com 18511960Sgabeblack@google.com return self 18611960Sgabeblack@google.com 18711960Sgabeblack@google.comdef makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False, 18811960Sgabeblack@google.com machine_type = None): 18911960Sgabeblack@google.com if bare_metal: 19011960Sgabeblack@google.com self = ArmSystem() 19111960Sgabeblack@google.com else: 19211960Sgabeblack@google.com self = LinuxArmSystem() 19311960Sgabeblack@google.com 19411960Sgabeblack@google.com if not mdesc: 19511960Sgabeblack@google.com # generic system 19611960Sgabeblack@google.com mdesc = SysConfig() 19711960Sgabeblack@google.com 19811960Sgabeblack@google.com self.readfile = mdesc.script() 19911960Sgabeblack@google.com self.iobus = Bus(bus_id=0) 20011960Sgabeblack@google.com self.membus = MemBus(bus_id=1) 20111960Sgabeblack@google.com self.membus.badaddr_responder.warn_access = "warn" 20211960Sgabeblack@google.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 20311960Sgabeblack@google.com self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True) 20411960Sgabeblack@google.com self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'), 20511960Sgabeblack@google.com file = disk('ael-arm.ext2')) 20611960Sgabeblack@google.com self.bridge.side_a = self.iobus.port 20711960Sgabeblack@google.com self.bridge.side_b = self.membus.port 20811960Sgabeblack@google.com self.physmem.port = self.membus.port 20911960Sgabeblack@google.com self.diskmem.port = self.membus.port 21011960Sgabeblack@google.com 21111960Sgabeblack@google.com self.mem_mode = mem_mode 21211960Sgabeblack@google.com 21311960Sgabeblack@google.com #self.cf0 = CowIdeDisk(driveID='master') 21411960Sgabeblack@google.com #self.cf0.childImage(mdesc.disk()) 21511960Sgabeblack@google.com #self.cf_ctrl = IdeController(disks=[self.cf0], 21611960Sgabeblack@google.com # pci_func = 0, pci_dev = 0, pci_bus = 0, 21711960Sgabeblack@google.com # io_shift = 1, ctrl_offset = 2, Command = 0x1, 21811960Sgabeblack@google.com # BAR0 = 0x18000000, BAR0Size = '16B', 21911960Sgabeblack@google.com # BAR1 = 0x18000100, BAR1Size = '1B', 22011960Sgabeblack@google.com # BAR0LegacyIO = True, BAR1LegacyIO = True,) 22111960Sgabeblack@google.com #self.cf_ctrl.pio = self.iobus.port 22211960Sgabeblack@google.com 22311960Sgabeblack@google.com if machine_type == "RealView_PBX": 22411960Sgabeblack@google.com self.realview = RealViewPBX() 22511960Sgabeblack@google.com elif machine_type == "RealView_EB": 22611960Sgabeblack@google.com self.realview = RealViewEB() 22711960Sgabeblack@google.com else: 22811960Sgabeblack@google.com print "Unknown Machine Type" 22911960Sgabeblack@google.com sys.exit(1) 23011960Sgabeblack@google.com 23111960Sgabeblack@google.com if not bare_metal and machine_type: 23211960Sgabeblack@google.com self.machine_type = machine_type 23311960Sgabeblack@google.com elif bare_metal: 23411960Sgabeblack@google.com self.realview.uart.end_on_eot = True 23511960Sgabeblack@google.com 23611960Sgabeblack@google.com self.realview.attachOnChipIO(self.membus) 23711960Sgabeblack@google.com self.realview.attachIO(self.iobus) 23811960Sgabeblack@google.com 23911960Sgabeblack@google.com self.intrctrl = IntrControl() 24011960Sgabeblack@google.com self.terminal = Terminal() 24111960Sgabeblack@google.com self.kernel = binary('vmlinux.arm') 24211960Sgabeblack@google.com self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' + \ 24311960Sgabeblack@google.com ' norandmaps slram=slram0,0x8000000,+0x8000000' + \ 24411960Sgabeblack@google.com ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0' 24511960Sgabeblack@google.com 24611960Sgabeblack@google.com return self 24711960Sgabeblack@google.com 24811960Sgabeblack@google.com 24911960Sgabeblack@google.comdef makeLinuxMipsSystem(mem_mode, mdesc = None): 25011960Sgabeblack@google.com class BaseMalta(Malta): 25111960Sgabeblack@google.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 25211960Sgabeblack@google.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 25311960Sgabeblack@google.com pci_func=0, pci_dev=0, pci_bus=0) 25411960Sgabeblack@google.com 25511960Sgabeblack@google.com self = LinuxMipsSystem() 25611960Sgabeblack@google.com if not mdesc: 25711960Sgabeblack@google.com # generic system 25811960Sgabeblack@google.com mdesc = SysConfig() 25911960Sgabeblack@google.com self.readfile = mdesc.script() 26011960Sgabeblack@google.com self.iobus = Bus(bus_id=0) 26111960Sgabeblack@google.com self.membus = MemBus(bus_id=1) 26211960Sgabeblack@google.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 26311960Sgabeblack@google.com self.physmem = PhysicalMemory(range = AddrRange('1GB')) 26411960Sgabeblack@google.com self.bridge.side_a = self.iobus.port 26511960Sgabeblack@google.com self.bridge.side_b = self.membus.port 26611960Sgabeblack@google.com self.physmem.port = self.membus.port 26711960Sgabeblack@google.com self.disk0 = CowIdeDisk(driveID='master') 26811960Sgabeblack@google.com self.disk2 = CowIdeDisk(driveID='master') 26911960Sgabeblack@google.com self.disk0.childImage(mdesc.disk()) 27011960Sgabeblack@google.com self.disk2.childImage(disk('linux-bigswap2.img')) 27111960Sgabeblack@google.com self.malta = BaseMalta() 27211960Sgabeblack@google.com self.malta.attachIO(self.iobus) 27311960Sgabeblack@google.com self.malta.ide.pio = self.iobus.port 27411960Sgabeblack@google.com self.malta.ethernet.pio = self.iobus.port 27511960Sgabeblack@google.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 27611960Sgabeblack@google.com read_only = True)) 27711960Sgabeblack@google.com self.intrctrl = IntrControl() 27811960Sgabeblack@google.com self.mem_mode = mem_mode 27911960Sgabeblack@google.com self.terminal = Terminal() 28011960Sgabeblack@google.com self.kernel = binary('mips/vmlinux') 28111960Sgabeblack@google.com self.console = binary('mips/console') 28211960Sgabeblack@google.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 28311960Sgabeblack@google.com 28411960Sgabeblack@google.com return self 28511960Sgabeblack@google.com 28611960Sgabeblack@google.comdef x86IOAddress(port): 28711960Sgabeblack@google.com IO_address_space_base = 0x8000000000000000 28811960Sgabeblack@google.com return IO_address_space_base + port; 28911960Sgabeblack@google.com 29011960Sgabeblack@google.comdef connectX86ClassicSystem(x86_sys): 29111960Sgabeblack@google.com x86_sys.membus = MemBus(bus_id=1) 29211960Sgabeblack@google.com x86_sys.physmem.port = x86_sys.membus.port 29311960Sgabeblack@google.com 29411960Sgabeblack@google.com # North Bridge 29511960Sgabeblack@google.com x86_sys.iobus = Bus(bus_id=0) 29611960Sgabeblack@google.com x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 29711960Sgabeblack@google.com x86_sys.bridge.side_a = x86_sys.iobus.port 29811960Sgabeblack@google.com x86_sys.bridge.side_b = x86_sys.membus.port 29911960Sgabeblack@google.com 30011960Sgabeblack@google.com # connect the io bus 30111960Sgabeblack@google.com x86_sys.pc.attachIO(x86_sys.iobus) 30211960Sgabeblack@google.com 30311960Sgabeblack@google.comdef connectX86RubySystem(x86_sys): 30411960Sgabeblack@google.com # North Bridge 30511960Sgabeblack@google.com x86_sys.piobus = Bus(bus_id=0) 30611960Sgabeblack@google.com 30711960Sgabeblack@google.com # 30811960Sgabeblack@google.com # Pio functional accesses from devices need direct access to memory 30911960Sgabeblack@google.com # RubyPort currently does support functional accesses. Therefore provide 31011960Sgabeblack@google.com # the piobus a direct connection to physical memory 31111960Sgabeblack@google.com # 31211960Sgabeblack@google.com x86_sys.piobus.port = x86_sys.physmem.port 31311960Sgabeblack@google.com 31411960Sgabeblack@google.com x86_sys.pc.attachIO(x86_sys.piobus) 31511960Sgabeblack@google.com 31611960Sgabeblack@google.com 31711960Sgabeblack@google.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 31811960Sgabeblack@google.com if self == None: 31911960Sgabeblack@google.com self = X86System() 32011960Sgabeblack@google.com 32111960Sgabeblack@google.com if not mdesc: 32211960Sgabeblack@google.com # generic system 32311960Sgabeblack@google.com mdesc = SysConfig() 32411960Sgabeblack@google.com self.readfile = mdesc.script() 32511960Sgabeblack@google.com 32611960Sgabeblack@google.com self.mem_mode = mem_mode 32711960Sgabeblack@google.com 32811960Sgabeblack@google.com # Physical memory 32911960Sgabeblack@google.com self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 33011960Sgabeblack@google.com 33111960Sgabeblack@google.com # Platform 33211960Sgabeblack@google.com self.pc = Pc() 33311960Sgabeblack@google.com 33411960Sgabeblack@google.com # Create and connect the busses required by each memory system 33511960Sgabeblack@google.com if Ruby: 33611960Sgabeblack@google.com connectX86RubySystem(self) 33711960Sgabeblack@google.com # add the ide to the list of dma devices that later need to attach to 33811960Sgabeblack@google.com # dma controllers 33911960Sgabeblack@google.com self._dma_devices = [self.pc.south_bridge.ide] 34011960Sgabeblack@google.com else: 34111960Sgabeblack@google.com connectX86ClassicSystem(self) 34211960Sgabeblack@google.com 34311960Sgabeblack@google.com self.intrctrl = IntrControl() 34411960Sgabeblack@google.com 34511960Sgabeblack@google.com # Disks 34611960Sgabeblack@google.com disk0 = CowIdeDisk(driveID='master') 34711960Sgabeblack@google.com disk2 = CowIdeDisk(driveID='master') 34811960Sgabeblack@google.com disk0.childImage(mdesc.disk()) 34911960Sgabeblack@google.com disk2.childImage(disk('linux-bigswap2.img')) 35011960Sgabeblack@google.com self.pc.south_bridge.ide.disks = [disk0, disk2] 35111960Sgabeblack@google.com 35211960Sgabeblack@google.com # Add in a Bios information structure. 35311960Sgabeblack@google.com structures = [X86SMBiosBiosInformation()] 35411960Sgabeblack@google.com self.smbios_table.structures = structures 35511960Sgabeblack@google.com 35611960Sgabeblack@google.com # Set up the Intel MP table 35711960Sgabeblack@google.com for i in xrange(numCPUs): 35811960Sgabeblack@google.com bp = X86IntelMPProcessor( 35911960Sgabeblack@google.com local_apic_id = i, 36011960Sgabeblack@google.com local_apic_version = 0x14, 36111960Sgabeblack@google.com enable = True, 36211960Sgabeblack@google.com bootstrap = (i == 0)) 36311960Sgabeblack@google.com self.intel_mp_table.add_entry(bp) 36411960Sgabeblack@google.com io_apic = X86IntelMPIOAPIC( 36511960Sgabeblack@google.com id = numCPUs, 36611960Sgabeblack@google.com version = 0x11, 36711960Sgabeblack@google.com enable = True, 36811960Sgabeblack@google.com address = 0xfec00000) 36911960Sgabeblack@google.com self.pc.south_bridge.io_apic.apic_id = io_apic.id 37011960Sgabeblack@google.com self.intel_mp_table.add_entry(io_apic) 37111960Sgabeblack@google.com isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 37211960Sgabeblack@google.com self.intel_mp_table.add_entry(isa_bus) 37311960Sgabeblack@google.com pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 37411960Sgabeblack@google.com self.intel_mp_table.add_entry(pci_bus) 37511960Sgabeblack@google.com connect_busses = X86IntelMPBusHierarchy(bus_id=0, 37611960Sgabeblack@google.com subtractive_decode=True, parent_bus=1) 37711960Sgabeblack@google.com self.intel_mp_table.add_entry(connect_busses) 37811960Sgabeblack@google.com pci_dev4_inta = X86IntelMPIOIntAssignment( 37911960Sgabeblack@google.com interrupt_type = 'INT', 38011960Sgabeblack@google.com polarity = 'ConformPolarity', 38111960Sgabeblack@google.com trigger = 'ConformTrigger', 38211960Sgabeblack@google.com source_bus_id = 1, 38311960Sgabeblack@google.com source_bus_irq = 0 + (4 << 2), 38411960Sgabeblack@google.com dest_io_apic_id = io_apic.id, 38511960Sgabeblack@google.com dest_io_apic_intin = 16) 38611960Sgabeblack@google.com self.intel_mp_table.add_entry(pci_dev4_inta); 38711960Sgabeblack@google.com def assignISAInt(irq, apicPin): 38811960Sgabeblack@google.com assign_8259_to_apic = X86IntelMPIOIntAssignment( 38911960Sgabeblack@google.com interrupt_type = 'ExtInt', 39011960Sgabeblack@google.com polarity = 'ConformPolarity', 39111960Sgabeblack@google.com trigger = 'ConformTrigger', 39211960Sgabeblack@google.com source_bus_id = 0, 39311960Sgabeblack@google.com source_bus_irq = irq, 39411960Sgabeblack@google.com dest_io_apic_id = io_apic.id, 39511960Sgabeblack@google.com dest_io_apic_intin = 0) 39611960Sgabeblack@google.com self.intel_mp_table.add_entry(assign_8259_to_apic) 39711960Sgabeblack@google.com assign_to_apic = X86IntelMPIOIntAssignment( 39811960Sgabeblack@google.com interrupt_type = 'INT', 39911960Sgabeblack@google.com polarity = 'ConformPolarity', 40011960Sgabeblack@google.com trigger = 'ConformTrigger', 40111960Sgabeblack@google.com source_bus_id = 0, 40211960Sgabeblack@google.com source_bus_irq = irq, 40311960Sgabeblack@google.com dest_io_apic_id = io_apic.id, 40411960Sgabeblack@google.com dest_io_apic_intin = apicPin) 40511960Sgabeblack@google.com self.intel_mp_table.add_entry(assign_to_apic) 40611960Sgabeblack@google.com assignISAInt(0, 2) 40711960Sgabeblack@google.com assignISAInt(1, 1) 40811960Sgabeblack@google.com for i in range(3, 15): 40911960Sgabeblack@google.com assignISAInt(i, i) 41011960Sgabeblack@google.com 41111960Sgabeblack@google.comdef setWorkCountOptions(system, options): 41211960Sgabeblack@google.com if options.work_item_id != None: 41311960Sgabeblack@google.com system.work_item_id = options.work_item_id 41411960Sgabeblack@google.com if options.work_begin_cpu_id_exit != None: 41511960Sgabeblack@google.com system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 41611960Sgabeblack@google.com if options.work_end_exit_count != None: 41711960Sgabeblack@google.com system.work_end_exit_count = options.work_end_exit_count 41811960Sgabeblack@google.com if options.work_end_checkpoint_count != None: 41911960Sgabeblack@google.com system.work_end_ckpt_count = options.work_end_checkpoint_count 42011960Sgabeblack@google.com if options.work_begin_exit_count != None: 42111960Sgabeblack@google.com system.work_begin_exit_count = options.work_begin_exit_count 42211960Sgabeblack@google.com if options.work_begin_checkpoint_count != None: 42311960Sgabeblack@google.com system.work_begin_ckpt_count = options.work_begin_checkpoint_count 42411960Sgabeblack@google.com if options.work_cpus_checkpoint_count != None: 42511960Sgabeblack@google.com system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 42611960Sgabeblack@google.com 42711960Sgabeblack@google.com 42811960Sgabeblack@google.comdef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 42911960Sgabeblack@google.com self = LinuxX86System() 43011960Sgabeblack@google.com 43111960Sgabeblack@google.com # Build up the x86 system and then specialize it for Linux 43211960Sgabeblack@google.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 43311960Sgabeblack@google.com 43411960Sgabeblack@google.com # We assume below that there's at least 1MB of memory. We'll require 2 43511960Sgabeblack@google.com # just to avoid corner cases. 43611960Sgabeblack@google.com assert(self.physmem.range.second.getValue() >= 0x200000) 43711960Sgabeblack@google.com 43811960Sgabeblack@google.com # Mark the first megabyte of memory as reserved 43911960Sgabeblack@google.com self.e820_table.entries.append(X86E820Entry( 44011960Sgabeblack@google.com addr = 0, 44111960Sgabeblack@google.com size = '1MB', 44211960Sgabeblack@google.com range_type = 2)) 44311960Sgabeblack@google.com 44411960Sgabeblack@google.com # Mark the rest as available 44511960Sgabeblack@google.com self.e820_table.entries.append(X86E820Entry( 44611960Sgabeblack@google.com addr = 0x100000, 44711960Sgabeblack@google.com size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 44811960Sgabeblack@google.com range_type = 1)) 44911960Sgabeblack@google.com 45011960Sgabeblack@google.com # Command line 45111960Sgabeblack@google.com self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 45211960Sgabeblack@google.com 'root=/dev/hda1' 45311960Sgabeblack@google.com return self 45411960Sgabeblack@google.com 45511960Sgabeblack@google.com 45611960Sgabeblack@google.comdef makeDualRoot(testSystem, driveSystem, dumpfile): 45711960Sgabeblack@google.com self = Root() 45811960Sgabeblack@google.com self.testsys = testSystem 45911960Sgabeblack@google.com self.drivesys = driveSystem 46011960Sgabeblack@google.com self.etherlink = EtherLink() 46111960Sgabeblack@google.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 46211960Sgabeblack@google.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 46311960Sgabeblack@google.com 46411960Sgabeblack@google.com if dumpfile: 46511960Sgabeblack@google.com self.etherdump = EtherDump(file=dumpfile) 46611960Sgabeblack@google.com self.etherlink.dump = Parent.etherdump 46711960Sgabeblack@google.com 46811960Sgabeblack@google.com return self 46911960Sgabeblack@google.com 47011960Sgabeblack@google.comdef setMipsOptions(TestCPUClass): 47111960Sgabeblack@google.com #CP0 Configuration 47211960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 47311960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 47411960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 47511960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_PRId_Revision = 0 47611960Sgabeblack@google.com 47711960Sgabeblack@google.com #CP0 Interrupt Control 47811960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 47911960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 48011960Sgabeblack@google.com 48111960Sgabeblack@google.com # Config Register 48211960Sgabeblack@google.com #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 48311960Sgabeblack@google.com #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 48411960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 48511960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 48611960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 48711960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 48811960Sgabeblack@google.com #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 48911960Sgabeblack@google.com 49011960Sgabeblack@google.com #Config 1 Register 49111960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 49211960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 49311960Sgabeblack@google.com # ***VERY IMPORTANT*** 49411960Sgabeblack@google.com # Remember to modify CP0_Config1 according to cache specs 49511960Sgabeblack@google.com # Examine file ../common/Cache.py 49611960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 49711960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 49811960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 49911960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 50011960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 50111960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 50211960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 50311960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 50411960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 50511960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 50611960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 50711960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 50811960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 50911960Sgabeblack@google.com 51011960Sgabeblack@google.com #Config 2 Register 51111960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 51211960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 51311960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 51411960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 51511960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 51611960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 51711960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 51811960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 51911960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 52011960Sgabeblack@google.com 52111960Sgabeblack@google.com 52211960Sgabeblack@google.com #Config 3 Register 52311960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 52411960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 52511960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 52611960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 52711960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 52811960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 52911960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 53011960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 53111960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 53211960Sgabeblack@google.com 53311960Sgabeblack@google.com #SRS Ctl - HSS 53411960Sgabeblack@google.com TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 53511960Sgabeblack@google.com 53611960Sgabeblack@google.com 53711960Sgabeblack@google.com #TestCPUClass.CoreParams.tlb = TLB() 53811960Sgabeblack@google.com #TestCPUClass.CoreParams.UnifiedTLB = 1 53911960Sgabeblack@google.com