FSConfig.py revision 7869:e9edb137c872 
1# Copyright (c) 2010 ARM Limited
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3#
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13# Copyright (c) 2006-2008 The Regents of The University of Michigan
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27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Kevin Lim
40
41from m5.objects import *
42from Benchmarks import *
43
44class CowIdeDisk(IdeDisk):
45    image = CowDiskImage(child=RawDiskImage(read_only=True),
46                         read_only=False)
47
48    def childImage(self, ci):
49        self.image.child.image_file = ci
50
51class MemBus(Bus):
52    badaddr_responder = BadAddr()
53    default = Self.badaddr_responder.pio
54
55
56def makeLinuxAlphaSystem(mem_mode, mdesc = None):
57    class BaseTsunami(Tsunami):
58        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
59        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
60                            pci_func=0, pci_dev=0, pci_bus=0)
61
62    self = LinuxAlphaSystem()
63    if not mdesc:
64        # generic system
65        mdesc = SysConfig()
66    self.readfile = mdesc.script()
67    self.iobus = Bus(bus_id=0)
68    self.membus = MemBus(bus_id=1)
69    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
70    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
71    self.bridge.side_a = self.iobus.port
72    self.bridge.side_b = self.membus.port
73    self.physmem.port = self.membus.port
74    self.disk0 = CowIdeDisk(driveID='master')
75    self.disk2 = CowIdeDisk(driveID='master')
76    self.disk0.childImage(mdesc.disk())
77    self.disk2.childImage(disk('linux-bigswap2.img'))
78    self.tsunami = BaseTsunami()
79    self.tsunami.attachIO(self.iobus)
80    self.tsunami.ide.pio = self.iobus.port
81    self.tsunami.ethernet.pio = self.iobus.port
82    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
83                                               read_only = True))
84    self.intrctrl = IntrControl()
85    self.mem_mode = mem_mode
86    self.terminal = Terminal()
87    self.kernel = binary('vmlinux')
88    self.pal = binary('ts_osfpal')
89    self.console = binary('console')
90    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
91
92    return self
93
94def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
95    class BaseTsunami(Tsunami):
96        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
97        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
98                            pci_func=0, pci_dev=0, pci_bus=0)
99
100    physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
101    self = LinuxAlphaSystem(physmem = physmem)
102    if not mdesc:
103        # generic system
104        mdesc = SysConfig()
105    self.readfile = mdesc.script()
106
107    # Create pio bus to connect all device pio ports to rubymem's pio port
108    self.piobus = Bus(bus_id=0)
109
110    #
111    # Pio functional accesses from devices need direct access to memory
112    # RubyPort currently does support functional accesses.  Therefore provide
113    # the piobus a direct connection to physical memory
114    #
115    self.piobus.port = physmem.port
116
117    self.disk0 = CowIdeDisk(driveID='master')
118    self.disk2 = CowIdeDisk(driveID='master')
119    self.disk0.childImage(mdesc.disk())
120    self.disk2.childImage(disk('linux-bigswap2.img'))
121    self.tsunami = BaseTsunami()
122    self.tsunami.attachIO(self.piobus)
123    self.tsunami.ide.pio = self.piobus.port
124    self.tsunami.ethernet.pio = self.piobus.port
125
126    #
127    # Store the dma devices for later connection to dma ruby ports.
128    # Append an underscore to dma_devices to avoid the SimObjectVector check.
129    #
130    self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
131
132    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
133                                               read_only = True))
134    self.intrctrl = IntrControl()
135    self.mem_mode = mem_mode
136    self.terminal = Terminal()
137    self.kernel = binary('vmlinux')
138    self.pal = binary('ts_osfpal')
139    self.console = binary('console')
140    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
141
142    return self
143
144def makeSparcSystem(mem_mode, mdesc = None):
145    class CowMmDisk(MmDisk):
146        image = CowDiskImage(child=RawDiskImage(read_only=True),
147                             read_only=False)
148
149        def childImage(self, ci):
150            self.image.child.image_file = ci
151
152    self = SparcSystem()
153    if not mdesc:
154        # generic system
155        mdesc = SysConfig()
156    self.readfile = mdesc.script()
157    self.iobus = Bus(bus_id=0)
158    self.membus = MemBus(bus_id=1)
159    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
160    self.t1000 = T1000()
161    self.t1000.attachOnChipIO(self.membus)
162    self.t1000.attachIO(self.iobus)
163    self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
164    self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
165    self.bridge.side_a = self.iobus.port
166    self.bridge.side_b = self.membus.port
167    self.physmem.port = self.membus.port
168    self.physmem2.port = self.membus.port
169    self.rom.port = self.membus.port
170    self.nvram.port = self.membus.port
171    self.hypervisor_desc.port = self.membus.port
172    self.partition_desc.port = self.membus.port
173    self.intrctrl = IntrControl()
174    self.disk0 = CowMmDisk()
175    self.disk0.childImage(disk('disk.s10hw2'))
176    self.disk0.pio = self.iobus.port
177    self.reset_bin = binary('reset_new.bin')
178    self.hypervisor_bin = binary('q_new.bin')
179    self.openboot_bin = binary('openboot_new.bin')
180    self.nvram_bin = binary('nvram1')
181    self.hypervisor_desc_bin = binary('1up-hv.bin')
182    self.partition_desc_bin = binary('1up-md.bin')
183
184    return self
185
186def makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False,
187        machine_type = None):
188    if bare_metal:
189        self = ArmSystem()
190    else:
191        self = LinuxArmSystem()
192
193    if not mdesc:
194        # generic system
195        mdesc = SysConfig()
196
197    self.readfile = mdesc.script()
198    self.iobus = Bus(bus_id=0)
199    self.membus = MemBus(bus_id=1)
200    self.membus.badaddr_responder.warn_access = "warn"
201    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
202    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
203    self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'),
204                                  file = disk('ael-arm.ext2'))
205    self.bridge.side_a = self.iobus.port
206    self.bridge.side_b = self.membus.port
207    self.physmem.port = self.membus.port
208    self.diskmem.port = self.membus.port
209
210    self.mem_mode = mem_mode
211
212    #self.cf0 = CowIdeDisk(driveID='master')
213    #self.cf0.childImage(mdesc.disk())
214    #self.cf_ctrl = IdeController(disks=[self.cf0],
215    #                             pci_func = 0, pci_dev = 0, pci_bus = 0,
216    #                             io_shift = 1, ctrl_offset = 2, Command = 0x1,
217    #                             BAR0 = 0x18000000, BAR0Size = '16B',
218    #                             BAR1 = 0x18000100, BAR1Size = '1B',
219    #                             BAR0LegacyIO = True, BAR1LegacyIO = True,)
220    #self.cf_ctrl.pio = self.iobus.port
221
222    if machine_type == "RealView_PBX":
223        self.realview = RealViewPBX()
224    elif machine_type == "RealView_EB":
225        self.realview = RealViewEB()
226    else:
227        print "Unknown Machine Type"
228        sys.exit(1)
229
230    if not bare_metal and machine_type:
231        self.machine_type = machine_type
232    elif bare_metal:
233        self.realview.uart.end_on_eot = True
234
235    self.realview.attachOnChipIO(self.membus)
236    self.realview.attachIO(self.iobus)
237
238    self.intrctrl = IntrControl()
239    self.terminal = Terminal()
240    self.kernel = binary('vmlinux.arm')
241    self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' + \
242                        ' norandmaps slram=slram0,0x8000000,+0x8000000' +      \
243                        ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0'
244
245    return self
246
247
248def makeLinuxMipsSystem(mem_mode, mdesc = None):
249    class BaseMalta(Malta):
250        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
251        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
252                            pci_func=0, pci_dev=0, pci_bus=0)
253
254    self = LinuxMipsSystem()
255    if not mdesc:
256        # generic system
257        mdesc = SysConfig()
258    self.readfile = mdesc.script()
259    self.iobus = Bus(bus_id=0)
260    self.membus = MemBus(bus_id=1)
261    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
262    self.physmem = PhysicalMemory(range = AddrRange('1GB'))
263    self.bridge.side_a = self.iobus.port
264    self.bridge.side_b = self.membus.port
265    self.physmem.port = self.membus.port
266    self.disk0 = CowIdeDisk(driveID='master')
267    self.disk2 = CowIdeDisk(driveID='master')
268    self.disk0.childImage(mdesc.disk())
269    self.disk2.childImage(disk('linux-bigswap2.img'))
270    self.malta = BaseMalta()
271    self.malta.attachIO(self.iobus)
272    self.malta.ide.pio = self.iobus.port
273    self.malta.ethernet.pio = self.iobus.port
274    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
275                                               read_only = True))
276    self.intrctrl = IntrControl()
277    self.mem_mode = mem_mode
278    self.terminal = Terminal()
279    self.kernel = binary('mips/vmlinux')
280    self.console = binary('mips/console')
281    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
282
283    return self
284
285def x86IOAddress(port):
286    IO_address_space_base = 0x8000000000000000
287    return IO_address_space_base + port;
288
289def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
290    if self == None:
291        self = X86System()
292
293    if not mdesc:
294        # generic system
295        mdesc = SysConfig()
296    self.readfile = mdesc.script()
297
298    self.mem_mode = mem_mode
299
300    # Physical memory
301    self.membus = MemBus(bus_id=1)
302    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
303    self.physmem.port = self.membus.port
304
305    # North Bridge
306    self.iobus = Bus(bus_id=0)
307    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
308    self.bridge.side_a = self.iobus.port
309    self.bridge.side_b = self.membus.port
310
311    # Platform
312    self.pc = Pc()
313    self.pc.attachIO(self.iobus)
314
315    self.intrctrl = IntrControl()
316
317    # Disks
318    disk0 = CowIdeDisk(driveID='master')
319    disk2 = CowIdeDisk(driveID='master')
320    disk0.childImage(mdesc.disk())
321    disk2.childImage(disk('linux-bigswap2.img'))
322    self.pc.south_bridge.ide.disks = [disk0, disk2]
323
324    # Add in a Bios information structure.
325    structures = [X86SMBiosBiosInformation()]
326    self.smbios_table.structures = structures
327
328    # Set up the Intel MP table
329    for i in xrange(numCPUs):
330        bp = X86IntelMPProcessor(
331                local_apic_id = i,
332                local_apic_version = 0x14,
333                enable = True,
334                bootstrap = (i == 0))
335        self.intel_mp_table.add_entry(bp)
336    io_apic = X86IntelMPIOAPIC(
337            id = numCPUs,
338            version = 0x11,
339            enable = True,
340            address = 0xfec00000)
341    self.pc.south_bridge.io_apic.apic_id = io_apic.id
342    self.intel_mp_table.add_entry(io_apic)
343    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
344    self.intel_mp_table.add_entry(isa_bus)
345    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
346    self.intel_mp_table.add_entry(pci_bus)
347    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
348            subtractive_decode=True, parent_bus=1)
349    self.intel_mp_table.add_entry(connect_busses)
350    pci_dev4_inta = X86IntelMPIOIntAssignment(
351            interrupt_type = 'INT',
352            polarity = 'ConformPolarity',
353            trigger = 'ConformTrigger',
354            source_bus_id = 1,
355            source_bus_irq = 0 + (4 << 2),
356            dest_io_apic_id = io_apic.id,
357            dest_io_apic_intin = 16)
358    self.intel_mp_table.add_entry(pci_dev4_inta);
359    def assignISAInt(irq, apicPin):
360        assign_8259_to_apic = X86IntelMPIOIntAssignment(
361                interrupt_type = 'ExtInt',
362                polarity = 'ConformPolarity',
363                trigger = 'ConformTrigger',
364                source_bus_id = 0,
365                source_bus_irq = irq,
366                dest_io_apic_id = io_apic.id,
367                dest_io_apic_intin = 0)
368        self.intel_mp_table.add_entry(assign_8259_to_apic)
369        assign_to_apic = X86IntelMPIOIntAssignment(
370                interrupt_type = 'INT',
371                polarity = 'ConformPolarity',
372                trigger = 'ConformTrigger',
373                source_bus_id = 0,
374                source_bus_irq = irq,
375                dest_io_apic_id = io_apic.id,
376                dest_io_apic_intin = apicPin)
377        self.intel_mp_table.add_entry(assign_to_apic)
378    assignISAInt(0, 2)
379    assignISAInt(1, 1)
380    for i in range(3, 15):
381        assignISAInt(i, i)
382
383
384def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None):
385    self = LinuxX86System()
386
387    # Build up a generic x86 system and then specialize it for Linux
388    makeX86System(mem_mode, numCPUs, mdesc, self)
389
390    # We assume below that there's at least 1MB of memory. We'll require 2
391    # just to avoid corner cases.
392    assert(self.physmem.range.second.getValue() >= 0x200000)
393
394    # Mark the first megabyte of memory as reserved
395    self.e820_table.entries.append(X86E820Entry(
396                addr = 0,
397                size = '1MB',
398                range_type = 2))
399
400    # Mark the rest as available
401    self.e820_table.entries.append(X86E820Entry(
402                addr = 0x100000,
403                size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
404                range_type = 1))
405
406    # Command line
407    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
408                        'root=/dev/hda1'
409    return self
410
411
412def makeDualRoot(testSystem, driveSystem, dumpfile):
413    self = Root()
414    self.testsys = testSystem
415    self.drivesys = driveSystem
416    self.etherlink = EtherLink()
417    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
418    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
419
420    if dumpfile:
421        self.etherdump = EtherDump(file=dumpfile)
422        self.etherlink.dump = Parent.etherdump
423
424    return self
425
426def setMipsOptions(TestCPUClass):
427        #CP0 Configuration
428        TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
429        TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
430        TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
431        TestCPUClass.CoreParams.CP0_PRId_Revision = 0
432
433        #CP0 Interrupt Control
434        TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
435        TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
436
437        # Config Register
438        #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
439        #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
440        TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
441        TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
442        TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
443        TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
444        #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
445
446        #Config 1 Register
447        TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
448        TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
449        # ***VERY IMPORTANT***
450        # Remember to modify CP0_Config1 according to cache specs
451        # Examine file ../common/Cache.py
452        TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
453        TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
454        TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
455        TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
456        TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
457        TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
458        TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
459        TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
460        TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
461        TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
462        TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
463        TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
464        TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
465
466        #Config 2 Register
467        TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
468        TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
469        TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
470        TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
471        TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
472        TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
473        TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
474        TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
475        TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
476
477
478        #Config 3 Register
479        TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
480        TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
481        TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
482        TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
483        TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
484        TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
485        TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
486        TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
487        TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
488
489        #SRS Ctl - HSS
490        TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
491
492
493        #TestCPUClass.CoreParams.tlb = TLB()
494        #TestCPUClass.CoreParams.UnifiedTLB = 1
495