FSConfig.py revision 7586:da93206873dc 
1# Copyright (c) 2010 ARM Limited
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3#
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38#
39# Authors: Kevin Lim
40
41from m5.objects import *
42from Benchmarks import *
43
44class CowIdeDisk(IdeDisk):
45    image = CowDiskImage(child=RawDiskImage(read_only=True),
46                         read_only=False)
47
48    def childImage(self, ci):
49        self.image.child.image_file = ci
50
51class MemBus(Bus):
52    badaddr_responder = BadAddr()
53    default = Self.badaddr_responder.pio
54
55
56def makeLinuxAlphaSystem(mem_mode, mdesc = None):
57    class BaseTsunami(Tsunami):
58        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
59        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
60                            pci_func=0, pci_dev=0, pci_bus=0)
61
62    self = LinuxAlphaSystem()
63    if not mdesc:
64        # generic system
65        mdesc = SysConfig()
66    self.readfile = mdesc.script()
67    self.iobus = Bus(bus_id=0)
68    self.membus = MemBus(bus_id=1)
69    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
70    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
71    self.bridge.side_a = self.iobus.port
72    self.bridge.side_b = self.membus.port
73    self.physmem.port = self.membus.port
74    self.disk0 = CowIdeDisk(driveID='master')
75    self.disk2 = CowIdeDisk(driveID='master')
76    self.disk0.childImage(mdesc.disk())
77    self.disk2.childImage(disk('linux-bigswap2.img'))
78    self.tsunami = BaseTsunami()
79    self.tsunami.attachIO(self.iobus)
80    self.tsunami.ide.pio = self.iobus.port
81    self.tsunami.ethernet.pio = self.iobus.port
82    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
83                                               read_only = True))
84    self.intrctrl = IntrControl()
85    self.mem_mode = mem_mode
86    self.terminal = Terminal()
87    self.kernel = binary('vmlinux')
88    self.pal = binary('ts_osfpal')
89    self.console = binary('console')
90    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
91
92    return self
93
94def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
95    class BaseTsunami(Tsunami):
96        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
97        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
98                            pci_func=0, pci_dev=0, pci_bus=0)
99
100    physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
101    self = LinuxAlphaSystem(physmem = physmem)
102    if not mdesc:
103        # generic system
104        mdesc = SysConfig()
105    self.readfile = mdesc.script()
106
107    # Create pio bus to connect all device pio ports to rubymem's pio port
108    self.piobus = Bus(bus_id=0)
109
110    #
111    # Pio functional accesses from devices need direct access to memory
112    # RubyPort currently does support functional accesses.  Therefore provide
113    # the piobus a direct connection to physical memory
114    #
115    self.piobus.port = physmem.port
116
117    self.disk0 = CowIdeDisk(driveID='master')
118    self.disk2 = CowIdeDisk(driveID='master')
119    self.disk0.childImage(mdesc.disk())
120    self.disk2.childImage(disk('linux-bigswap2.img'))
121    self.tsunami = BaseTsunami()
122    self.tsunami.attachIO(self.piobus)
123    self.tsunami.ide.pio = self.piobus.port
124    self.tsunami.ethernet.pio = self.piobus.port
125
126    #
127    # store the dma devices for later connection to dma ruby ports
128    #
129    self.dma_devices = [self.tsunami.ide, self.tsunami.ethernet]
130
131    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
132                                               read_only = True))
133    self.intrctrl = IntrControl()
134    self.mem_mode = mem_mode
135    self.terminal = Terminal()
136    self.kernel = binary('vmlinux')
137    self.pal = binary('ts_osfpal')
138    self.console = binary('console')
139    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
140
141    return self
142
143def makeSparcSystem(mem_mode, mdesc = None):
144    class CowMmDisk(MmDisk):
145        image = CowDiskImage(child=RawDiskImage(read_only=True),
146                             read_only=False)
147
148        def childImage(self, ci):
149            self.image.child.image_file = ci
150
151    self = SparcSystem()
152    if not mdesc:
153        # generic system
154        mdesc = SysConfig()
155    self.readfile = mdesc.script()
156    self.iobus = Bus(bus_id=0)
157    self.membus = MemBus(bus_id=1)
158    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
159    self.t1000 = T1000()
160    self.t1000.attachOnChipIO(self.membus)
161    self.t1000.attachIO(self.iobus)
162    self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
163    self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
164    self.bridge.side_a = self.iobus.port
165    self.bridge.side_b = self.membus.port
166    self.physmem.port = self.membus.port
167    self.physmem2.port = self.membus.port
168    self.rom.port = self.membus.port
169    self.nvram.port = self.membus.port
170    self.hypervisor_desc.port = self.membus.port
171    self.partition_desc.port = self.membus.port
172    self.intrctrl = IntrControl()
173    self.disk0 = CowMmDisk()
174    self.disk0.childImage(disk('disk.s10hw2'))
175    self.disk0.pio = self.iobus.port
176    self.reset_bin = binary('reset_new.bin')
177    self.hypervisor_bin = binary('q_new.bin')
178    self.openboot_bin = binary('openboot_new.bin')
179    self.nvram_bin = binary('nvram1')
180    self.hypervisor_desc_bin = binary('1up-hv.bin')
181    self.partition_desc_bin = binary('1up-md.bin')
182
183    return self
184
185def makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False,
186        machine_type = None):
187    if bare_metal:
188        self = ArmSystem()
189    else:
190        self = LinuxArmSystem()
191
192    if not mdesc:
193        # generic system
194        mdesc = SysConfig()
195
196    self.readfile = mdesc.script()
197    self.iobus = Bus(bus_id=0)
198    self.membus = MemBus(bus_id=1)
199    self.membus.badaddr_responder.warn_access = "warn"
200    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
201    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
202    self.bridge.side_a = self.iobus.port
203    self.bridge.side_b = self.membus.port
204    self.physmem.port = self.membus.port
205
206    self.mem_mode = mem_mode
207
208    if machine_type == "RealView_PBX":
209        self.realview = RealViewPBX()
210    elif machine_type == "RealView_EB":
211        self.realview = RealViewEB()
212    else:
213        print "Unknown Machine Type"
214        sys.exit(1)
215
216    if not bare_metal and machine_type:
217        self.machine_type = machine_type
218    elif bare_metal:
219        self.realview.uart.end_on_eot = True
220
221    self.realview.attachOnChipIO(self.membus)
222    self.realview.attachIO(self.iobus)
223
224    self.intrctrl = IntrControl()
225    self.terminal = Terminal()
226    self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps'
227
228    return self
229
230
231def makeLinuxMipsSystem(mem_mode, mdesc = None):
232    class BaseMalta(Malta):
233        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
234        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
235                            pci_func=0, pci_dev=0, pci_bus=0)
236
237    self = LinuxMipsSystem()
238    if not mdesc:
239        # generic system
240        mdesc = SysConfig()
241    self.readfile = mdesc.script()
242    self.iobus = Bus(bus_id=0)
243    self.membus = MemBus(bus_id=1)
244    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
245    self.physmem = PhysicalMemory(range = AddrRange('1GB'))
246    self.bridge.side_a = self.iobus.port
247    self.bridge.side_b = self.membus.port
248    self.physmem.port = self.membus.port
249    self.disk0 = CowIdeDisk(driveID='master')
250    self.disk2 = CowIdeDisk(driveID='master')
251    self.disk0.childImage(mdesc.disk())
252    self.disk2.childImage(disk('linux-bigswap2.img'))
253    self.malta = BaseMalta()
254    self.malta.attachIO(self.iobus)
255    self.malta.ide.pio = self.iobus.port
256    self.malta.ethernet.pio = self.iobus.port
257    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
258                                               read_only = True))
259    self.intrctrl = IntrControl()
260    self.mem_mode = mem_mode
261    self.terminal = Terminal()
262    self.kernel = binary('mips/vmlinux')
263    self.console = binary('mips/console')
264    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
265
266    return self
267
268def x86IOAddress(port):
269    IO_address_space_base = 0x8000000000000000
270    return IO_address_space_base + port;
271
272def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
273    if self == None:
274        self = X86System()
275
276    if not mdesc:
277        # generic system
278        mdesc = SysConfig()
279    mdesc.diskname = 'x86root.img'
280    self.readfile = mdesc.script()
281
282    self.mem_mode = mem_mode
283
284    # Physical memory
285    self.membus = MemBus(bus_id=1)
286    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
287    self.physmem.port = self.membus.port
288
289    # North Bridge
290    self.iobus = Bus(bus_id=0)
291    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
292    self.bridge.side_a = self.iobus.port
293    self.bridge.side_b = self.membus.port
294
295    # Platform
296    self.pc = Pc()
297    self.pc.attachIO(self.iobus)
298
299    self.intrctrl = IntrControl()
300
301    # Disks
302    disk0 = CowIdeDisk(driveID='master')
303    disk2 = CowIdeDisk(driveID='master')
304    disk0.childImage(mdesc.disk())
305    disk2.childImage(disk('linux-bigswap2.img'))
306    self.pc.south_bridge.ide.disks = [disk0, disk2]
307
308    # Add in a Bios information structure.
309    structures = [X86SMBiosBiosInformation()]
310    self.smbios_table.structures = structures
311
312    # Set up the Intel MP table
313    for i in xrange(numCPUs):
314        bp = X86IntelMPProcessor(
315                local_apic_id = i,
316                local_apic_version = 0x14,
317                enable = True,
318                bootstrap = (i == 0))
319        self.intel_mp_table.add_entry(bp)
320    io_apic = X86IntelMPIOAPIC(
321            id = numCPUs,
322            version = 0x11,
323            enable = True,
324            address = 0xfec00000)
325    self.pc.south_bridge.io_apic.apic_id = io_apic.id
326    self.intel_mp_table.add_entry(io_apic)
327    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
328    self.intel_mp_table.add_entry(isa_bus)
329    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
330    self.intel_mp_table.add_entry(pci_bus)
331    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
332            subtractive_decode=True, parent_bus=1)
333    self.intel_mp_table.add_entry(connect_busses)
334    pci_dev4_inta = X86IntelMPIOIntAssignment(
335            interrupt_type = 'INT',
336            polarity = 'ConformPolarity',
337            trigger = 'ConformTrigger',
338            source_bus_id = 1,
339            source_bus_irq = 0 + (4 << 2),
340            dest_io_apic_id = io_apic.id,
341            dest_io_apic_intin = 16)
342    self.intel_mp_table.add_entry(pci_dev4_inta);
343    def assignISAInt(irq, apicPin):
344        assign_8259_to_apic = X86IntelMPIOIntAssignment(
345                interrupt_type = 'ExtInt',
346                polarity = 'ConformPolarity',
347                trigger = 'ConformTrigger',
348                source_bus_id = 0,
349                source_bus_irq = irq,
350                dest_io_apic_id = io_apic.id,
351                dest_io_apic_intin = 0)
352        self.intel_mp_table.add_entry(assign_8259_to_apic)
353        assign_to_apic = X86IntelMPIOIntAssignment(
354                interrupt_type = 'INT',
355                polarity = 'ConformPolarity',
356                trigger = 'ConformTrigger',
357                source_bus_id = 0,
358                source_bus_irq = irq,
359                dest_io_apic_id = io_apic.id,
360                dest_io_apic_intin = apicPin)
361        self.intel_mp_table.add_entry(assign_to_apic)
362    assignISAInt(0, 2)
363    assignISAInt(1, 1)
364    for i in range(3, 15):
365        assignISAInt(i, i)
366
367
368def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None):
369    self = LinuxX86System()
370
371    # Build up a generic x86 system and then specialize it for Linux
372    makeX86System(mem_mode, numCPUs, mdesc, self)
373
374    # We assume below that there's at least 1MB of memory. We'll require 2
375    # just to avoid corner cases.
376    assert(self.physmem.range.second.getValue() >= 0x200000)
377
378    # Mark the first megabyte of memory as reserved
379    self.e820_table.entries.append(X86E820Entry(
380                addr = 0,
381                size = '1MB',
382                range_type = 2))
383
384    # Mark the rest as available
385    self.e820_table.entries.append(X86E820Entry(
386                addr = 0x100000,
387                size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
388                range_type = 1))
389
390    # Command line
391    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
392                        'root=/dev/hda1'
393    return self
394
395
396def makeDualRoot(testSystem, driveSystem, dumpfile):
397    self = Root()
398    self.testsys = testSystem
399    self.drivesys = driveSystem
400    self.etherlink = EtherLink()
401    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
402    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
403
404    if dumpfile:
405        self.etherdump = EtherDump(file=dumpfile)
406        self.etherlink.dump = Parent.etherdump
407
408    return self
409
410def setMipsOptions(TestCPUClass):
411        #CP0 Configuration
412        TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
413        TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
414        TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
415        TestCPUClass.CoreParams.CP0_PRId_Revision = 0
416
417        #CP0 Interrupt Control
418        TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
419        TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
420
421        # Config Register
422        #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
423        #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
424        TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
425        TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
426        TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
427        TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
428        #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
429
430        #Config 1 Register
431        TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
432        TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
433        # ***VERY IMPORTANT***
434        # Remember to modify CP0_Config1 according to cache specs
435        # Examine file ../common/Cache.py
436        TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
437        TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
438        TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
439        TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
440        TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
441        TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
442        TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
443        TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
444        TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
445        TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
446        TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
447        TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
448        TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
449
450        #Config 2 Register
451        TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
452        TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
453        TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
454        TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
455        TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
456        TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
457        TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
458        TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
459        TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
460
461
462        #Config 3 Register
463        TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
464        TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
465        TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
466        TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
467        TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
468        TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
469        TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
470        TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
471        TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
472
473        #SRS Ctl - HSS
474        TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
475
476
477        #TestCPUClass.CoreParams.tlb = TLB()
478        #TestCPUClass.CoreParams.UnifiedTLB = 1
479