FSConfig.py revision 6802:e649cb8af113 
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
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5# modification, are permitted provided that the following conditions are
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7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
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11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29from m5.objects import *
30from Benchmarks import *
31
32class CowIdeDisk(IdeDisk):
33    image = CowDiskImage(child=RawDiskImage(read_only=True),
34                         read_only=False)
35
36    def childImage(self, ci):
37        self.image.child.image_file = ci
38
39class MemBus(Bus):
40    badaddr_responder = BadAddr()
41    default = Self.badaddr_responder.pio
42
43
44def makeLinuxAlphaSystem(mem_mode, mdesc = None):
45    class BaseTsunami(Tsunami):
46        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
47        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
48                            pci_func=0, pci_dev=0, pci_bus=0)
49
50    self = LinuxAlphaSystem()
51    if not mdesc:
52        # generic system
53        mdesc = SysConfig()
54    self.readfile = mdesc.script()
55    self.iobus = Bus(bus_id=0)
56    self.membus = MemBus(bus_id=1)
57    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
58    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
59    self.bridge.side_a = self.iobus.port
60    self.bridge.side_b = self.membus.port
61    self.physmem.port = self.membus.port
62    self.disk0 = CowIdeDisk(driveID='master')
63    self.disk2 = CowIdeDisk(driveID='master')
64    self.disk0.childImage(mdesc.disk())
65    self.disk2.childImage(disk('linux-bigswap2.img'))
66    self.tsunami = BaseTsunami()
67    self.tsunami.attachIO(self.iobus)
68    self.tsunami.ide.pio = self.iobus.port
69    self.tsunami.ethernet.pio = self.iobus.port
70    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
71                                               read_only = True))
72    self.intrctrl = IntrControl()
73    self.mem_mode = mem_mode
74    self.terminal = Terminal()
75    self.kernel = binary('vmlinux')
76    self.pal = binary('ts_osfpal')
77    self.console = binary('console')
78    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
79
80    return self
81
82def makeLinuxAlphaRubySystem(mem_mode, rubymem, mdesc = None):
83    class BaseTsunami(Tsunami):
84        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
85        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
86                            pci_func=0, pci_dev=0, pci_bus=0)
87
88
89    self = LinuxAlphaSystem(physmem = rubymem)
90    if not mdesc:
91        # generic system
92        mdesc = SysConfig()
93    self.readfile = mdesc.script()
94
95    # Create pio bus to connect all device pio ports to rubymem's pio port
96    self.piobus = Bus(bus_id=0)
97
98    self.disk0 = CowIdeDisk(driveID='master')
99    self.disk2 = CowIdeDisk(driveID='master')
100    self.disk0.childImage(mdesc.disk())
101    self.disk2.childImage(disk('linux-bigswap2.img'))
102    self.tsunami = BaseTsunami()
103    self.tsunami.attachIO(self.piobus)
104    self.tsunami.ide.pio = self.piobus.port
105    self.tsunami.ethernet.pio = self.piobus.port
106
107    # connect the dma ports directly to ruby dma ports
108    self.tsunami.ide.dma = self.physmem.dma_port
109    self.tsunami.ethernet.dma = self.physmem.dma_port
110
111    # connect the pio bus to rubymem
112    self.physmem.pio_port = self.piobus.port
113
114    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
115                                               read_only = True))
116    self.intrctrl = IntrControl()
117    self.mem_mode = mem_mode
118    self.terminal = Terminal()
119    self.kernel = binary('vmlinux')
120    self.pal = binary('ts_osfpal')
121    self.console = binary('console')
122    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
123
124    return self
125
126def makeSparcSystem(mem_mode, mdesc = None):
127    class CowMmDisk(MmDisk):
128        image = CowDiskImage(child=RawDiskImage(read_only=True),
129                             read_only=False)
130
131        def childImage(self, ci):
132            self.image.child.image_file = ci
133
134    self = SparcSystem()
135    if not mdesc:
136        # generic system
137        mdesc = SysConfig()
138    self.readfile = mdesc.script()
139    self.iobus = Bus(bus_id=0)
140    self.membus = MemBus(bus_id=1)
141    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
142    self.t1000 = T1000()
143    self.t1000.attachOnChipIO(self.membus)
144    self.t1000.attachIO(self.iobus)
145    self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
146    self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
147    self.bridge.side_a = self.iobus.port
148    self.bridge.side_b = self.membus.port
149    self.physmem.port = self.membus.port
150    self.physmem2.port = self.membus.port
151    self.rom.port = self.membus.port
152    self.nvram.port = self.membus.port
153    self.hypervisor_desc.port = self.membus.port
154    self.partition_desc.port = self.membus.port
155    self.intrctrl = IntrControl()
156    self.disk0 = CowMmDisk()
157    self.disk0.childImage(disk('disk.s10hw2'))
158    self.disk0.pio = self.iobus.port
159    self.reset_bin = binary('reset_new.bin')
160    self.hypervisor_bin = binary('q_new.bin')
161    self.openboot_bin = binary('openboot_new.bin')
162    self.nvram_bin = binary('nvram1')
163    self.hypervisor_desc_bin = binary('1up-hv.bin')
164    self.partition_desc_bin = binary('1up-md.bin')
165
166    return self
167
168def makeLinuxMipsSystem(mem_mode, mdesc = None):
169    class BaseMalta(Malta):
170        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
171        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
172                            pci_func=0, pci_dev=0, pci_bus=0)
173
174    self = LinuxMipsSystem()
175    if not mdesc:
176        # generic system
177        mdesc = SysConfig()
178    self.readfile = mdesc.script()
179    self.iobus = Bus(bus_id=0)
180    self.membus = MemBus(bus_id=1)
181    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
182    self.physmem = PhysicalMemory(range = AddrRange('1GB'))
183    self.bridge.side_a = self.iobus.port
184    self.bridge.side_b = self.membus.port
185    self.physmem.port = self.membus.port
186    self.disk0 = CowIdeDisk(driveID='master')
187    self.disk2 = CowIdeDisk(driveID='master')
188    self.disk0.childImage(mdesc.disk())
189    self.disk2.childImage(disk('linux-bigswap2.img'))
190    self.malta = BaseMalta()
191    self.malta.attachIO(self.iobus)
192    self.malta.ide.pio = self.iobus.port
193    self.malta.ethernet.pio = self.iobus.port
194    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
195                                               read_only = True))
196    self.intrctrl = IntrControl()
197    self.mem_mode = mem_mode
198    self.terminal = Terminal()
199    self.kernel = binary('mips/vmlinux')
200    self.console = binary('mips/console')
201    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
202
203    return self
204
205def x86IOAddress(port):
206    IO_address_space_base = 0x8000000000000000
207    return IO_address_space_base + port;
208
209def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None):
210    if self == None:
211        self = X86System()
212
213    if not mdesc:
214        # generic system
215        mdesc = SysConfig()
216    mdesc.diskname = 'x86root.img'
217    self.readfile = mdesc.script()
218
219    self.mem_mode = mem_mode
220
221    # Physical memory
222    self.membus = MemBus(bus_id=1)
223    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
224    self.physmem.port = self.membus.port
225
226    # North Bridge
227    self.iobus = Bus(bus_id=0)
228    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
229    self.bridge.side_a = self.iobus.port
230    self.bridge.side_b = self.membus.port
231
232    # Platform
233    self.pc = Pc()
234    self.pc.attachIO(self.iobus)
235
236    self.intrctrl = IntrControl()
237
238    # Disks
239    disk0 = CowIdeDisk(driveID='master')
240    disk2 = CowIdeDisk(driveID='master')
241    disk0.childImage(mdesc.disk())
242    disk2.childImage(disk('linux-bigswap2.img'))
243    self.pc.south_bridge.ide.disks = [disk0, disk2]
244
245    # Add in a Bios information structure.
246    structures = [X86SMBiosBiosInformation()]
247    self.smbios_table.structures = structures
248
249    # Set up the Intel MP table
250    for i in xrange(numCPUs):
251        bp = X86IntelMPProcessor(
252                local_apic_id = i,
253                local_apic_version = 0x14,
254                enable = True,
255                bootstrap = (i == 0))
256        self.intel_mp_table.add_entry(bp)
257    io_apic = X86IntelMPIOAPIC(
258            id = numCPUs,
259            version = 0x11,
260            enable = True,
261            address = 0xfec00000)
262    self.pc.south_bridge.io_apic.apic_id = io_apic.id
263    self.intel_mp_table.add_entry(io_apic)
264    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
265    self.intel_mp_table.add_entry(isa_bus)
266    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
267    self.intel_mp_table.add_entry(pci_bus)
268    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
269            subtractive_decode=True, parent_bus=1)
270    self.intel_mp_table.add_entry(connect_busses)
271    pci_dev4_inta = X86IntelMPIOIntAssignment(
272            interrupt_type = 'INT',
273            polarity = 'ConformPolarity',
274            trigger = 'ConformTrigger',
275            source_bus_id = 1,
276            source_bus_irq = 0 + (4 << 2),
277            dest_io_apic_id = io_apic.id,
278            dest_io_apic_intin = 16)
279    self.intel_mp_table.add_entry(pci_dev4_inta);
280    def assignISAInt(irq, apicPin):
281        assign_8259_to_apic = X86IntelMPIOIntAssignment(
282                interrupt_type = 'ExtInt',
283                polarity = 'ConformPolarity',
284                trigger = 'ConformTrigger',
285                source_bus_id = 0,
286                source_bus_irq = irq,
287                dest_io_apic_id = io_apic.id,
288                dest_io_apic_intin = 0)
289        self.intel_mp_table.add_entry(assign_8259_to_apic)
290        assign_to_apic = X86IntelMPIOIntAssignment(
291                interrupt_type = 'INT',
292                polarity = 'ConformPolarity',
293                trigger = 'ConformTrigger',
294                source_bus_id = 0,
295                source_bus_irq = irq,
296                dest_io_apic_id = io_apic.id,
297                dest_io_apic_intin = apicPin)
298        self.intel_mp_table.add_entry(assign_to_apic)
299    assignISAInt(0, 2)
300    assignISAInt(1, 1)
301    for i in range(3, 15):
302        assignISAInt(i, i)
303
304
305def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None):
306    self = LinuxX86System()
307
308    # Build up a generic x86 system and then specialize it for Linux
309    makeX86System(mem_mode, numCPUs, mdesc, self)
310
311    # We assume below that there's at least 1MB of memory. We'll require 2
312    # just to avoid corner cases.
313    assert(self.physmem.range.second >= 0x200000)
314
315    # Mark the first megabyte of memory as reserved
316    self.e820_table.entries.append(X86E820Entry(
317                addr = 0,
318                size = '1MB',
319                range_type = 2))
320
321    # Mark the rest as available
322    self.e820_table.entries.append(X86E820Entry(
323                addr = 0x100000,
324                size = '%dB' % (self.physmem.range.second - 0x100000 + 1),
325                range_type = 1))
326
327    # Command line
328    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
329                        'root=/dev/hda1'
330    return self
331
332
333def makeDualRoot(testSystem, driveSystem, dumpfile):
334    self = Root()
335    self.testsys = testSystem
336    self.drivesys = driveSystem
337    self.etherlink = EtherLink()
338    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
339    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
340
341    if dumpfile:
342        self.etherdump = EtherDump(file=dumpfile)
343        self.etherlink.dump = Parent.etherdump
344
345    return self
346
347def setMipsOptions(TestCPUClass):
348        #CP0 Configuration
349        TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
350        TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
351        TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
352        TestCPUClass.CoreParams.CP0_PRId_Revision = 0
353
354        #CP0 Interrupt Control
355        TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
356        TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
357
358        # Config Register
359        #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
360        #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
361        TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
362        TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
363        TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
364        TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
365        #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
366
367        #Config 1 Register
368        TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
369        TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
370        # ***VERY IMPORTANT***
371        # Remember to modify CP0_Config1 according to cache specs
372        # Examine file ../common/Cache.py
373        TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
374        TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
375        TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
376        TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
377        TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
378        TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
379        TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
380        TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
381        TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
382        TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
383        TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
384        TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
385        TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
386
387        #Config 2 Register
388        TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
389        TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
390        TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
391        TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
392        TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
393        TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
394        TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
395        TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
396        TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
397
398
399        #Config 3 Register
400        TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
401        TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
402        TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
403        TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
404        TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
405        TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
406        TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
407        TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
408        TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
409
410        #SRS Ctl - HSS
411        TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
412
413
414        #TestCPUClass.CoreParams.tlb = TLB()
415        #TestCPUClass.CoreParams.UnifiedTLB = 1
416