FSConfig.py revision 5847:02e0e93d1ba7 
1# Copyright (c) 2006-2008 The Regents of The University of Michigan
2# All rights reserved.
3#
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5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
9# notice, this list of conditions and the following disclaimer in the
10# documentation and/or other materials provided with the distribution;
11# neither the name of the copyright holders nor the names of its
12# contributors may be used to endorse or promote products derived from
13# this software without specific prior written permission.
14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Kevin Lim
28
29import m5
30from m5 import makeList
31from m5.objects import *
32from Benchmarks import *
33
34class CowIdeDisk(IdeDisk):
35    image = CowDiskImage(child=RawDiskImage(read_only=True),
36                         read_only=False)
37
38    def childImage(self, ci):
39        self.image.child.image_file = ci
40
41def makeLinuxAlphaSystem(mem_mode, mdesc = None):
42    class BaseTsunami(Tsunami):
43        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
44        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
45                            pci_func=0, pci_dev=0, pci_bus=0)
46
47    self = LinuxAlphaSystem()
48    if not mdesc:
49        # generic system
50        mdesc = SysConfig()
51    self.readfile = mdesc.script()
52    self.iobus = Bus(bus_id=0)
53    self.membus = Bus(bus_id=1)
54    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
55    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
56    self.bridge.side_a = self.iobus.port
57    self.bridge.side_b = self.membus.port
58    self.physmem.port = self.membus.port
59    self.disk0 = CowIdeDisk(driveID='master')
60    self.disk2 = CowIdeDisk(driveID='master')
61    self.disk0.childImage(mdesc.disk())
62    self.disk2.childImage(disk('linux-bigswap2.img'))
63    self.tsunami = BaseTsunami()
64    self.tsunami.attachIO(self.iobus)
65    self.tsunami.ide.pio = self.iobus.port
66    self.tsunami.ethernet.pio = self.iobus.port
67    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
68                                               read_only = True))
69    self.intrctrl = IntrControl()
70    self.mem_mode = mem_mode
71    self.terminal = Terminal()
72    self.kernel = binary('vmlinux')
73    self.pal = binary('ts_osfpal')
74    self.console = binary('console')
75    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
76
77    return self
78
79def makeSparcSystem(mem_mode, mdesc = None):
80    class CowMmDisk(MmDisk):
81        image = CowDiskImage(child=RawDiskImage(read_only=True),
82                             read_only=False)
83
84        def childImage(self, ci):
85            self.image.child.image_file = ci
86
87    self = SparcSystem()
88    if not mdesc:
89        # generic system
90        mdesc = SysConfig()
91    self.readfile = mdesc.script()
92    self.iobus = Bus(bus_id=0)
93    self.membus = Bus(bus_id=1)
94    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
95    self.t1000 = T1000()
96    self.t1000.attachOnChipIO(self.membus)
97    self.t1000.attachIO(self.iobus)
98    self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True)
99    self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True)
100    self.bridge.side_a = self.iobus.port
101    self.bridge.side_b = self.membus.port
102    self.physmem.port = self.membus.port
103    self.physmem2.port = self.membus.port
104    self.rom.port = self.membus.port
105    self.nvram.port = self.membus.port
106    self.hypervisor_desc.port = self.membus.port
107    self.partition_desc.port = self.membus.port
108    self.intrctrl = IntrControl()
109    self.disk0 = CowMmDisk()
110    self.disk0.childImage(disk('disk.s10hw2'))
111    self.disk0.pio = self.iobus.port
112    self.reset_bin = binary('reset_new.bin')
113    self.hypervisor_bin = binary('q_new.bin')
114    self.openboot_bin = binary('openboot_new.bin')
115    self.nvram_bin = binary('nvram1')
116    self.hypervisor_desc_bin = binary('1up-hv.bin')
117    self.partition_desc_bin = binary('1up-md.bin')
118
119    return self
120
121def makeLinuxMipsSystem(mem_mode, mdesc = None):
122    class BaseMalta(Malta):
123        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
124        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
125                            pci_func=0, pci_dev=0, pci_bus=0)
126
127    self = LinuxMipsSystem()
128    if not mdesc:
129        # generic system
130        mdesc = SysConfig()
131    self.readfile = mdesc.script()
132    self.iobus = Bus(bus_id=0)
133    self.membus = Bus(bus_id=1)
134    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
135    self.physmem = PhysicalMemory(range = AddrRange('1GB'))
136    self.bridge.side_a = self.iobus.port
137    self.bridge.side_b = self.membus.port
138    self.physmem.port = self.membus.port
139    self.disk0 = CowIdeDisk(driveID='master')
140    self.disk2 = CowIdeDisk(driveID='master')
141    self.disk0.childImage(mdesc.disk())
142    self.disk2.childImage(disk('linux-bigswap2.img'))
143    self.malta = BaseMalta()
144    self.malta.attachIO(self.iobus)
145    self.malta.ide.pio = self.iobus.port
146    self.malta.ethernet.pio = self.iobus.port
147    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
148                                               read_only = True))
149    self.intrctrl = IntrControl()
150    self.mem_mode = mem_mode
151    self.terminal = Terminal()
152    self.kernel = binary('mips/vmlinux')
153    self.console = binary('mips/console')
154    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
155
156    return self
157
158def x86IOAddress(port):
159    IO_address_space_base = 0x8000000000000000
160    return IO_address_space_base + port;
161
162def makeX86System(mem_mode, mdesc = None, self = None):
163    if self == None:
164        self = X86System()
165
166    if not mdesc:
167        # generic system
168        mdesc = SysConfig()
169    mdesc.diskname = 'x86root.img'
170    self.readfile = mdesc.script()
171
172    # Physical memory
173    self.membus = Bus(bus_id=1)
174    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
175    self.physmem.port = self.membus.port
176
177    # North Bridge
178    self.iobus = Bus(bus_id=0)
179    self.bridge = Bridge(delay='50ns', nack_delay='4ns')
180    self.bridge.side_a = self.iobus.port
181    self.bridge.side_b = self.membus.port
182
183    # Platform
184    self.pc = Pc()
185    self.pc.attachIO(self.iobus)
186
187    self.intrctrl = IntrControl()
188
189    # Disks
190    disk0 = CowIdeDisk(driveID='master')
191    disk2 = CowIdeDisk(driveID='master')
192    disk0.childImage(mdesc.disk())
193    disk2.childImage(disk('linux-bigswap2.img'))
194    self.pc.south_bridge.ide.disks = [disk0, disk2]
195
196    # Add in a Bios information structure.
197    structures = [X86SMBiosBiosInformation()]
198    self.smbios_table.structures = structures
199
200    # Set up the Intel MP table
201    bp = X86IntelMPProcessor(
202            local_apic_id = 0,
203            local_apic_version = 0x14,
204            enable = True,
205            bootstrap = True)
206    self.intel_mp_table.add_entry(bp)
207    io_apic = X86IntelMPIOAPIC(
208            id = 1,
209            version = 0x11,
210            enable = True,
211            address = 0xfec00000)
212    self.intel_mp_table.add_entry(io_apic)
213    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
214    self.intel_mp_table.add_entry(isa_bus)
215    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
216    self.intel_mp_table.add_entry(pci_bus)
217    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
218            subtractive_decode=True, parent_bus=1)
219    self.intel_mp_table.add_entry(connect_busses)
220    pci_dev4_inta = X86IntelMPIOIntAssignment(
221            interrupt_type = 'INT',
222            polarity = 'ConformPolarity',
223            trigger = 'ConformTrigger',
224            source_bus_id = 1,
225            source_bus_irq = 0 + (4 << 2),
226            dest_io_apic_id = 1,
227            dest_io_apic_intin = 16)
228    assign_8259_0_to_apic = X86IntelMPIOIntAssignment(
229            interrupt_type = 'ExtInt',
230            polarity = 'ConformPolarity',
231            trigger = 'ConformTrigger',
232            source_bus_id = 0,
233            source_bus_irq = 0,
234            dest_io_apic_id = 1,
235            dest_io_apic_intin = 0)
236    self.intel_mp_table.add_entry(assign_8259_0_to_apic)
237    assign_0_to_apic = X86IntelMPIOIntAssignment(
238            interrupt_type = 'INT',
239            polarity = 'ConformPolarity',
240            trigger = 'ConformTrigger',
241            source_bus_id = 0,
242            source_bus_irq = 0,
243            dest_io_apic_id = 1,
244            dest_io_apic_intin = 2)
245    self.intel_mp_table.add_entry(assign_0_to_apic)
246    assign_8259_1_to_apic = X86IntelMPIOIntAssignment(
247            interrupt_type = 'ExtInt',
248            polarity = 'ConformPolarity',
249            trigger = 'ConformTrigger',
250            source_bus_id = 0,
251            source_bus_irq = 1,
252            dest_io_apic_id = 1,
253            dest_io_apic_intin = 0)
254    self.intel_mp_table.add_entry(assign_8259_1_to_apic)
255    assign_1_to_apic = X86IntelMPIOIntAssignment(
256            interrupt_type = 'INT',
257            polarity = 'ConformPolarity',
258            trigger = 'ConformTrigger',
259            source_bus_id = 0,
260            source_bus_irq = 1,
261            dest_io_apic_id = 1,
262            dest_io_apic_intin = 1)
263    self.intel_mp_table.add_entry(assign_1_to_apic)
264    assign_8259_12_to_apic = X86IntelMPIOIntAssignment(
265            interrupt_type = 'ExtInt',
266            polarity = 'ConformPolarity',
267            trigger = 'ConformTrigger',
268            source_bus_id = 0,
269            source_bus_irq = 12,
270            dest_io_apic_id = 1,
271            dest_io_apic_intin = 0)
272    self.intel_mp_table.add_entry(assign_8259_12_to_apic)
273    assign_12_to_apic = X86IntelMPIOIntAssignment(
274            interrupt_type = 'INT',
275            polarity = 'ConformPolarity',
276            trigger = 'ConformTrigger',
277            source_bus_id = 0,
278            source_bus_irq = 12,
279            dest_io_apic_id = 1,
280            dest_io_apic_intin = 12)
281    self.intel_mp_table.add_entry(assign_12_to_apic)
282    assign_8259_14_to_apic = X86IntelMPIOIntAssignment(
283            interrupt_type = 'ExtInt',
284            polarity = 'ConformPolarity',
285            trigger = 'ConformTrigger',
286            source_bus_id = 0,
287            source_bus_irq = 14,
288            dest_io_apic_id = 1,
289            dest_io_apic_intin = 0)
290    self.intel_mp_table.add_entry(assign_8259_14_to_apic)
291    assign_14_to_apic = X86IntelMPIOIntAssignment(
292            interrupt_type = 'INT',
293            polarity = 'ConformPolarity',
294            trigger = 'ConformTrigger',
295            source_bus_id = 0,
296            source_bus_irq = 14,
297            dest_io_apic_id = 1,
298            dest_io_apic_intin = 14)
299    self.intel_mp_table.add_entry(assign_14_to_apic)
300
301
302def makeLinuxX86System(mem_mode, mdesc = None):
303    self = LinuxX86System()
304
305    # Build up a generic x86 system and then specialize it for Linux
306    makeX86System(mem_mode, mdesc, self)
307
308    # We assume below that there's at least 1MB of memory. We'll require 2
309    # just to avoid corner cases.
310    assert(self.physmem.range.second >= 0x200000)
311
312    # Mark the first megabyte of memory as reserved
313    self.e820_table.entries.append(X86E820Entry(
314                addr = 0,
315                size = '1MB',
316                range_type = 2))
317
318    # Mark the rest as available
319    self.e820_table.entries.append(X86E820Entry(
320                addr = 0x100000,
321                size = '%dB' % (self.physmem.range.second - 0x100000 - 1),
322                range_type = 1))
323
324    # Command line
325    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
326                        'root=/dev/hda1'
327    return self
328
329
330def makeDualRoot(testSystem, driveSystem, dumpfile):
331    self = Root()
332    self.testsys = testSystem
333    self.drivesys = driveSystem
334    self.etherlink = EtherLink()
335    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
336    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
337
338    if dumpfile:
339        self.etherdump = EtherDump(file=dumpfile)
340        self.etherlink.dump = Parent.etherdump
341
342    return self
343
344def setMipsOptions(TestCPUClass):
345        #CP0 Configuration
346        TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0
347        TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1
348        TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147
349        TestCPUClass.CoreParams.CP0_PRId_Revision = 0
350
351        #CP0 Interrupt Control
352        TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7
353        TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7
354
355        # Config Register
356        #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB
357        #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB
358        TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian
359        TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2
360        TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32
361        TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU
362        #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached
363
364        #Config 1 Register
365        TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented
366        TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size
367        # ***VERY IMPORTANT***
368        # Remember to modify CP0_Config1 according to cache specs
369        # Examine file ../common/Cache.py
370        TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128)
371        TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5
372        TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1
373        TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2
374        TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5
375        TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1
376        TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?)
377        TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32
378        TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented
379        TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented
380        TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented
381        TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented
382        TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented
383
384        #Config 2 Register
385        TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented
386        TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control
387        TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way
388        TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size
389        TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity
390        TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control
391        TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way
392        TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size
393        TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity
394
395
396        #Config 3 Register
397        TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented
398        TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present
399        TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32
400        TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported
401        TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented
402        TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists)
403        TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present
404        TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented
405        TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented
406
407        #SRS Ctl - HSS
408        TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented
409
410
411        #TestCPUClass.CoreParams.tlb = TLB()
412        #TestCPUClass.CoreParams.UnifiedTLB = 1
413