FSConfig.py revision 5299:e61b9f2a9732
14997Sgblack@eecs.umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 24997Sgblack@eecs.umich.edu# All rights reserved. 34997Sgblack@eecs.umich.edu# 44997Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 54997Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are 64997Sgblack@eecs.umich.edu# met: redistributions of source code must retain the above copyright 74997Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer; 84997Sgblack@eecs.umich.edu# redistributions in binary form must reproduce the above copyright 94997Sgblack@eecs.umich.edu# notice, this list of conditions and the following disclaimer in the 104997Sgblack@eecs.umich.edu# documentation and/or other materials provided with the distribution; 114997Sgblack@eecs.umich.edu# neither the name of the copyright holders nor the names of its 124997Sgblack@eecs.umich.edu# contributors may be used to endorse or promote products derived from 134997Sgblack@eecs.umich.edu# this software without specific prior written permission. 144997Sgblack@eecs.umich.edu# 154997Sgblack@eecs.umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 164997Sgblack@eecs.umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 174997Sgblack@eecs.umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 184997Sgblack@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 194997Sgblack@eecs.umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 204997Sgblack@eecs.umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 214997Sgblack@eecs.umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 224997Sgblack@eecs.umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 234997Sgblack@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 244997Sgblack@eecs.umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 254997Sgblack@eecs.umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 264997Sgblack@eecs.umich.edu# 274997Sgblack@eecs.umich.edu# Authors: Kevin Lim 284997Sgblack@eecs.umich.edu 294997Sgblack@eecs.umich.eduimport m5 304997Sgblack@eecs.umich.edufrom m5 import makeList 314997Sgblack@eecs.umich.edufrom m5.objects import * 324997Sgblack@eecs.umich.edufrom Benchmarks import * 334997Sgblack@eecs.umich.edu 344997Sgblack@eecs.umich.educlass CowIdeDisk(IdeDisk): 354997Sgblack@eecs.umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 364997Sgblack@eecs.umich.edu read_only=False) 374997Sgblack@eecs.umich.edu 384997Sgblack@eecs.umich.edu def childImage(self, ci): 394997Sgblack@eecs.umich.edu self.image.child.image_file = ci 404997Sgblack@eecs.umich.edu 414997Sgblack@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 424997Sgblack@eecs.umich.edu class BaseTsunami(Tsunami): 434997Sgblack@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 444997Sgblack@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 454997Sgblack@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 464997Sgblack@eecs.umich.edu 474997Sgblack@eecs.umich.edu self = LinuxAlphaSystem() 484997Sgblack@eecs.umich.edu if not mdesc: 494997Sgblack@eecs.umich.edu # generic system 504997Sgblack@eecs.umich.edu mdesc = SysConfig() 514997Sgblack@eecs.umich.edu self.readfile = mdesc.script() 524997Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 534997Sgblack@eecs.umich.edu self.membus = Bus(bus_id=1) 544997Sgblack@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 554997Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 564997Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 574997Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 584997Sgblack@eecs.umich.edu self.physmem.port = self.membus.port 594997Sgblack@eecs.umich.edu self.disk0 = CowIdeDisk(driveID='master') 604997Sgblack@eecs.umich.edu self.disk2 = CowIdeDisk(driveID='master') 614997Sgblack@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 624997Sgblack@eecs.umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 634997Sgblack@eecs.umich.edu self.tsunami = BaseTsunami() 644997Sgblack@eecs.umich.edu self.tsunami.attachIO(self.iobus) 654997Sgblack@eecs.umich.edu self.tsunami.ide.pio = self.iobus.port 664997Sgblack@eecs.umich.edu self.tsunami.ethernet.pio = self.iobus.port 674997Sgblack@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 684997Sgblack@eecs.umich.edu read_only = True)) 694997Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 704997Sgblack@eecs.umich.edu self.mem_mode = mem_mode 714997Sgblack@eecs.umich.edu self.sim_console = SimConsole() 724997Sgblack@eecs.umich.edu self.kernel = binary('vmlinux') 734997Sgblack@eecs.umich.edu self.pal = binary('ts_osfpal') 744997Sgblack@eecs.umich.edu self.console = binary('console') 754997Sgblack@eecs.umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 76 77 return self 78 79def makeSparcSystem(mem_mode, mdesc = None): 80 class CowMmDisk(MmDisk): 81 image = CowDiskImage(child=RawDiskImage(read_only=True), 82 read_only=False) 83 84 def childImage(self, ci): 85 self.image.child.image_file = ci 86 87 self = SparcSystem() 88 if not mdesc: 89 # generic system 90 mdesc = SysConfig() 91 self.readfile = mdesc.script() 92 self.iobus = Bus(bus_id=0) 93 self.membus = Bus(bus_id=1) 94 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 95 self.t1000 = T1000() 96 self.t1000.attachOnChipIO(self.membus) 97 self.t1000.attachIO(self.iobus) 98 self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 99 self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 100 self.bridge.side_a = self.iobus.port 101 self.bridge.side_b = self.membus.port 102 self.physmem.port = self.membus.port 103 self.physmem2.port = self.membus.port 104 self.rom.port = self.membus.port 105 self.nvram.port = self.membus.port 106 self.hypervisor_desc.port = self.membus.port 107 self.partition_desc.port = self.membus.port 108 self.intrctrl = IntrControl() 109 self.disk0 = CowMmDisk() 110 self.disk0.childImage(disk('disk.s10hw2')) 111 self.disk0.pio = self.iobus.port 112 self.reset_bin = binary('reset_new.bin') 113 self.hypervisor_bin = binary('q_new.bin') 114 self.openboot_bin = binary('openboot_new.bin') 115 self.nvram_bin = binary('nvram1') 116 self.hypervisor_desc_bin = binary('1up-hv.bin') 117 self.partition_desc_bin = binary('1up-md.bin') 118 119 return self 120 121def makeLinuxMipsSystem(mem_mode, mdesc = None): 122 class BaseMalta(Malta): 123 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 124 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 125 pci_func=0, pci_dev=0, pci_bus=0) 126 127 self = LinuxMipsSystem() 128 if not mdesc: 129 # generic system 130 mdesc = SysConfig() 131 self.readfile = mdesc.script() 132 self.iobus = Bus(bus_id=0) 133 self.membus = Bus(bus_id=1) 134 self.bridge = Bridge(delay='50ns', nack_delay='4ns') 135 self.physmem = PhysicalMemory(range = AddrRange('1GB')) 136 self.bridge.side_a = self.iobus.port 137 self.bridge.side_b = self.membus.port 138 self.physmem.port = self.membus.port 139 self.disk0 = CowIdeDisk(driveID='master') 140 self.disk2 = CowIdeDisk(driveID='master') 141 self.disk0.childImage(mdesc.disk()) 142 self.disk2.childImage(disk('linux-bigswap2.img')) 143 self.malta = BaseMalta() 144 self.malta.attachIO(self.iobus) 145 self.malta.ide.pio = self.iobus.port 146 self.malta.ethernet.pio = self.iobus.port 147 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 148 read_only = True)) 149 self.intrctrl = IntrControl() 150 self.mem_mode = mem_mode 151 self.sim_console = SimConsole() 152 self.kernel = binary('mips/vmlinux') 153 self.console = binary('mips/console') 154 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 155 156 return self 157 158def makeLinuxX86System(mem_mode, mdesc = None): 159 self = LinuxX86System() 160 if not mdesc: 161 # generic system 162 mdesc = SysConfig() 163 self.readfile = mdesc.script() 164 165 # Physical memory 166 self.membus = Bus(bus_id=0) 167 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 168 self.physmem.port = self.membus.port 169 170 # Platform 171 self.opteron = Opteron() 172 173 self.intrctrl = IntrControl() 174 175 return self 176 177 178def makeDualRoot(testSystem, driveSystem, dumpfile): 179 self = Root() 180 self.testsys = testSystem 181 self.drivesys = driveSystem 182 self.etherlink = EtherLink() 183 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 184 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 185 186 if dumpfile: 187 self.etherdump = EtherDump(file=dumpfile) 188 self.etherlink.dump = Parent.etherdump 189 190 return self 191 192def setMipsOptions(TestCPUClass): 193 #CP0 Configuration 194 TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 195 TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 196 TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 197 TestCPUClass.CoreParams.CP0_PRId_Revision = 0 198 199 #CP0 Interrupt Control 200 TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 201 TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 202 203 # Config Register 204 #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 205 #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 206 TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 207 TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 208 TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 209 TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 210 #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 211 212 #Config 1 Register 213 TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 214 TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 215 # ***VERY IMPORTANT*** 216 # Remember to modify CP0_Config1 according to cache specs 217 # Examine file ../common/Cache.py 218 TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 219 TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 220 TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 221 TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 222 TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 223 TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 224 TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 225 TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 226 TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 227 TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 228 TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 229 TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 230 TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 231 232 #Config 2 Register 233 TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 234 TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 235 TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 236 TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 237 TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 238 TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 239 TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 240 TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 241 TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 242 243 244 #Config 3 Register 245 TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 246 TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 247 TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 248 TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 249 TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 250 TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 251 TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 252 TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 253 TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 254 255 #SRS Ctl - HSS 256 TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 257 258 259 #TestCPUClass.CoreParams.tlb = TLB() 260 #TestCPUClass.CoreParams.UnifiedTLB = 1 261