FSConfig.py revision 5263:e059fb430ef3
12SN/A# Copyright (c) 2006-2007 The Regents of The University of Michigan 210466Sandreas.hansson@arm.com# All rights reserved. 38703Sandreas.hansson@arm.com# 48703Sandreas.hansson@arm.com# Redistribution and use in source and binary forms, with or without 58703Sandreas.hansson@arm.com# modification, are permitted provided that the following conditions are 68703Sandreas.hansson@arm.com# met: redistributions of source code must retain the above copyright 78703Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer; 88703Sandreas.hansson@arm.com# redistributions in binary form must reproduce the above copyright 98703Sandreas.hansson@arm.com# notice, this list of conditions and the following disclaimer in the 108703Sandreas.hansson@arm.com# documentation and/or other materials provided with the distribution; 118703Sandreas.hansson@arm.com# neither the name of the copyright holders nor the names of its 128703Sandreas.hansson@arm.com# contributors may be used to endorse or promote products derived from 138703Sandreas.hansson@arm.com# this software without specific prior written permission. 141762SN/A# 157897Shestness@cs.utexas.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262SN/A# 272SN/A# Authors: Kevin Lim 282SN/A 292SN/Aimport m5 302SN/Afrom m5 import makeList 312SN/Afrom m5.objects import * 322SN/Afrom Benchmarks import * 332SN/A 342SN/Aclass CowIdeDisk(IdeDisk): 352SN/A image = CowDiskImage(child=RawDiskImage(read_only=True), 362SN/A read_only=False) 372SN/A 382SN/A def childImage(self, ci): 392SN/A self.image.child.image_file = ci 402665Ssaidi@eecs.umich.edu 412665Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 422665Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 432665Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 447897Shestness@cs.utexas.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 452SN/A pci_func=0, pci_dev=0, pci_bus=0) 462SN/A 472SN/A self = LinuxAlphaSystem() 482SN/A if not mdesc: 492SN/A # generic system 502SN/A mdesc = SysConfig() 519645SAndreas.Sandberg@ARM.com self.readfile = mdesc.script() 5275SN/A self.iobus = Bus(bus_id=0) 532SN/A self.membus = Bus(bus_id=1) 5410466Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 552439SN/A self.physmem = PhysicalMemory(range = AddrRange('64MB')) 562439SN/A self.bridge.side_a = self.iobus.port 57603SN/A self.bridge.side_b = self.membus.port 5810466Sandreas.hansson@arm.com self.physmem.port = self.membus.port 594762Snate@binkert.org self.disk0 = CowIdeDisk(driveID='master') 608703Sandreas.hansson@arm.com self.disk2 = CowIdeDisk(driveID='master') 612520SN/A self.disk0.childImage(mdesc.disk()) 629847Sandreas.hansson@arm.com self.disk2.childImage(disk('linux-bigswap2.img')) 638931Sandreas.hansson@arm.com self.tsunami = BaseTsunami() 644762Snate@binkert.org self.tsunami.attachIO(self.iobus) 656658Snate@binkert.org self.tsunami.ide.pio = self.iobus.port 6610494Sandreas.hansson@arm.com self.tsunami.ethernet.pio = self.iobus.port 6710494Sandreas.hansson@arm.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 6810494Sandreas.hansson@arm.com read_only = True)) 6910494Sandreas.hansson@arm.com self.intrctrl = IntrControl() 7010494Sandreas.hansson@arm.com self.mem_mode = mem_mode 7110494Sandreas.hansson@arm.com self.sim_console = SimConsole() 7210494Sandreas.hansson@arm.com self.kernel = binary('vmlinux') 7310494Sandreas.hansson@arm.com self.pal = binary('ts_osfpal') 741634SN/A self.console = binary('console') 758769Sgblack@eecs.umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 768769Sgblack@eecs.umich.edu 771634SN/A return self 78803SN/A 798769Sgblack@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 802SN/A class CowMmDisk(MmDisk): 818703Sandreas.hansson@arm.com image = CowDiskImage(child=RawDiskImage(read_only=True), 822SN/A read_only=False) 838703Sandreas.hansson@arm.com 848703Sandreas.hansson@arm.com def childImage(self, ci): 858703Sandreas.hansson@arm.com self.image.child.image_file = ci 868703Sandreas.hansson@arm.com 878703Sandreas.hansson@arm.com self = SparcSystem() 888703Sandreas.hansson@arm.com if not mdesc: 898703Sandreas.hansson@arm.com # generic system 908922Swilliam.wang@arm.com mdesc = SysConfig() 918703Sandreas.hansson@arm.com self.readfile = mdesc.script() 928703Sandreas.hansson@arm.com self.iobus = Bus(bus_id=0) 938703Sandreas.hansson@arm.com self.membus = Bus(bus_id=1) 948703Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 958703Sandreas.hansson@arm.com self.t1000 = T1000() 968703Sandreas.hansson@arm.com self.t1000.attachOnChipIO(self.membus) 978703Sandreas.hansson@arm.com self.t1000.attachIO(self.iobus) 988922Swilliam.wang@arm.com self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 998703Sandreas.hansson@arm.com self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1008975Sandreas.hansson@arm.com self.bridge.side_a = self.iobus.port 1018703Sandreas.hansson@arm.com self.bridge.side_b = self.membus.port 1028922Swilliam.wang@arm.com self.physmem.port = self.membus.port 1038922Swilliam.wang@arm.com self.physmem2.port = self.membus.port 1048703Sandreas.hansson@arm.com self.rom.port = self.membus.port 1058703Sandreas.hansson@arm.com self.nvram.port = self.membus.port 1068703Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.port 1078703Sandreas.hansson@arm.com self.partition_desc.port = self.membus.port 108603SN/A self.intrctrl = IntrControl() 1092901Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1108703Sandreas.hansson@arm.com self.disk0.childImage(disk('disk.s10hw2')) 1118706Sandreas.hansson@arm.com self.disk0.pio = self.iobus.port 1128706Sandreas.hansson@arm.com self.reset_bin = binary('reset_new.bin') 1138706Sandreas.hansson@arm.com self.hypervisor_bin = binary('q_new.bin') 1148706Sandreas.hansson@arm.com self.openboot_bin = binary('openboot_new.bin') 1158706Sandreas.hansson@arm.com self.nvram_bin = binary('nvram1') 1168706Sandreas.hansson@arm.com self.hypervisor_desc_bin = binary('1up-hv.bin') 1178852Sandreas.hansson@arm.com self.partition_desc_bin = binary('1up-md.bin') 1188703Sandreas.hansson@arm.com 1198703Sandreas.hansson@arm.com return self 1208703Sandreas.hansson@arm.com 1218703Sandreas.hansson@arm.comdef makeLinuxMipsSystem(mem_mode, mdesc = None): 1228852Sandreas.hansson@arm.com class BaseMalta(Malta): 1238703Sandreas.hansson@arm.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1248922Swilliam.wang@arm.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1258703Sandreas.hansson@arm.com pci_func=0, pci_dev=0, pci_bus=0) 1268703Sandreas.hansson@arm.com 1278703Sandreas.hansson@arm.com self = LinuxMipsSystem() 1288703Sandreas.hansson@arm.com if not mdesc: 1299294Sandreas.hansson@arm.com # generic system 1309294Sandreas.hansson@arm.com mdesc = SysConfig() 1318703Sandreas.hansson@arm.com self.readfile = mdesc.script() 1329524SAndreas.Sandberg@ARM.com self.iobus = Bus(bus_id=0) 1339524SAndreas.Sandberg@ARM.com self.membus = Bus(bus_id=1) 1349524SAndreas.Sandberg@ARM.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1359524SAndreas.Sandberg@ARM.com self.physmem = PhysicalMemory(range = AddrRange('1GB')) 1369524SAndreas.Sandberg@ARM.com self.bridge.side_a = self.iobus.port 1379524SAndreas.Sandberg@ARM.com self.bridge.side_b = self.membus.port 1389524SAndreas.Sandberg@ARM.com self.physmem.port = self.membus.port 1399524SAndreas.Sandberg@ARM.com self.disk0 = CowIdeDisk(driveID='master') 1409524SAndreas.Sandberg@ARM.com self.disk2 = CowIdeDisk(driveID='master') 1419524SAndreas.Sandberg@ARM.com self.disk0.childImage(mdesc.disk()) 1429524SAndreas.Sandberg@ARM.com self.disk2.childImage(disk('linux-bigswap2.img')) 1439524SAndreas.Sandberg@ARM.com self.malta = BaseMalta() 1449524SAndreas.Sandberg@ARM.com self.malta.attachIO(self.iobus) 1454762Snate@binkert.org self.malta.ide.pio = self.iobus.port 1462901Ssaidi@eecs.umich.edu self.malta.ethernet.pio = self.iobus.port 1479524SAndreas.Sandberg@ARM.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1489524SAndreas.Sandberg@ARM.com read_only = True)) 1499524SAndreas.Sandberg@ARM.com self.intrctrl = IntrControl() 1509524SAndreas.Sandberg@ARM.com self.mem_mode = mem_mode 1519524SAndreas.Sandberg@ARM.com self.sim_console = SimConsole() 1529524SAndreas.Sandberg@ARM.com self.kernel = binary('mips/vmlinux') 1539524SAndreas.Sandberg@ARM.com self.console = binary('mips/console') 1549524SAndreas.Sandberg@ARM.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1559524SAndreas.Sandberg@ARM.com 1569524SAndreas.Sandberg@ARM.com return self 1579524SAndreas.Sandberg@ARM.com 1589524SAndreas.Sandberg@ARM.comdef makeX86System(mem_mode, mdesc = None): 1599524SAndreas.Sandberg@ARM.com self = X86System() 1609524SAndreas.Sandberg@ARM.com if not mdesc: 1619524SAndreas.Sandberg@ARM.com # generic system 1629524SAndreas.Sandberg@ARM.com mdesc = SysConfig() 1639524SAndreas.Sandberg@ARM.com self.readfile = mdesc.script() 1649524SAndreas.Sandberg@ARM.com 1659524SAndreas.Sandberg@ARM.com # Physical memory 1669524SAndreas.Sandberg@ARM.com self.membus = Bus(bus_id=0) 1679524SAndreas.Sandberg@ARM.com self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1689524SAndreas.Sandberg@ARM.com self.physmem.port = self.membus.port 1699524SAndreas.Sandberg@ARM.com 1709524SAndreas.Sandberg@ARM.com # Platform 1719524SAndreas.Sandberg@ARM.com self.opteron = Opteron() 1729524SAndreas.Sandberg@ARM.com 1739524SAndreas.Sandberg@ARM.com self.intrctrl = IntrControl() 1749524SAndreas.Sandberg@ARM.com 1759524SAndreas.Sandberg@ARM.com return self 1769524SAndreas.Sandberg@ARM.com 1779524SAndreas.Sandberg@ARM.com 1789524SAndreas.Sandberg@ARM.comdef makeDualRoot(testSystem, driveSystem, dumpfile): 1799524SAndreas.Sandberg@ARM.com self = Root() 1809524SAndreas.Sandberg@ARM.com self.testsys = testSystem 1819524SAndreas.Sandberg@ARM.com self.drivesys = driveSystem 1829524SAndreas.Sandberg@ARM.com self.etherlink = EtherLink() 1839524SAndreas.Sandberg@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 1842901Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 1854762Snate@binkert.org 1869524SAndreas.Sandberg@ARM.com if dumpfile: 1872901Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 1889814Sandreas.hansson@arm.com self.etherlink.dump = Parent.etherdump 1899814Sandreas.hansson@arm.com 1909814Sandreas.hansson@arm.com return self 1919814Sandreas.hansson@arm.com 1929814Sandreas.hansson@arm.comdef setMipsOptions(TestCPUClass): 1939850Sandreas.hansson@arm.com #CP0 Configuration 1942SN/A TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 1959850Sandreas.hansson@arm.com TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 1962SN/A TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 1972680Sktlim@umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 1985714Shsul@eecs.umich.edu 1991806SN/A #CP0 Interrupt Control 2006221Snate@binkert.org TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 2015713Shsul@eecs.umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 2025713Shsul@eecs.umich.edu 2035713Shsul@eecs.umich.edu # Config Register 2045713Shsul@eecs.umich.edu #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 2055714Shsul@eecs.umich.edu #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 2061806SN/A TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 2076227Snate@binkert.org TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 2085714Shsul@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 2091806SN/A TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 210180SN/A #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 2116029Ssteve.reinhardt@amd.com 2126029Ssteve.reinhardt@amd.com #Config 1 Register 2136029Ssteve.reinhardt@amd.com TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 2146029Ssteve.reinhardt@amd.com TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 2158765Sgblack@eecs.umich.edu # ***VERY IMPORTANT*** 2168765Sgblack@eecs.umich.edu # Remember to modify CP0_Config1 according to cache specs 2172378SN/A # Examine file ../common/Cache.py 2182378SN/A TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 2192520SN/A TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 2202520SN/A TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 2218852Sandreas.hansson@arm.com TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 2222520SN/A TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 2231885SN/A TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 2241070SN/A TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 225954SN/A TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 2261070SN/A TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 2271070SN/A TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 2281070SN/A TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 2291070SN/A TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 2301070SN/A TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 2311070SN/A 2321070SN/A #Config 2 Register 2331070SN/A TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 2341070SN/A TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 2351070SN/A TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 2361070SN/A TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 2371070SN/A TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 2387580SAli.Saidi@arm.com TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 2397580SAli.Saidi@arm.com TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 2407580SAli.Saidi@arm.com TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 2417580SAli.Saidi@arm.com TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 2427580SAli.Saidi@arm.com 2437580SAli.Saidi@arm.com 2447580SAli.Saidi@arm.com #Config 3 Register 2457580SAli.Saidi@arm.com TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 24610037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 24710037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 24810037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 24910037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 25010037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 25110037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 25210037SARM gem5 Developers TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 2534997Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 2547770SAli.Saidi@ARM.com 2554997Sgblack@eecs.umich.edu #SRS Ctl - HSS 2564997Sgblack@eecs.umich.edu TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 2574997Sgblack@eecs.umich.edu 2584997Sgblack@eecs.umich.edu 2597770SAli.Saidi@ARM.com #TestCPUClass.CoreParams.tlb = TLB() 2604997Sgblack@eecs.umich.edu #TestCPUClass.CoreParams.UnifiedTLB = 1 2614997Sgblack@eecs.umich.edu