FSConfig.py revision 5222:bb733a878f85
12689Sktlim@umich.edu# Copyright (c) 2006-2007 The Regents of The University of Michigan 22689Sktlim@umich.edu# All rights reserved. 32689Sktlim@umich.edu# 42689Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 52689Sktlim@umich.edu# modification, are permitted provided that the following conditions are 62689Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 72689Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 82689Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 92689Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 102689Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 112689Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 122689Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 132689Sktlim@umich.edu# this software without specific prior written permission. 142689Sktlim@umich.edu# 152689Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 162689Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 172689Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 182689Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 192689Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 202689Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 212689Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 222689Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 232689Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 242689Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 252689Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 262689Sktlim@umich.edu# 272689Sktlim@umich.edu# Authors: Kevin Lim 282689Sktlim@umich.edu 292689Sktlim@umich.eduimport m5 302689Sktlim@umich.edufrom m5 import makeList 3111793Sbrandon.potter@amd.comfrom m5.objects import * 3211793Sbrandon.potter@amd.comfrom Benchmarks import * 332683Sktlim@umich.edu 343402Sktlim@umich.educlass CowIdeDisk(IdeDisk): 352683Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 368793Sgblack@eecs.umich.edu read_only=False) 3713905Sgabeblack@google.com 388799Sgblack@eecs.umich.edu def childImage(self, ci): 397679Sgblack@eecs.umich.edu self.image.child.image_file = ci 408706Sandreas.hansson@arm.com 418706Sandreas.hansson@arm.comdef makeLinuxAlphaSystem(mem_mode, mdesc = None): 428793Sgblack@eecs.umich.edu class BaseTsunami(Tsunami): 432862Sktlim@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 448706Sandreas.hansson@arm.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 452862Sktlim@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 466331Sgblack@eecs.umich.edu 4710537Sandreas.hansson@arm.com self = LinuxAlphaSystem() 4810537Sandreas.hansson@arm.com if not mdesc: 4910537Sandreas.hansson@arm.com # generic system 502683Sktlim@umich.edu mdesc = SysConfig() 518799Sgblack@eecs.umich.edu self.readfile = mdesc.script() 5214023Sgabeblack@google.com self.iobus = Bus(bus_id=0) 532683Sktlim@umich.edu self.membus = Bus(bus_id=1) 542683Sktlim@umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 552683Sktlim@umich.edu self.physmem = PhysicalMemory(range = AddrRange('64MB')) 563486Sktlim@umich.edu self.bridge.side_a = self.iobus.port 573486Sktlim@umich.edu self.bridge.side_b = self.membus.port 588799Sgblack@eecs.umich.edu self.physmem.port = self.membus.port 598706Sandreas.hansson@arm.com self.disk0 = CowIdeDisk(driveID='master') 608799Sgblack@eecs.umich.edu self.disk2 = CowIdeDisk(driveID='master') 618706Sandreas.hansson@arm.com self.disk0.childImage(mdesc.disk()) 623486Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 633486Sktlim@umich.edu self.tsunami = BaseTsunami() 642862Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 6510905Sandreas.sandberg@arm.com self.tsunami.ide.pio = self.iobus.port 662862Sktlim@umich.edu self.tsunami.ethernet.pio = self.iobus.port 672862Sktlim@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 682862Sktlim@umich.edu read_only = True)) 692862Sktlim@umich.edu self.intrctrl = IntrControl() 702862Sktlim@umich.edu self.mem_mode = mem_mode 718806Sgblack@eecs.umich.edu self.sim_console = SimConsole() 728806Sgblack@eecs.umich.edu self.kernel = binary('vmlinux') 738806Sgblack@eecs.umich.edu self.pal = binary('ts_osfpal') 748806Sgblack@eecs.umich.edu self.console = binary('console') 758806Sgblack@eecs.umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 768806Sgblack@eecs.umich.edu 778806Sgblack@eecs.umich.edu return self 788806Sgblack@eecs.umich.edu 7910905Sandreas.sandberg@arm.comdef makeSparcSystem(mem_mode, mdesc = None): 802862Sktlim@umich.edu class CowMmDisk(MmDisk): 812862Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 822862Sktlim@umich.edu read_only=False) 8310905Sandreas.sandberg@arm.com 842862Sktlim@umich.edu def childImage(self, ci): 852862Sktlim@umich.edu self.image.child.image_file = ci 862862Sktlim@umich.edu 872862Sktlim@umich.edu self = SparcSystem() 882862Sktlim@umich.edu if not mdesc: 892862Sktlim@umich.edu # generic system 908806Sgblack@eecs.umich.edu mdesc = SysConfig() 918806Sgblack@eecs.umich.edu self.readfile = mdesc.script() 928806Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 938806Sgblack@eecs.umich.edu self.membus = Bus(bus_id=1) 948806Sgblack@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 958806Sgblack@eecs.umich.edu self.t1000 = T1000() 968806Sgblack@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 978806Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 9810905Sandreas.sandberg@arm.com self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 992862Sktlim@umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1002862Sktlim@umich.edu self.bridge.side_a = self.iobus.port 1013675Sktlim@umich.edu self.bridge.side_b = self.membus.port 1028706Sandreas.hansson@arm.com self.physmem.port = self.membus.port 1033675Sktlim@umich.edu self.physmem2.port = self.membus.port 1048921Sandreas.hansson@arm.com self.rom.port = self.membus.port 1058921Sandreas.hansson@arm.com self.nvram.port = self.membus.port 1068921Sandreas.hansson@arm.com self.hypervisor_desc.port = self.membus.port 1078921Sandreas.hansson@arm.com self.partition_desc.port = self.membus.port 1088921Sandreas.hansson@arm.com self.intrctrl = IntrControl() 1098921Sandreas.hansson@arm.com self.disk0 = CowMmDisk() 1108921Sandreas.hansson@arm.com self.disk0.childImage(disk('disk.s10hw2')) 1118852Sandreas.hansson@arm.com self.disk0.pio = self.iobus.port 11214197Sgabeblack@google.com self.reset_bin = binary('reset_new.bin') 11314197Sgabeblack@google.com self.hypervisor_bin = binary('q_new.bin') 1149814Sandreas.hansson@arm.com self.openboot_bin = binary('openboot_new.bin') 1158921Sandreas.hansson@arm.com self.nvram_bin = binary('nvram1') 1168921Sandreas.hansson@arm.com self.hypervisor_desc_bin = binary('1up-hv.bin') 1178706Sandreas.hansson@arm.com self.partition_desc_bin = binary('1up-md.bin') 1188921Sandreas.hansson@arm.com 11914023Sgabeblack@google.com return self 12014197Sgabeblack@google.com 1218921Sandreas.hansson@arm.comdef makeLinuxMipsSystem(mem_mode, mdesc = None): 1228921Sandreas.hansson@arm.com class BaseMalta(Malta): 1238921Sandreas.hansson@arm.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1243675Sktlim@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1252683Sktlim@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 1269101SBrad.Beckmann@amd.com 1279101SBrad.Beckmann@amd.com self = LinuxMipsSystem() 1289101SBrad.Beckmann@amd.com if not mdesc: 1299101SBrad.Beckmann@amd.com # generic system 1309101SBrad.Beckmann@amd.com mdesc = SysConfig() 1319101SBrad.Beckmann@amd.com self.readfile = mdesc.script() 1329101SBrad.Beckmann@amd.com self.iobus = Bus(bus_id=0) 1339101SBrad.Beckmann@amd.com self.membus = Bus(bus_id=1) 13414022Sgabeblack@google.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1359101SBrad.Beckmann@amd.com self.physmem = PhysicalMemory(range = AddrRange('1GB')) 1369101SBrad.Beckmann@amd.com self.bridge.side_a = self.iobus.port 13714023Sgabeblack@google.com self.bridge.side_b = self.membus.port 13814023Sgabeblack@google.com self.physmem.port = self.membus.port 1399101SBrad.Beckmann@amd.com self.disk0 = CowIdeDisk(driveID='master') 1409101SBrad.Beckmann@amd.com self.disk2 = CowIdeDisk(driveID='master') 1412683Sktlim@umich.edu self.disk0.childImage(mdesc.disk()) 1422683Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 1432683Sktlim@umich.edu self.malta = BaseMalta() 1442683Sktlim@umich.edu self.malta.attachIO(self.iobus) 1452683Sktlim@umich.edu self.malta.ide.pio = self.iobus.port 1462683Sktlim@umich.edu self.malta.ethernet.pio = self.iobus.port 1472683Sktlim@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1482683Sktlim@umich.edu read_only = True)) 1492683Sktlim@umich.edu self.intrctrl = IntrControl() 1502683Sktlim@umich.edu self.mem_mode = mem_mode 1512683Sktlim@umich.edu self.sim_console = SimConsole() 1522683Sktlim@umich.edu self.kernel = binary('mips/vmlinux') 1532683Sktlim@umich.edu self.console = binary('mips/console') 154 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 155 156 return self 157 158def makeX86System(mem_mode, mdesc = None): 159 self = X86System() 160 if not mdesc: 161 # generic system 162 mdesc = SysConfig() 163 self.readfile = mdesc.script() 164 165 # Physical memory 166 self.membus = Bus(bus_id=0) 167 self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 168 self.physmem.port = self.membus.port 169 170 # Platform 171 self.opteron = Opteron() 172 173 self.intrctrl = IntrControl() 174 175 return self 176 177 178def makeDualRoot(testSystem, driveSystem, dumpfile): 179 self = Root() 180 self.testsys = testSystem 181 self.drivesys = driveSystem 182 self.etherlink = EtherLink() 183 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 184 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 185 186 if dumpfile: 187 self.etherdump = EtherDump(file=dumpfile) 188 self.etherlink.dump = Parent.etherdump 189 190 return self 191