FSConfig.py revision 13605:8904f6c497e6
1# Copyright (c) 2010-2012, 2015-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 14# Copyright (c) 2006-2008 The Regents of The University of Michigan 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Kevin Lim 41 42from __future__ import print_function 43 44from m5.objects import * 45from Benchmarks import * 46from m5.util import * 47from common import PlatformConfig 48 49# Populate to reflect supported os types per target ISA 50os_types = { 'alpha' : [ 'linux' ], 51 'mips' : [ 'linux' ], 52 'sparc' : [ 'linux' ], 53 'x86' : [ 'linux' ], 54 'arm' : [ 'linux', 55 'android-gingerbread', 56 'android-ics', 57 'android-jellybean', 58 'android-kitkat', 59 'android-nougat', ], 60 } 61 62class CowIdeDisk(IdeDisk): 63 image = CowDiskImage(child=RawDiskImage(read_only=True), 64 read_only=False) 65 66 def childImage(self, ci): 67 self.image.child.image_file = ci 68 69class MemBus(SystemXBar): 70 badaddr_responder = BadAddr() 71 default = Self.badaddr_responder.pio 72 73def fillInCmdline(mdesc, template, **kwargs): 74 kwargs.setdefault('disk', mdesc.disk()) 75 kwargs.setdefault('rootdev', mdesc.rootdev()) 76 kwargs.setdefault('mem', mdesc.mem()) 77 kwargs.setdefault('script', mdesc.script()) 78 return template % kwargs 79 80def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 81 82 class BaseTsunami(Tsunami): 83 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 84 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 85 pci_func=0, pci_dev=0, pci_bus=0) 86 87 self = LinuxAlphaSystem() 88 if not mdesc: 89 # generic system 90 mdesc = SysConfig() 91 self.readfile = mdesc.script() 92 93 self.tsunami = BaseTsunami() 94 95 # Create the io bus to connect all device ports 96 self.iobus = IOXBar() 97 self.tsunami.attachIO(self.iobus) 98 99 self.tsunami.ide.pio = self.iobus.master 100 101 self.tsunami.ethernet.pio = self.iobus.master 102 103 if ruby: 104 # Store the dma devices for later connection to dma ruby ports. 105 # Append an underscore to dma_ports to avoid the SimObjectVector check. 106 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 107 else: 108 self.membus = MemBus() 109 110 # By default the bridge responds to all addresses above the I/O 111 # base address (including the PCI config space) 112 IO_address_space_base = 0x80000000000 113 self.bridge = Bridge(delay='50ns', 114 ranges = [AddrRange(IO_address_space_base, Addr.max)]) 115 self.bridge.master = self.iobus.slave 116 self.bridge.slave = self.membus.master 117 118 self.tsunami.ide.dma = self.iobus.slave 119 self.tsunami.ethernet.dma = self.iobus.slave 120 121 self.system_port = self.membus.slave 122 123 self.mem_ranges = [AddrRange(mdesc.mem())] 124 self.disk0 = CowIdeDisk(driveID='master') 125 self.disk2 = CowIdeDisk(driveID='master') 126 self.disk0.childImage(mdesc.disk()) 127 self.disk2.childImage(disk('linux-bigswap2.img')) 128 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 129 read_only = True)) 130 self.intrctrl = IntrControl() 131 self.mem_mode = mem_mode 132 self.terminal = Terminal() 133 self.kernel = binary('vmlinux') 134 self.pal = binary('ts_osfpal') 135 self.console = binary('console') 136 if not cmdline: 137 cmdline = 'root=/dev/hda1 console=ttyS0' 138 self.boot_osflags = fillInCmdline(mdesc, cmdline) 139 140 return self 141 142def makeSparcSystem(mem_mode, mdesc=None, cmdline=None): 143 # Constants from iob.cc and uart8250.cc 144 iob_man_addr = 0x9800000000 145 uart_pio_size = 8 146 147 class CowMmDisk(MmDisk): 148 image = CowDiskImage(child=RawDiskImage(read_only=True), 149 read_only=False) 150 151 def childImage(self, ci): 152 self.image.child.image_file = ci 153 154 self = SparcSystem() 155 if not mdesc: 156 # generic system 157 mdesc = SysConfig() 158 self.readfile = mdesc.script() 159 self.iobus = IOXBar() 160 self.membus = MemBus() 161 self.bridge = Bridge(delay='50ns') 162 self.t1000 = T1000() 163 self.t1000.attachOnChipIO(self.membus) 164 self.t1000.attachIO(self.iobus) 165 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 166 AddrRange(Addr('2GB'), size ='256MB')] 167 self.bridge.master = self.iobus.slave 168 self.bridge.slave = self.membus.master 169 self.rom.port = self.membus.master 170 self.nvram.port = self.membus.master 171 self.hypervisor_desc.port = self.membus.master 172 self.partition_desc.port = self.membus.master 173 self.intrctrl = IntrControl() 174 self.disk0 = CowMmDisk() 175 self.disk0.childImage(mdesc.disk()) 176 self.disk0.pio = self.iobus.master 177 178 # The puart0 and hvuart are placed on the IO bus, so create ranges 179 # for them. The remaining IO range is rather fragmented, so poke 180 # holes for the iob and partition descriptors etc. 181 self.bridge.ranges = \ 182 [ 183 AddrRange(self.t1000.puart0.pio_addr, 184 self.t1000.puart0.pio_addr + uart_pio_size - 1), 185 AddrRange(self.disk0.pio_addr, 186 self.t1000.fake_jbi.pio_addr + 187 self.t1000.fake_jbi.pio_size - 1), 188 AddrRange(self.t1000.fake_clk.pio_addr, 189 iob_man_addr - 1), 190 AddrRange(self.t1000.fake_l2_1.pio_addr, 191 self.t1000.fake_ssi.pio_addr + 192 self.t1000.fake_ssi.pio_size - 1), 193 AddrRange(self.t1000.hvuart.pio_addr, 194 self.t1000.hvuart.pio_addr + uart_pio_size - 1) 195 ] 196 self.reset_bin = binary('reset_new.bin') 197 self.hypervisor_bin = binary('q_new.bin') 198 self.openboot_bin = binary('openboot_new.bin') 199 self.nvram_bin = binary('nvram1') 200 self.hypervisor_desc_bin = binary('1up-hv.bin') 201 self.partition_desc_bin = binary('1up-md.bin') 202 203 self.system_port = self.membus.slave 204 205 return self 206 207def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 208 dtb_filename=None, bare_metal=False, cmdline=None, 209 external_memory="", ruby=False, security=False, 210 ignore_dtb=False): 211 assert machine_type 212 213 pci_devices = [] 214 215 if bare_metal: 216 self = ArmSystem() 217 else: 218 self = LinuxArmSystem() 219 220 if not mdesc: 221 # generic system 222 mdesc = SysConfig() 223 224 self.readfile = mdesc.script() 225 self.iobus = IOXBar() 226 if not ruby: 227 self.bridge = Bridge(delay='50ns') 228 self.bridge.master = self.iobus.slave 229 self.membus = MemBus() 230 self.membus.badaddr_responder.warn_access = "warn" 231 self.bridge.slave = self.membus.master 232 233 self.mem_mode = mem_mode 234 235 platform_class = PlatformConfig.get(machine_type) 236 # Resolve the real platform name, the original machine_type 237 # variable might have been an alias. 238 machine_type = platform_class.__name__ 239 self.realview = platform_class() 240 241 if not dtb_filename and not (bare_metal or ignore_dtb): 242 fatal("No DTB specified and no default DTB known for '%s'" % \ 243 machine_type) 244 245 if isinstance(self.realview, VExpress_EMM64): 246 if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 247 print("Selected 64-bit ARM architecture, updating default " 248 "disk image...") 249 mdesc.diskname = 'linaro-minimal-aarch64.img' 250 251 252 # Attach any PCI devices this platform supports 253 self.realview.attachPciDevices() 254 255 self.cf0 = CowIdeDisk(driveID='master') 256 self.cf0.childImage(mdesc.disk()) 257 # Old platforms have a built-in IDE or CF controller. Default to 258 # the IDE controller if both exist. New platforms expect the 259 # storage controller to be added from the config script. 260 if hasattr(self.realview, "ide"): 261 self.realview.ide.disks = [self.cf0] 262 elif hasattr(self.realview, "cf_ctrl"): 263 self.realview.cf_ctrl.disks = [self.cf0] 264 else: 265 self.pci_ide = IdeController(disks=[self.cf0]) 266 pci_devices.append(self.pci_ide) 267 268 self.mem_ranges = [] 269 size_remain = long(Addr(mdesc.mem())) 270 for region in self.realview._mem_regions: 271 if size_remain > long(region[1]): 272 self.mem_ranges.append(AddrRange(region[0], size=region[1])) 273 size_remain = size_remain - long(region[1]) 274 else: 275 self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 276 size_remain = 0 277 break 278 warn("Memory size specified spans more than one region. Creating" \ 279 " another memory controller for that range.") 280 281 if size_remain > 0: 282 fatal("The currently selected ARM platforms doesn't support" \ 283 " the amount of DRAM you've selected. Please try" \ 284 " another platform") 285 286 self.have_security = security 287 288 if bare_metal: 289 # EOT character on UART will end the simulation 290 self.realview.uart[0].end_on_eot = True 291 else: 292 if dtb_filename and not ignore_dtb: 293 self.dtb_filename = binary(dtb_filename) 294 295 self.machine_type = machine_type if machine_type in ArmMachineType.map \ 296 else "DTOnly" 297 298 # Ensure that writes to the UART actually go out early in the boot 299 if not cmdline: 300 cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 301 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 302 'mem=%(mem)s root=%(rootdev)s' 303 304 # When using external memory, gem5 writes the boot loader to nvmem 305 # and then SST will read from it, but SST can only get to nvmem from 306 # iobus, as gem5's membus is only used for initialization and 307 # SST doesn't use it. Attaching nvmem to iobus solves this issue. 308 # During initialization, system_port -> membus -> iobus -> nvmem. 309 if external_memory: 310 self.realview.setupBootLoader(self.iobus, self, binary) 311 elif ruby: 312 self.realview.setupBootLoader(None, self, binary) 313 else: 314 self.realview.setupBootLoader(self.membus, self, binary) 315 316 if hasattr(self.realview.gic, 'cpu_addr'): 317 self.gic_cpu_addr = self.realview.gic.cpu_addr 318 319 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 320 321 # This check is for users who have previously put 'android' in 322 # the disk image filename to tell the config scripts to 323 # prepare the kernel with android-specific boot options. That 324 # behavior has been replaced with a more explicit option per 325 # the error message below. The disk can have any name now and 326 # doesn't need to include 'android' substring. 327 if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 328 if 'android' not in mdesc.os_type(): 329 fatal("It looks like you are trying to boot an Android " \ 330 "platform. To boot Android, you must specify " \ 331 "--os-type with an appropriate Android release on " \ 332 "the command line.") 333 334 # android-specific tweaks 335 if 'android' in mdesc.os_type(): 336 # generic tweaks 337 cmdline += " init=/init" 338 339 # release-specific tweaks 340 if 'kitkat' in mdesc.os_type(): 341 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 342 "android.bootanim=0 " 343 elif 'nougat' in mdesc.os_type(): 344 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 345 "android.bootanim=0 " + \ 346 "vmalloc=640MB " + \ 347 "android.early.fstab=/fstab.gem5 " + \ 348 "androidboot.selinux=permissive " + \ 349 "video=Virtual-1:1920x1080-16" 350 351 self.boot_osflags = fillInCmdline(mdesc, cmdline) 352 353 if external_memory: 354 # I/O traffic enters iobus 355 self.external_io = ExternalMaster(port_data="external_io", 356 port_type=external_memory) 357 self.external_io.port = self.iobus.slave 358 359 # Ensure iocache only receives traffic destined for (actual) memory. 360 self.iocache = ExternalSlave(port_data="iocache", 361 port_type=external_memory, 362 addr_ranges=self.mem_ranges) 363 self.iocache.port = self.iobus.master 364 365 # Let system_port get to nvmem and nothing else. 366 self.bridge.ranges = [self.realview.nvmem.range] 367 368 self.realview.attachOnChipIO(self.iobus) 369 # Attach off-chip devices 370 self.realview.attachIO(self.iobus) 371 elif ruby: 372 self._dma_ports = [ ] 373 self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports) 374 self.realview.attachIO(self.iobus, dma_ports=self._dma_ports) 375 else: 376 self.realview.attachOnChipIO(self.membus, self.bridge) 377 # Attach off-chip devices 378 self.realview.attachIO(self.iobus) 379 380 for dev_id, dev in enumerate(pci_devices): 381 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0) 382 self.realview.attachPciDevice( 383 dev, self.iobus, 384 dma_ports=self._dma_ports if ruby else None) 385 386 self.intrctrl = IntrControl() 387 self.terminal = Terminal() 388 self.vncserver = VncServer() 389 390 if not ruby: 391 self.system_port = self.membus.slave 392 393 if ruby: 394 if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1: 395 fatal("The MI_example protocol cannot implement Load/Store " 396 "Exclusive operations. Multicore ARM systems configured " 397 "with the MI_example protocol will not work properly.") 398 warn("You are trying to use Ruby on ARM, which is not working " 399 "properly yet.") 400 401 return self 402 403 404def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 405 class BaseMalta(Malta): 406 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 407 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 408 pci_func=0, pci_dev=0, pci_bus=0) 409 410 self = LinuxMipsSystem() 411 if not mdesc: 412 # generic system 413 mdesc = SysConfig() 414 self.readfile = mdesc.script() 415 self.iobus = IOXBar() 416 self.membus = MemBus() 417 self.bridge = Bridge(delay='50ns') 418 self.mem_ranges = [AddrRange('1GB')] 419 self.bridge.master = self.iobus.slave 420 self.bridge.slave = self.membus.master 421 self.disk0 = CowIdeDisk(driveID='master') 422 self.disk2 = CowIdeDisk(driveID='master') 423 self.disk0.childImage(mdesc.disk()) 424 self.disk2.childImage(disk('linux-bigswap2.img')) 425 self.malta = BaseMalta() 426 self.malta.attachIO(self.iobus) 427 self.malta.ide.pio = self.iobus.master 428 self.malta.ide.dma = self.iobus.slave 429 self.malta.ethernet.pio = self.iobus.master 430 self.malta.ethernet.dma = self.iobus.slave 431 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 432 read_only = True)) 433 self.intrctrl = IntrControl() 434 self.mem_mode = mem_mode 435 self.terminal = Terminal() 436 self.kernel = binary('mips/vmlinux') 437 self.console = binary('mips/console') 438 if not cmdline: 439 cmdline = 'root=/dev/hda1 console=ttyS0' 440 self.boot_osflags = fillInCmdline(mdesc, cmdline) 441 442 self.system_port = self.membus.slave 443 444 return self 445 446def x86IOAddress(port): 447 IO_address_space_base = 0x8000000000000000 448 return IO_address_space_base + port 449 450def connectX86ClassicSystem(x86_sys, numCPUs): 451 # Constants similar to x86_traits.hh 452 IO_address_space_base = 0x8000000000000000 453 pci_config_address_space_base = 0xc000000000000000 454 interrupts_address_space_base = 0xa000000000000000 455 APIC_range_size = 1 << 12; 456 457 x86_sys.membus = MemBus() 458 459 # North Bridge 460 x86_sys.iobus = IOXBar() 461 x86_sys.bridge = Bridge(delay='50ns') 462 x86_sys.bridge.master = x86_sys.iobus.slave 463 x86_sys.bridge.slave = x86_sys.membus.master 464 # Allow the bridge to pass through: 465 # 1) kernel configured PCI device memory map address: address range 466 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 467 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 468 # 3) everything in the IO address range up to the local APIC, and 469 # 4) then the entire PCI address space and beyond. 470 x86_sys.bridge.ranges = \ 471 [ 472 AddrRange(0xC0000000, 0xFFFF0000), 473 AddrRange(IO_address_space_base, 474 interrupts_address_space_base - 1), 475 AddrRange(pci_config_address_space_base, 476 Addr.max) 477 ] 478 479 # Create a bridge from the IO bus to the memory bus to allow access to 480 # the local APIC (two pages) 481 x86_sys.apicbridge = Bridge(delay='50ns') 482 x86_sys.apicbridge.slave = x86_sys.iobus.master 483 x86_sys.apicbridge.master = x86_sys.membus.slave 484 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 485 interrupts_address_space_base + 486 numCPUs * APIC_range_size 487 - 1)] 488 489 # connect the io bus 490 x86_sys.pc.attachIO(x86_sys.iobus) 491 492 x86_sys.system_port = x86_sys.membus.slave 493 494def connectX86RubySystem(x86_sys): 495 # North Bridge 496 x86_sys.iobus = IOXBar() 497 498 # add the ide to the list of dma devices that later need to attach to 499 # dma controllers 500 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 501 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 502 503 504def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 505 if self == None: 506 self = X86System() 507 508 if not mdesc: 509 # generic system 510 mdesc = SysConfig() 511 self.readfile = mdesc.script() 512 513 self.mem_mode = mem_mode 514 515 # Physical memory 516 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 517 # for various devices. Hence, if the physical memory size is greater than 518 # 3GB, we need to split it into two parts. 519 excess_mem_size = \ 520 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 521 if excess_mem_size <= 0: 522 self.mem_ranges = [AddrRange(mdesc.mem())] 523 else: 524 warn("Physical memory size specified is %s which is greater than " \ 525 "3GB. Twice the number of memory controllers would be " \ 526 "created." % (mdesc.mem())) 527 528 self.mem_ranges = [AddrRange('3GB'), 529 AddrRange(Addr('4GB'), size = excess_mem_size)] 530 531 # Platform 532 self.pc = Pc() 533 534 # Create and connect the busses required by each memory system 535 if Ruby: 536 connectX86RubySystem(self) 537 else: 538 connectX86ClassicSystem(self, numCPUs) 539 540 self.intrctrl = IntrControl() 541 542 # Disks 543 disk0 = CowIdeDisk(driveID='master') 544 disk2 = CowIdeDisk(driveID='master') 545 disk0.childImage(mdesc.disk()) 546 disk2.childImage(disk('linux-bigswap2.img')) 547 self.pc.south_bridge.ide.disks = [disk0, disk2] 548 549 # Add in a Bios information structure. 550 structures = [X86SMBiosBiosInformation()] 551 self.smbios_table.structures = structures 552 553 # Set up the Intel MP table 554 base_entries = [] 555 ext_entries = [] 556 for i in xrange(numCPUs): 557 bp = X86IntelMPProcessor( 558 local_apic_id = i, 559 local_apic_version = 0x14, 560 enable = True, 561 bootstrap = (i == 0)) 562 base_entries.append(bp) 563 io_apic = X86IntelMPIOAPIC( 564 id = numCPUs, 565 version = 0x11, 566 enable = True, 567 address = 0xfec00000) 568 self.pc.south_bridge.io_apic.apic_id = io_apic.id 569 base_entries.append(io_apic) 570 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 571 # but linux kernel cannot config PCI device if it was not connected to PCI bus, 572 # so we fix PCI bus id to 0, and ISA bus id to 1. 573 pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ') 574 base_entries.append(pci_bus) 575 isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ') 576 base_entries.append(isa_bus) 577 connect_busses = X86IntelMPBusHierarchy(bus_id=1, 578 subtractive_decode=True, parent_bus=0) 579 ext_entries.append(connect_busses) 580 pci_dev4_inta = X86IntelMPIOIntAssignment( 581 interrupt_type = 'INT', 582 polarity = 'ConformPolarity', 583 trigger = 'ConformTrigger', 584 source_bus_id = 0, 585 source_bus_irq = 0 + (4 << 2), 586 dest_io_apic_id = io_apic.id, 587 dest_io_apic_intin = 16) 588 base_entries.append(pci_dev4_inta) 589 def assignISAInt(irq, apicPin): 590 assign_8259_to_apic = X86IntelMPIOIntAssignment( 591 interrupt_type = 'ExtInt', 592 polarity = 'ConformPolarity', 593 trigger = 'ConformTrigger', 594 source_bus_id = 1, 595 source_bus_irq = irq, 596 dest_io_apic_id = io_apic.id, 597 dest_io_apic_intin = 0) 598 base_entries.append(assign_8259_to_apic) 599 assign_to_apic = X86IntelMPIOIntAssignment( 600 interrupt_type = 'INT', 601 polarity = 'ConformPolarity', 602 trigger = 'ConformTrigger', 603 source_bus_id = 1, 604 source_bus_irq = irq, 605 dest_io_apic_id = io_apic.id, 606 dest_io_apic_intin = apicPin) 607 base_entries.append(assign_to_apic) 608 assignISAInt(0, 2) 609 assignISAInt(1, 1) 610 for i in range(3, 15): 611 assignISAInt(i, i) 612 self.intel_mp_table.base_entries = base_entries 613 self.intel_mp_table.ext_entries = ext_entries 614 615def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 616 cmdline=None): 617 self = LinuxX86System() 618 619 # Build up the x86 system and then specialize it for Linux 620 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 621 622 # We assume below that there's at least 1MB of memory. We'll require 2 623 # just to avoid corner cases. 624 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 625 assert(phys_mem_size >= 0x200000) 626 assert(len(self.mem_ranges) <= 2) 627 628 entries = \ 629 [ 630 # Mark the first megabyte of memory as reserved 631 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 632 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 633 # Mark the rest of physical memory as available 634 X86E820Entry(addr = 0x100000, 635 size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 636 range_type = 1), 637 ] 638 639 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 640 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 641 # specific range can pass though bridge to iobus. 642 if len(self.mem_ranges) == 1: 643 entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 644 size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 645 range_type=2)) 646 647 # Reserve the last 16kB of the 32-bit address space for the m5op interface 648 entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 649 650 # In case the physical memory is greater than 3GB, we split it into two 651 # parts and add a separate e820 entry for the second part. This entry 652 # starts at 0x100000000, which is the first address after the space 653 # reserved for devices. 654 if len(self.mem_ranges) == 2: 655 entries.append(X86E820Entry(addr = 0x100000000, 656 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 657 658 self.e820_table.entries = entries 659 660 # Command line 661 if not cmdline: 662 cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 663 self.boot_osflags = fillInCmdline(mdesc, cmdline) 664 self.kernel = binary('x86_64-vmlinux-2.6.22.9') 665 return self 666 667 668def makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 669 self = Root(full_system = full_system) 670 self.testsys = testSystem 671 self.drivesys = driveSystem 672 self.etherlink = EtherLink() 673 674 if hasattr(testSystem, 'realview'): 675 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 676 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 677 elif hasattr(testSystem, 'tsunami'): 678 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 679 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 680 else: 681 fatal("Don't know how to connect these system together") 682 683 if dumpfile: 684 self.etherdump = EtherDump(file=dumpfile) 685 self.etherlink.dump = Parent.etherdump 686 687 return self 688 689 690def makeDistRoot(testSystem, 691 rank, 692 size, 693 server_name, 694 server_port, 695 sync_repeat, 696 sync_start, 697 linkspeed, 698 linkdelay, 699 dumpfile): 700 self = Root(full_system = True) 701 self.testsys = testSystem 702 703 self.etherlink = DistEtherLink(speed = linkspeed, 704 delay = linkdelay, 705 dist_rank = rank, 706 dist_size = size, 707 server_name = server_name, 708 server_port = server_port, 709 sync_start = sync_start, 710 sync_repeat = sync_repeat) 711 712 if hasattr(testSystem, 'realview'): 713 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 714 elif hasattr(testSystem, 'tsunami'): 715 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 716 else: 717 fatal("Don't know how to connect DistEtherLink to this system") 718 719 if dumpfile: 720 self.etherdump = EtherDump(file=dumpfile) 721 self.etherlink.dump = Parent.etherdump 722 723 return self 724