FSConfig.py revision 13015:9e48c6a83b85
1# Copyright (c) 2010-2012, 2015-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 14# Copyright (c) 2006-2008 The Regents of The University of Michigan 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Kevin Lim 41 42from __future__ import print_function 43 44from m5.objects import * 45from Benchmarks import * 46from m5.util import * 47from common import PlatformConfig 48 49# Populate to reflect supported os types per target ISA 50os_types = { 'alpha' : [ 'linux' ], 51 'mips' : [ 'linux' ], 52 'sparc' : [ 'linux' ], 53 'x86' : [ 'linux' ], 54 'arm' : [ 'linux', 55 'android-gingerbread', 56 'android-ics', 57 'android-jellybean', 58 'android-kitkat', 59 'android-nougat', ], 60 } 61 62class CowIdeDisk(IdeDisk): 63 image = CowDiskImage(child=RawDiskImage(read_only=True), 64 read_only=False) 65 66 def childImage(self, ci): 67 self.image.child.image_file = ci 68 69class MemBus(SystemXBar): 70 badaddr_responder = BadAddr() 71 default = Self.badaddr_responder.pio 72 73def fillInCmdline(mdesc, template, **kwargs): 74 kwargs.setdefault('disk', mdesc.disk()) 75 kwargs.setdefault('rootdev', mdesc.rootdev()) 76 kwargs.setdefault('mem', mdesc.mem()) 77 kwargs.setdefault('script', mdesc.script()) 78 return template % kwargs 79 80def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 81 82 class BaseTsunami(Tsunami): 83 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 84 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 85 pci_func=0, pci_dev=0, pci_bus=0) 86 87 self = LinuxAlphaSystem() 88 if not mdesc: 89 # generic system 90 mdesc = SysConfig() 91 self.readfile = mdesc.script() 92 93 self.tsunami = BaseTsunami() 94 95 # Create the io bus to connect all device ports 96 self.iobus = IOXBar() 97 self.tsunami.attachIO(self.iobus) 98 99 self.tsunami.ide.pio = self.iobus.master 100 101 self.tsunami.ethernet.pio = self.iobus.master 102 103 if ruby: 104 # Store the dma devices for later connection to dma ruby ports. 105 # Append an underscore to dma_ports to avoid the SimObjectVector check. 106 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 107 else: 108 self.membus = MemBus() 109 110 # By default the bridge responds to all addresses above the I/O 111 # base address (including the PCI config space) 112 IO_address_space_base = 0x80000000000 113 self.bridge = Bridge(delay='50ns', 114 ranges = [AddrRange(IO_address_space_base, Addr.max)]) 115 self.bridge.master = self.iobus.slave 116 self.bridge.slave = self.membus.master 117 118 self.tsunami.ide.dma = self.iobus.slave 119 self.tsunami.ethernet.dma = self.iobus.slave 120 121 self.system_port = self.membus.slave 122 123 self.mem_ranges = [AddrRange(mdesc.mem())] 124 self.disk0 = CowIdeDisk(driveID='master') 125 self.disk2 = CowIdeDisk(driveID='master') 126 self.disk0.childImage(mdesc.disk()) 127 self.disk2.childImage(disk('linux-bigswap2.img')) 128 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 129 read_only = True)) 130 self.intrctrl = IntrControl() 131 self.mem_mode = mem_mode 132 self.terminal = Terminal() 133 self.kernel = binary('vmlinux') 134 self.pal = binary('ts_osfpal') 135 self.console = binary('console') 136 if not cmdline: 137 cmdline = 'root=/dev/hda1 console=ttyS0' 138 self.boot_osflags = fillInCmdline(mdesc, cmdline) 139 140 return self 141 142def makeSparcSystem(mem_mode, mdesc=None, cmdline=None): 143 # Constants from iob.cc and uart8250.cc 144 iob_man_addr = 0x9800000000 145 uart_pio_size = 8 146 147 class CowMmDisk(MmDisk): 148 image = CowDiskImage(child=RawDiskImage(read_only=True), 149 read_only=False) 150 151 def childImage(self, ci): 152 self.image.child.image_file = ci 153 154 self = SparcSystem() 155 if not mdesc: 156 # generic system 157 mdesc = SysConfig() 158 self.readfile = mdesc.script() 159 self.iobus = IOXBar() 160 self.membus = MemBus() 161 self.bridge = Bridge(delay='50ns') 162 self.t1000 = T1000() 163 self.t1000.attachOnChipIO(self.membus) 164 self.t1000.attachIO(self.iobus) 165 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 166 AddrRange(Addr('2GB'), size ='256MB')] 167 self.bridge.master = self.iobus.slave 168 self.bridge.slave = self.membus.master 169 self.rom.port = self.membus.master 170 self.nvram.port = self.membus.master 171 self.hypervisor_desc.port = self.membus.master 172 self.partition_desc.port = self.membus.master 173 self.intrctrl = IntrControl() 174 self.disk0 = CowMmDisk() 175 self.disk0.childImage(mdesc.disk()) 176 self.disk0.pio = self.iobus.master 177 178 # The puart0 and hvuart are placed on the IO bus, so create ranges 179 # for them. The remaining IO range is rather fragmented, so poke 180 # holes for the iob and partition descriptors etc. 181 self.bridge.ranges = \ 182 [ 183 AddrRange(self.t1000.puart0.pio_addr, 184 self.t1000.puart0.pio_addr + uart_pio_size - 1), 185 AddrRange(self.disk0.pio_addr, 186 self.t1000.fake_jbi.pio_addr + 187 self.t1000.fake_jbi.pio_size - 1), 188 AddrRange(self.t1000.fake_clk.pio_addr, 189 iob_man_addr - 1), 190 AddrRange(self.t1000.fake_l2_1.pio_addr, 191 self.t1000.fake_ssi.pio_addr + 192 self.t1000.fake_ssi.pio_size - 1), 193 AddrRange(self.t1000.hvuart.pio_addr, 194 self.t1000.hvuart.pio_addr + uart_pio_size - 1) 195 ] 196 self.reset_bin = binary('reset_new.bin') 197 self.hypervisor_bin = binary('q_new.bin') 198 self.openboot_bin = binary('openboot_new.bin') 199 self.nvram_bin = binary('nvram1') 200 self.hypervisor_desc_bin = binary('1up-hv.bin') 201 self.partition_desc_bin = binary('1up-md.bin') 202 203 self.system_port = self.membus.slave 204 205 return self 206 207def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 208 dtb_filename=None, bare_metal=False, cmdline=None, 209 external_memory="", ruby=False, security=False, 210 ignore_dtb=False): 211 assert machine_type 212 213 default_dtbs = { 214 "RealViewEB": None, 215 "RealViewPBX": None, 216 "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus, 217 "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", 218 } 219 220 default_kernels = { 221 "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8", 222 "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8", 223 "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", 224 "VExpress_EMM64": "vmlinux.aarch64.20140821", 225 } 226 227 pci_devices = [] 228 229 if bare_metal: 230 self = ArmSystem() 231 else: 232 self = LinuxArmSystem() 233 234 if not mdesc: 235 # generic system 236 mdesc = SysConfig() 237 238 self.readfile = mdesc.script() 239 self.iobus = IOXBar() 240 if not ruby: 241 self.bridge = Bridge(delay='50ns') 242 self.bridge.master = self.iobus.slave 243 self.membus = MemBus() 244 self.membus.badaddr_responder.warn_access = "warn" 245 self.bridge.slave = self.membus.master 246 247 self.mem_mode = mem_mode 248 249 platform_class = PlatformConfig.get(machine_type) 250 # Resolve the real platform name, the original machine_type 251 # variable might have been an alias. 252 machine_type = platform_class.__name__ 253 self.realview = platform_class() 254 255 if not dtb_filename and not (bare_metal or ignore_dtb): 256 try: 257 dtb_filename = default_dtbs[machine_type] 258 except KeyError: 259 fatal("No DTB specified and no default DTB known for '%s'" % \ 260 machine_type) 261 262 if isinstance(self.realview, VExpress_EMM64): 263 if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 264 print("Selected 64-bit ARM architecture, updating default " 265 "disk image...") 266 mdesc.diskname = 'linaro-minimal-aarch64.img' 267 268 269 # Attach any PCI devices this platform supports 270 self.realview.attachPciDevices() 271 272 self.cf0 = CowIdeDisk(driveID='master') 273 self.cf0.childImage(mdesc.disk()) 274 # Old platforms have a built-in IDE or CF controller. Default to 275 # the IDE controller if both exist. New platforms expect the 276 # storage controller to be added from the config script. 277 if hasattr(self.realview, "ide"): 278 self.realview.ide.disks = [self.cf0] 279 elif hasattr(self.realview, "cf_ctrl"): 280 self.realview.cf_ctrl.disks = [self.cf0] 281 else: 282 self.pci_ide = IdeController(disks=[self.cf0]) 283 pci_devices.append(self.pci_ide) 284 285 self.mem_ranges = [] 286 size_remain = long(Addr(mdesc.mem())) 287 for region in self.realview._mem_regions: 288 if size_remain > long(region[1]): 289 self.mem_ranges.append(AddrRange(region[0], size=region[1])) 290 size_remain = size_remain - long(region[1]) 291 else: 292 self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 293 size_remain = 0 294 break 295 warn("Memory size specified spans more than one region. Creating" \ 296 " another memory controller for that range.") 297 298 if size_remain > 0: 299 fatal("The currently selected ARM platforms doesn't support" \ 300 " the amount of DRAM you've selected. Please try" \ 301 " another platform") 302 303 self.have_security = security 304 305 if bare_metal: 306 # EOT character on UART will end the simulation 307 self.realview.uart[0].end_on_eot = True 308 else: 309 if machine_type in default_kernels: 310 self.kernel = binary(default_kernels[machine_type]) 311 312 if dtb_filename and not ignore_dtb: 313 self.dtb_filename = binary(dtb_filename) 314 315 self.machine_type = machine_type if machine_type in ArmMachineType.map \ 316 else "DTOnly" 317 318 # Ensure that writes to the UART actually go out early in the boot 319 if not cmdline: 320 cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 321 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 322 'mem=%(mem)s root=%(rootdev)s' 323 324 # When using external memory, gem5 writes the boot loader to nvmem 325 # and then SST will read from it, but SST can only get to nvmem from 326 # iobus, as gem5's membus is only used for initialization and 327 # SST doesn't use it. Attaching nvmem to iobus solves this issue. 328 # During initialization, system_port -> membus -> iobus -> nvmem. 329 if external_memory: 330 self.realview.setupBootLoader(self.iobus, self, binary) 331 elif ruby: 332 self.realview.setupBootLoader(None, self, binary) 333 else: 334 self.realview.setupBootLoader(self.membus, self, binary) 335 self.gic_cpu_addr = self.realview.gic.cpu_addr 336 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 337 338 # This check is for users who have previously put 'android' in 339 # the disk image filename to tell the config scripts to 340 # prepare the kernel with android-specific boot options. That 341 # behavior has been replaced with a more explicit option per 342 # the error message below. The disk can have any name now and 343 # doesn't need to include 'android' substring. 344 if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 345 if 'android' not in mdesc.os_type(): 346 fatal("It looks like you are trying to boot an Android " \ 347 "platform. To boot Android, you must specify " \ 348 "--os-type with an appropriate Android release on " \ 349 "the command line.") 350 351 # android-specific tweaks 352 if 'android' in mdesc.os_type(): 353 # generic tweaks 354 cmdline += " init=/init" 355 356 # release-specific tweaks 357 if 'kitkat' in mdesc.os_type(): 358 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 359 "android.bootanim=0 " 360 elif 'nougat' in mdesc.os_type(): 361 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 362 "android.bootanim=0 " + \ 363 "vmalloc=640MB " + \ 364 "android.early.fstab=/fstab.gem5 " + \ 365 "androidboot.selinux=permissive " + \ 366 "video=Virtual-1:1920x1080-16" 367 368 self.boot_osflags = fillInCmdline(mdesc, cmdline) 369 370 if external_memory: 371 # I/O traffic enters iobus 372 self.external_io = ExternalMaster(port_data="external_io", 373 port_type=external_memory) 374 self.external_io.port = self.iobus.slave 375 376 # Ensure iocache only receives traffic destined for (actual) memory. 377 self.iocache = ExternalSlave(port_data="iocache", 378 port_type=external_memory, 379 addr_ranges=self.mem_ranges) 380 self.iocache.port = self.iobus.master 381 382 # Let system_port get to nvmem and nothing else. 383 self.bridge.ranges = [self.realview.nvmem.range] 384 385 self.realview.attachOnChipIO(self.iobus) 386 # Attach off-chip devices 387 self.realview.attachIO(self.iobus) 388 elif ruby: 389 self._dma_ports = [ ] 390 self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports) 391 self.realview.attachIO(self.iobus, dma_ports=self._dma_ports) 392 else: 393 self.realview.attachOnChipIO(self.membus, self.bridge) 394 # Attach off-chip devices 395 self.realview.attachIO(self.iobus) 396 397 for dev_id, dev in enumerate(pci_devices): 398 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0) 399 self.realview.attachPciDevice( 400 dev, self.iobus, 401 dma_ports=self._dma_ports if ruby else None) 402 403 self.intrctrl = IntrControl() 404 self.terminal = Terminal() 405 self.vncserver = VncServer() 406 407 if not ruby: 408 self.system_port = self.membus.slave 409 410 if ruby: 411 if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1: 412 fatal("The MI_example protocol cannot implement Load/Store " 413 "Exclusive operations. Multicore ARM systems configured " 414 "with the MI_example protocol will not work properly.") 415 warn("You are trying to use Ruby on ARM, which is not working " 416 "properly yet.") 417 418 return self 419 420 421def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 422 class BaseMalta(Malta): 423 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 424 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 425 pci_func=0, pci_dev=0, pci_bus=0) 426 427 self = LinuxMipsSystem() 428 if not mdesc: 429 # generic system 430 mdesc = SysConfig() 431 self.readfile = mdesc.script() 432 self.iobus = IOXBar() 433 self.membus = MemBus() 434 self.bridge = Bridge(delay='50ns') 435 self.mem_ranges = [AddrRange('1GB')] 436 self.bridge.master = self.iobus.slave 437 self.bridge.slave = self.membus.master 438 self.disk0 = CowIdeDisk(driveID='master') 439 self.disk2 = CowIdeDisk(driveID='master') 440 self.disk0.childImage(mdesc.disk()) 441 self.disk2.childImage(disk('linux-bigswap2.img')) 442 self.malta = BaseMalta() 443 self.malta.attachIO(self.iobus) 444 self.malta.ide.pio = self.iobus.master 445 self.malta.ide.dma = self.iobus.slave 446 self.malta.ethernet.pio = self.iobus.master 447 self.malta.ethernet.dma = self.iobus.slave 448 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 449 read_only = True)) 450 self.intrctrl = IntrControl() 451 self.mem_mode = mem_mode 452 self.terminal = Terminal() 453 self.kernel = binary('mips/vmlinux') 454 self.console = binary('mips/console') 455 if not cmdline: 456 cmdline = 'root=/dev/hda1 console=ttyS0' 457 self.boot_osflags = fillInCmdline(mdesc, cmdline) 458 459 self.system_port = self.membus.slave 460 461 return self 462 463def x86IOAddress(port): 464 IO_address_space_base = 0x8000000000000000 465 return IO_address_space_base + port 466 467def connectX86ClassicSystem(x86_sys, numCPUs): 468 # Constants similar to x86_traits.hh 469 IO_address_space_base = 0x8000000000000000 470 pci_config_address_space_base = 0xc000000000000000 471 interrupts_address_space_base = 0xa000000000000000 472 APIC_range_size = 1 << 12; 473 474 x86_sys.membus = MemBus() 475 476 # North Bridge 477 x86_sys.iobus = IOXBar() 478 x86_sys.bridge = Bridge(delay='50ns') 479 x86_sys.bridge.master = x86_sys.iobus.slave 480 x86_sys.bridge.slave = x86_sys.membus.master 481 # Allow the bridge to pass through: 482 # 1) kernel configured PCI device memory map address: address range 483 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 484 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 485 # 3) everything in the IO address range up to the local APIC, and 486 # 4) then the entire PCI address space and beyond. 487 x86_sys.bridge.ranges = \ 488 [ 489 AddrRange(0xC0000000, 0xFFFF0000), 490 AddrRange(IO_address_space_base, 491 interrupts_address_space_base - 1), 492 AddrRange(pci_config_address_space_base, 493 Addr.max) 494 ] 495 496 # Create a bridge from the IO bus to the memory bus to allow access to 497 # the local APIC (two pages) 498 x86_sys.apicbridge = Bridge(delay='50ns') 499 x86_sys.apicbridge.slave = x86_sys.iobus.master 500 x86_sys.apicbridge.master = x86_sys.membus.slave 501 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 502 interrupts_address_space_base + 503 numCPUs * APIC_range_size 504 - 1)] 505 506 # connect the io bus 507 x86_sys.pc.attachIO(x86_sys.iobus) 508 509 x86_sys.system_port = x86_sys.membus.slave 510 511def connectX86RubySystem(x86_sys): 512 # North Bridge 513 x86_sys.iobus = IOXBar() 514 515 # add the ide to the list of dma devices that later need to attach to 516 # dma controllers 517 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 518 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 519 520 521def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 522 if self == None: 523 self = X86System() 524 525 if not mdesc: 526 # generic system 527 mdesc = SysConfig() 528 self.readfile = mdesc.script() 529 530 self.mem_mode = mem_mode 531 532 # Physical memory 533 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 534 # for various devices. Hence, if the physical memory size is greater than 535 # 3GB, we need to split it into two parts. 536 excess_mem_size = \ 537 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 538 if excess_mem_size <= 0: 539 self.mem_ranges = [AddrRange(mdesc.mem())] 540 else: 541 warn("Physical memory size specified is %s which is greater than " \ 542 "3GB. Twice the number of memory controllers would be " \ 543 "created." % (mdesc.mem())) 544 545 self.mem_ranges = [AddrRange('3GB'), 546 AddrRange(Addr('4GB'), size = excess_mem_size)] 547 548 # Platform 549 self.pc = Pc() 550 551 # Create and connect the busses required by each memory system 552 if Ruby: 553 connectX86RubySystem(self) 554 else: 555 connectX86ClassicSystem(self, numCPUs) 556 557 self.intrctrl = IntrControl() 558 559 # Disks 560 disk0 = CowIdeDisk(driveID='master') 561 disk2 = CowIdeDisk(driveID='master') 562 disk0.childImage(mdesc.disk()) 563 disk2.childImage(disk('linux-bigswap2.img')) 564 self.pc.south_bridge.ide.disks = [disk0, disk2] 565 566 # Add in a Bios information structure. 567 structures = [X86SMBiosBiosInformation()] 568 self.smbios_table.structures = structures 569 570 # Set up the Intel MP table 571 base_entries = [] 572 ext_entries = [] 573 for i in xrange(numCPUs): 574 bp = X86IntelMPProcessor( 575 local_apic_id = i, 576 local_apic_version = 0x14, 577 enable = True, 578 bootstrap = (i == 0)) 579 base_entries.append(bp) 580 io_apic = X86IntelMPIOAPIC( 581 id = numCPUs, 582 version = 0x11, 583 enable = True, 584 address = 0xfec00000) 585 self.pc.south_bridge.io_apic.apic_id = io_apic.id 586 base_entries.append(io_apic) 587 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 588 # but linux kernel cannot config PCI device if it was not connected to PCI bus, 589 # so we fix PCI bus id to 0, and ISA bus id to 1. 590 pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ') 591 base_entries.append(pci_bus) 592 isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ') 593 base_entries.append(isa_bus) 594 connect_busses = X86IntelMPBusHierarchy(bus_id=1, 595 subtractive_decode=True, parent_bus=0) 596 ext_entries.append(connect_busses) 597 pci_dev4_inta = X86IntelMPIOIntAssignment( 598 interrupt_type = 'INT', 599 polarity = 'ConformPolarity', 600 trigger = 'ConformTrigger', 601 source_bus_id = 0, 602 source_bus_irq = 0 + (4 << 2), 603 dest_io_apic_id = io_apic.id, 604 dest_io_apic_intin = 16) 605 base_entries.append(pci_dev4_inta) 606 def assignISAInt(irq, apicPin): 607 assign_8259_to_apic = X86IntelMPIOIntAssignment( 608 interrupt_type = 'ExtInt', 609 polarity = 'ConformPolarity', 610 trigger = 'ConformTrigger', 611 source_bus_id = 1, 612 source_bus_irq = irq, 613 dest_io_apic_id = io_apic.id, 614 dest_io_apic_intin = 0) 615 base_entries.append(assign_8259_to_apic) 616 assign_to_apic = X86IntelMPIOIntAssignment( 617 interrupt_type = 'INT', 618 polarity = 'ConformPolarity', 619 trigger = 'ConformTrigger', 620 source_bus_id = 1, 621 source_bus_irq = irq, 622 dest_io_apic_id = io_apic.id, 623 dest_io_apic_intin = apicPin) 624 base_entries.append(assign_to_apic) 625 assignISAInt(0, 2) 626 assignISAInt(1, 1) 627 for i in range(3, 15): 628 assignISAInt(i, i) 629 self.intel_mp_table.base_entries = base_entries 630 self.intel_mp_table.ext_entries = ext_entries 631 632def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 633 cmdline=None): 634 self = LinuxX86System() 635 636 # Build up the x86 system and then specialize it for Linux 637 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 638 639 # We assume below that there's at least 1MB of memory. We'll require 2 640 # just to avoid corner cases. 641 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 642 assert(phys_mem_size >= 0x200000) 643 assert(len(self.mem_ranges) <= 2) 644 645 entries = \ 646 [ 647 # Mark the first megabyte of memory as reserved 648 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 649 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 650 # Mark the rest of physical memory as available 651 X86E820Entry(addr = 0x100000, 652 size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 653 range_type = 1), 654 ] 655 656 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 657 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 658 # specific range can pass though bridge to iobus. 659 if len(self.mem_ranges) == 1: 660 entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 661 size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 662 range_type=2)) 663 664 # Reserve the last 16kB of the 32-bit address space for the m5op interface 665 entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 666 667 # In case the physical memory is greater than 3GB, we split it into two 668 # parts and add a separate e820 entry for the second part. This entry 669 # starts at 0x100000000, which is the first address after the space 670 # reserved for devices. 671 if len(self.mem_ranges) == 2: 672 entries.append(X86E820Entry(addr = 0x100000000, 673 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 674 675 self.e820_table.entries = entries 676 677 # Command line 678 if not cmdline: 679 cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 680 self.boot_osflags = fillInCmdline(mdesc, cmdline) 681 self.kernel = binary('x86_64-vmlinux-2.6.22.9') 682 return self 683 684 685def makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 686 self = Root(full_system = full_system) 687 self.testsys = testSystem 688 self.drivesys = driveSystem 689 self.etherlink = EtherLink() 690 691 if hasattr(testSystem, 'realview'): 692 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 693 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 694 elif hasattr(testSystem, 'tsunami'): 695 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 696 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 697 else: 698 fatal("Don't know how to connect these system together") 699 700 if dumpfile: 701 self.etherdump = EtherDump(file=dumpfile) 702 self.etherlink.dump = Parent.etherdump 703 704 return self 705 706 707def makeDistRoot(testSystem, 708 rank, 709 size, 710 server_name, 711 server_port, 712 sync_repeat, 713 sync_start, 714 linkspeed, 715 linkdelay, 716 dumpfile): 717 self = Root(full_system = True) 718 self.testsys = testSystem 719 720 self.etherlink = DistEtherLink(speed = linkspeed, 721 delay = linkdelay, 722 dist_rank = rank, 723 dist_size = size, 724 server_name = server_name, 725 server_port = server_port, 726 sync_start = sync_start, 727 sync_repeat = sync_repeat) 728 729 if hasattr(testSystem, 'realview'): 730 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 731 elif hasattr(testSystem, 'tsunami'): 732 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 733 else: 734 fatal("Don't know how to connect DistEtherLink to this system") 735 736 if dumpfile: 737 self.etherdump = EtherDump(file=dumpfile) 738 self.etherlink.dump = Parent.etherdump 739 740 return self 741