FSConfig.py revision 12079:a5cc6df83fcf
1# Copyright (c) 2010-2012, 2015-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 14# Copyright (c) 2006-2008 The Regents of The University of Michigan 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Kevin Lim 41 42from m5.objects import * 43from Benchmarks import * 44from m5.util import * 45from common import PlatformConfig 46 47# Populate to reflect supported os types per target ISA 48os_types = { 'alpha' : [ 'linux' ], 49 'mips' : [ 'linux' ], 50 'sparc' : [ 'linux' ], 51 'x86' : [ 'linux' ], 52 'arm' : [ 'linux', 53 'android-gingerbread', 54 'android-ics', 55 'android-jellybean', 56 'android-kitkat', 57 'android-nougat', ], 58 } 59 60class CowIdeDisk(IdeDisk): 61 image = CowDiskImage(child=RawDiskImage(read_only=True), 62 read_only=False) 63 64 def childImage(self, ci): 65 self.image.child.image_file = ci 66 67class MemBus(SystemXBar): 68 badaddr_responder = BadAddr() 69 default = Self.badaddr_responder.pio 70 71def fillInCmdline(mdesc, template, **kwargs): 72 kwargs.setdefault('disk', mdesc.disk()) 73 kwargs.setdefault('rootdev', mdesc.rootdev()) 74 kwargs.setdefault('mem', mdesc.mem()) 75 kwargs.setdefault('script', mdesc.script()) 76 return template % kwargs 77 78def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 79 80 class BaseTsunami(Tsunami): 81 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 82 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 83 pci_func=0, pci_dev=0, pci_bus=0) 84 85 self = LinuxAlphaSystem() 86 if not mdesc: 87 # generic system 88 mdesc = SysConfig() 89 self.readfile = mdesc.script() 90 91 self.tsunami = BaseTsunami() 92 93 # Create the io bus to connect all device ports 94 self.iobus = IOXBar() 95 self.tsunami.attachIO(self.iobus) 96 97 self.tsunami.ide.pio = self.iobus.master 98 99 self.tsunami.ethernet.pio = self.iobus.master 100 101 if ruby: 102 # Store the dma devices for later connection to dma ruby ports. 103 # Append an underscore to dma_ports to avoid the SimObjectVector check. 104 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 105 else: 106 self.membus = MemBus() 107 108 # By default the bridge responds to all addresses above the I/O 109 # base address (including the PCI config space) 110 IO_address_space_base = 0x80000000000 111 self.bridge = Bridge(delay='50ns', 112 ranges = [AddrRange(IO_address_space_base, Addr.max)]) 113 self.bridge.master = self.iobus.slave 114 self.bridge.slave = self.membus.master 115 116 self.tsunami.ide.dma = self.iobus.slave 117 self.tsunami.ethernet.dma = self.iobus.slave 118 119 self.system_port = self.membus.slave 120 121 self.mem_ranges = [AddrRange(mdesc.mem())] 122 self.disk0 = CowIdeDisk(driveID='master') 123 self.disk2 = CowIdeDisk(driveID='master') 124 self.disk0.childImage(mdesc.disk()) 125 self.disk2.childImage(disk('linux-bigswap2.img')) 126 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 127 read_only = True)) 128 self.intrctrl = IntrControl() 129 self.mem_mode = mem_mode 130 self.terminal = Terminal() 131 self.kernel = binary('vmlinux') 132 self.pal = binary('ts_osfpal') 133 self.console = binary('console') 134 if not cmdline: 135 cmdline = 'root=/dev/hda1 console=ttyS0' 136 self.boot_osflags = fillInCmdline(mdesc, cmdline) 137 138 return self 139 140def makeSparcSystem(mem_mode, mdesc=None, cmdline=None): 141 # Constants from iob.cc and uart8250.cc 142 iob_man_addr = 0x9800000000 143 uart_pio_size = 8 144 145 class CowMmDisk(MmDisk): 146 image = CowDiskImage(child=RawDiskImage(read_only=True), 147 read_only=False) 148 149 def childImage(self, ci): 150 self.image.child.image_file = ci 151 152 self = SparcSystem() 153 if not mdesc: 154 # generic system 155 mdesc = SysConfig() 156 self.readfile = mdesc.script() 157 self.iobus = IOXBar() 158 self.membus = MemBus() 159 self.bridge = Bridge(delay='50ns') 160 self.t1000 = T1000() 161 self.t1000.attachOnChipIO(self.membus) 162 self.t1000.attachIO(self.iobus) 163 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 164 AddrRange(Addr('2GB'), size ='256MB')] 165 self.bridge.master = self.iobus.slave 166 self.bridge.slave = self.membus.master 167 self.rom.port = self.membus.master 168 self.nvram.port = self.membus.master 169 self.hypervisor_desc.port = self.membus.master 170 self.partition_desc.port = self.membus.master 171 self.intrctrl = IntrControl() 172 self.disk0 = CowMmDisk() 173 self.disk0.childImage(mdesc.disk()) 174 self.disk0.pio = self.iobus.master 175 176 # The puart0 and hvuart are placed on the IO bus, so create ranges 177 # for them. The remaining IO range is rather fragmented, so poke 178 # holes for the iob and partition descriptors etc. 179 self.bridge.ranges = \ 180 [ 181 AddrRange(self.t1000.puart0.pio_addr, 182 self.t1000.puart0.pio_addr + uart_pio_size - 1), 183 AddrRange(self.disk0.pio_addr, 184 self.t1000.fake_jbi.pio_addr + 185 self.t1000.fake_jbi.pio_size - 1), 186 AddrRange(self.t1000.fake_clk.pio_addr, 187 iob_man_addr - 1), 188 AddrRange(self.t1000.fake_l2_1.pio_addr, 189 self.t1000.fake_ssi.pio_addr + 190 self.t1000.fake_ssi.pio_size - 1), 191 AddrRange(self.t1000.hvuart.pio_addr, 192 self.t1000.hvuart.pio_addr + uart_pio_size - 1) 193 ] 194 self.reset_bin = binary('reset_new.bin') 195 self.hypervisor_bin = binary('q_new.bin') 196 self.openboot_bin = binary('openboot_new.bin') 197 self.nvram_bin = binary('nvram1') 198 self.hypervisor_desc_bin = binary('1up-hv.bin') 199 self.partition_desc_bin = binary('1up-md.bin') 200 201 self.system_port = self.membus.slave 202 203 return self 204 205def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 206 dtb_filename=None, bare_metal=False, cmdline=None, 207 external_memory="", ruby=False, security=False): 208 assert machine_type 209 210 default_dtbs = { 211 "RealViewEB": None, 212 "RealViewPBX": None, 213 "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus, 214 "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", 215 } 216 217 default_kernels = { 218 "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8", 219 "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8", 220 "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", 221 "VExpress_EMM64": "vmlinux.aarch64.20140821", 222 } 223 224 pci_devices = [] 225 226 if bare_metal: 227 self = ArmSystem() 228 else: 229 self = LinuxArmSystem() 230 231 if not mdesc: 232 # generic system 233 mdesc = SysConfig() 234 235 self.readfile = mdesc.script() 236 self.iobus = IOXBar() 237 if not ruby: 238 self.bridge = Bridge(delay='50ns') 239 self.bridge.master = self.iobus.slave 240 self.membus = MemBus() 241 self.membus.badaddr_responder.warn_access = "warn" 242 self.bridge.slave = self.membus.master 243 244 self.mem_mode = mem_mode 245 246 platform_class = PlatformConfig.get(machine_type) 247 # Resolve the real platform name, the original machine_type 248 # variable might have been an alias. 249 machine_type = platform_class.__name__ 250 self.realview = platform_class() 251 252 if not dtb_filename and not bare_metal: 253 try: 254 dtb_filename = default_dtbs[machine_type] 255 except KeyError: 256 fatal("No DTB specified and no default DTB known for '%s'" % \ 257 machine_type) 258 259 if isinstance(self.realview, VExpress_EMM64): 260 if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 261 print "Selected 64-bit ARM architecture, updating default disk image..." 262 mdesc.diskname = 'linaro-minimal-aarch64.img' 263 264 265 # Attach any PCI devices this platform supports 266 self.realview.attachPciDevices() 267 268 self.cf0 = CowIdeDisk(driveID='master') 269 self.cf0.childImage(mdesc.disk()) 270 # Old platforms have a built-in IDE or CF controller. Default to 271 # the IDE controller if both exist. New platforms expect the 272 # storage controller to be added from the config script. 273 if hasattr(self.realview, "ide"): 274 self.realview.ide.disks = [self.cf0] 275 elif hasattr(self.realview, "cf_ctrl"): 276 self.realview.cf_ctrl.disks = [self.cf0] 277 else: 278 self.pci_ide = IdeController(disks=[self.cf0]) 279 pci_devices.append(self.pci_ide) 280 281 self.mem_ranges = [] 282 size_remain = long(Addr(mdesc.mem())) 283 for region in self.realview._mem_regions: 284 if size_remain > long(region[1]): 285 self.mem_ranges.append(AddrRange(region[0], size=region[1])) 286 size_remain = size_remain - long(region[1]) 287 else: 288 self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 289 size_remain = 0 290 break 291 warn("Memory size specified spans more than one region. Creating" \ 292 " another memory controller for that range.") 293 294 if size_remain > 0: 295 fatal("The currently selected ARM platforms doesn't support" \ 296 " the amount of DRAM you've selected. Please try" \ 297 " another platform") 298 299 self.have_security = security 300 301 if bare_metal: 302 # EOT character on UART will end the simulation 303 self.realview.uart.end_on_eot = True 304 else: 305 if machine_type in default_kernels: 306 self.kernel = binary(default_kernels[machine_type]) 307 308 if dtb_filename: 309 self.dtb_filename = binary(dtb_filename) 310 311 self.machine_type = machine_type if machine_type in ArmMachineType.map \ 312 else "DTOnly" 313 314 # Ensure that writes to the UART actually go out early in the boot 315 if not cmdline: 316 cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 317 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 318 'mem=%(mem)s root=%(rootdev)s' 319 320 # When using external memory, gem5 writes the boot loader to nvmem 321 # and then SST will read from it, but SST can only get to nvmem from 322 # iobus, as gem5's membus is only used for initialization and 323 # SST doesn't use it. Attaching nvmem to iobus solves this issue. 324 # During initialization, system_port -> membus -> iobus -> nvmem. 325 if external_memory or ruby: 326 self.realview.setupBootLoader(self.iobus, self, binary) 327 else: 328 self.realview.setupBootLoader(self.membus, self, binary) 329 self.gic_cpu_addr = self.realview.gic.cpu_addr 330 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 331 332 # This check is for users who have previously put 'android' in 333 # the disk image filename to tell the config scripts to 334 # prepare the kernel with android-specific boot options. That 335 # behavior has been replaced with a more explicit option per 336 # the error message below. The disk can have any name now and 337 # doesn't need to include 'android' substring. 338 if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 339 if 'android' not in mdesc.os_type(): 340 fatal("It looks like you are trying to boot an Android " \ 341 "platform. To boot Android, you must specify " \ 342 "--os-type with an appropriate Android release on " \ 343 "the command line.") 344 345 # android-specific tweaks 346 if 'android' in mdesc.os_type(): 347 # generic tweaks 348 cmdline += " init=/init" 349 350 # release-specific tweaks 351 if 'kitkat' in mdesc.os_type(): 352 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 353 "android.bootanim=0 " 354 elif 'nougat' in mdesc.os_type(): 355 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 356 "android.bootanim=0 " + \ 357 "vmalloc=640MB " + \ 358 "android.early.fstab=/fstab.gem5 " + \ 359 "androidboot.selinux=permissive " + \ 360 "video=Virtual-1:1920x1080-16" 361 362 self.boot_osflags = fillInCmdline(mdesc, cmdline) 363 364 if external_memory: 365 # I/O traffic enters iobus 366 self.external_io = ExternalMaster(port_data="external_io", 367 port_type=external_memory) 368 self.external_io.port = self.iobus.slave 369 370 # Ensure iocache only receives traffic destined for (actual) memory. 371 self.iocache = ExternalSlave(port_data="iocache", 372 port_type=external_memory, 373 addr_ranges=self.mem_ranges) 374 self.iocache.port = self.iobus.master 375 376 # Let system_port get to nvmem and nothing else. 377 self.bridge.ranges = [self.realview.nvmem.range] 378 379 self.realview.attachOnChipIO(self.iobus) 380 # Attach off-chip devices 381 self.realview.attachIO(self.iobus) 382 elif ruby: 383 self._dma_ports = [ ] 384 self.realview.attachOnChipIO(self.iobus, dma_ports=self._dma_ports) 385 # Force Ruby to treat the boot ROM as an IO device. 386 self.realview.nvmem.in_addr_map = False 387 self.realview.attachIO(self.iobus, dma_ports=self._dma_ports) 388 else: 389 self.realview.attachOnChipIO(self.membus, self.bridge) 390 # Attach off-chip devices 391 self.realview.attachIO(self.iobus) 392 393 for dev_id, dev in enumerate(pci_devices): 394 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0) 395 self.realview.attachPciDevice( 396 dev, self.iobus, 397 dma_ports=self._dma_ports if ruby else None) 398 399 self.intrctrl = IntrControl() 400 self.terminal = Terminal() 401 self.vncserver = VncServer() 402 403 if not ruby: 404 self.system_port = self.membus.slave 405 406 if ruby: 407 if buildEnv['PROTOCOL'] == 'MI_example' and num_cpus > 1: 408 fatal("The MI_example protocol cannot implement Load/Store " 409 "Exclusive operations. Multicore ARM systems configured " 410 "with the MI_example protocol will not work properly.") 411 warn("You are trying to use Ruby on ARM, which is not working " 412 "properly yet.") 413 414 return self 415 416 417def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 418 class BaseMalta(Malta): 419 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 420 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 421 pci_func=0, pci_dev=0, pci_bus=0) 422 423 self = LinuxMipsSystem() 424 if not mdesc: 425 # generic system 426 mdesc = SysConfig() 427 self.readfile = mdesc.script() 428 self.iobus = IOXBar() 429 self.membus = MemBus() 430 self.bridge = Bridge(delay='50ns') 431 self.mem_ranges = [AddrRange('1GB')] 432 self.bridge.master = self.iobus.slave 433 self.bridge.slave = self.membus.master 434 self.disk0 = CowIdeDisk(driveID='master') 435 self.disk2 = CowIdeDisk(driveID='master') 436 self.disk0.childImage(mdesc.disk()) 437 self.disk2.childImage(disk('linux-bigswap2.img')) 438 self.malta = BaseMalta() 439 self.malta.attachIO(self.iobus) 440 self.malta.ide.pio = self.iobus.master 441 self.malta.ide.dma = self.iobus.slave 442 self.malta.ethernet.pio = self.iobus.master 443 self.malta.ethernet.dma = self.iobus.slave 444 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 445 read_only = True)) 446 self.intrctrl = IntrControl() 447 self.mem_mode = mem_mode 448 self.terminal = Terminal() 449 self.kernel = binary('mips/vmlinux') 450 self.console = binary('mips/console') 451 if not cmdline: 452 cmdline = 'root=/dev/hda1 console=ttyS0' 453 self.boot_osflags = fillInCmdline(mdesc, cmdline) 454 455 self.system_port = self.membus.slave 456 457 return self 458 459def x86IOAddress(port): 460 IO_address_space_base = 0x8000000000000000 461 return IO_address_space_base + port 462 463def connectX86ClassicSystem(x86_sys, numCPUs): 464 # Constants similar to x86_traits.hh 465 IO_address_space_base = 0x8000000000000000 466 pci_config_address_space_base = 0xc000000000000000 467 interrupts_address_space_base = 0xa000000000000000 468 APIC_range_size = 1 << 12; 469 470 x86_sys.membus = MemBus() 471 472 # North Bridge 473 x86_sys.iobus = IOXBar() 474 x86_sys.bridge = Bridge(delay='50ns') 475 x86_sys.bridge.master = x86_sys.iobus.slave 476 x86_sys.bridge.slave = x86_sys.membus.master 477 # Allow the bridge to pass through: 478 # 1) kernel configured PCI device memory map address: address range 479 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 480 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 481 # 3) everything in the IO address range up to the local APIC, and 482 # 4) then the entire PCI address space and beyond. 483 x86_sys.bridge.ranges = \ 484 [ 485 AddrRange(0xC0000000, 0xFFFF0000), 486 AddrRange(IO_address_space_base, 487 interrupts_address_space_base - 1), 488 AddrRange(pci_config_address_space_base, 489 Addr.max) 490 ] 491 492 # Create a bridge from the IO bus to the memory bus to allow access to 493 # the local APIC (two pages) 494 x86_sys.apicbridge = Bridge(delay='50ns') 495 x86_sys.apicbridge.slave = x86_sys.iobus.master 496 x86_sys.apicbridge.master = x86_sys.membus.slave 497 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 498 interrupts_address_space_base + 499 numCPUs * APIC_range_size 500 - 1)] 501 502 # connect the io bus 503 x86_sys.pc.attachIO(x86_sys.iobus) 504 505 x86_sys.system_port = x86_sys.membus.slave 506 507def connectX86RubySystem(x86_sys): 508 # North Bridge 509 x86_sys.iobus = IOXBar() 510 511 # add the ide to the list of dma devices that later need to attach to 512 # dma controllers 513 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 514 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 515 516 517def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 518 if self == None: 519 self = X86System() 520 521 if not mdesc: 522 # generic system 523 mdesc = SysConfig() 524 self.readfile = mdesc.script() 525 526 self.mem_mode = mem_mode 527 528 # Physical memory 529 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 530 # for various devices. Hence, if the physical memory size is greater than 531 # 3GB, we need to split it into two parts. 532 excess_mem_size = \ 533 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 534 if excess_mem_size <= 0: 535 self.mem_ranges = [AddrRange(mdesc.mem())] 536 else: 537 warn("Physical memory size specified is %s which is greater than " \ 538 "3GB. Twice the number of memory controllers would be " \ 539 "created." % (mdesc.mem())) 540 541 self.mem_ranges = [AddrRange('3GB'), 542 AddrRange(Addr('4GB'), size = excess_mem_size)] 543 544 # Platform 545 self.pc = Pc() 546 547 # Create and connect the busses required by each memory system 548 if Ruby: 549 connectX86RubySystem(self) 550 else: 551 connectX86ClassicSystem(self, numCPUs) 552 553 self.intrctrl = IntrControl() 554 555 # Disks 556 disk0 = CowIdeDisk(driveID='master') 557 disk2 = CowIdeDisk(driveID='master') 558 disk0.childImage(mdesc.disk()) 559 disk2.childImage(disk('linux-bigswap2.img')) 560 self.pc.south_bridge.ide.disks = [disk0, disk2] 561 562 # Add in a Bios information structure. 563 structures = [X86SMBiosBiosInformation()] 564 self.smbios_table.structures = structures 565 566 # Set up the Intel MP table 567 base_entries = [] 568 ext_entries = [] 569 for i in xrange(numCPUs): 570 bp = X86IntelMPProcessor( 571 local_apic_id = i, 572 local_apic_version = 0x14, 573 enable = True, 574 bootstrap = (i == 0)) 575 base_entries.append(bp) 576 io_apic = X86IntelMPIOAPIC( 577 id = numCPUs, 578 version = 0x11, 579 enable = True, 580 address = 0xfec00000) 581 self.pc.south_bridge.io_apic.apic_id = io_apic.id 582 base_entries.append(io_apic) 583 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 584 # but linux kernel cannot config PCI device if it was not connected to PCI bus, 585 # so we fix PCI bus id to 0, and ISA bus id to 1. 586 pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ') 587 base_entries.append(pci_bus) 588 isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ') 589 base_entries.append(isa_bus) 590 connect_busses = X86IntelMPBusHierarchy(bus_id=1, 591 subtractive_decode=True, parent_bus=0) 592 ext_entries.append(connect_busses) 593 pci_dev4_inta = X86IntelMPIOIntAssignment( 594 interrupt_type = 'INT', 595 polarity = 'ConformPolarity', 596 trigger = 'ConformTrigger', 597 source_bus_id = 0, 598 source_bus_irq = 0 + (4 << 2), 599 dest_io_apic_id = io_apic.id, 600 dest_io_apic_intin = 16) 601 base_entries.append(pci_dev4_inta) 602 def assignISAInt(irq, apicPin): 603 assign_8259_to_apic = X86IntelMPIOIntAssignment( 604 interrupt_type = 'ExtInt', 605 polarity = 'ConformPolarity', 606 trigger = 'ConformTrigger', 607 source_bus_id = 1, 608 source_bus_irq = irq, 609 dest_io_apic_id = io_apic.id, 610 dest_io_apic_intin = 0) 611 base_entries.append(assign_8259_to_apic) 612 assign_to_apic = X86IntelMPIOIntAssignment( 613 interrupt_type = 'INT', 614 polarity = 'ConformPolarity', 615 trigger = 'ConformTrigger', 616 source_bus_id = 1, 617 source_bus_irq = irq, 618 dest_io_apic_id = io_apic.id, 619 dest_io_apic_intin = apicPin) 620 base_entries.append(assign_to_apic) 621 assignISAInt(0, 2) 622 assignISAInt(1, 1) 623 for i in range(3, 15): 624 assignISAInt(i, i) 625 self.intel_mp_table.base_entries = base_entries 626 self.intel_mp_table.ext_entries = ext_entries 627 628def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 629 cmdline=None): 630 self = LinuxX86System() 631 632 # Build up the x86 system and then specialize it for Linux 633 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 634 635 # We assume below that there's at least 1MB of memory. We'll require 2 636 # just to avoid corner cases. 637 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 638 assert(phys_mem_size >= 0x200000) 639 assert(len(self.mem_ranges) <= 2) 640 641 entries = \ 642 [ 643 # Mark the first megabyte of memory as reserved 644 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 645 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 646 # Mark the rest of physical memory as available 647 X86E820Entry(addr = 0x100000, 648 size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 649 range_type = 1), 650 ] 651 652 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 653 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 654 # specific range can pass though bridge to iobus. 655 if len(self.mem_ranges) == 1: 656 entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 657 size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 658 range_type=2)) 659 660 # Reserve the last 16kB of the 32-bit address space for the m5op interface 661 entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 662 663 # In case the physical memory is greater than 3GB, we split it into two 664 # parts and add a separate e820 entry for the second part. This entry 665 # starts at 0x100000000, which is the first address after the space 666 # reserved for devices. 667 if len(self.mem_ranges) == 2: 668 entries.append(X86E820Entry(addr = 0x100000000, 669 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 670 671 self.e820_table.entries = entries 672 673 # Command line 674 if not cmdline: 675 cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 676 self.boot_osflags = fillInCmdline(mdesc, cmdline) 677 self.kernel = binary('x86_64-vmlinux-2.6.22.9') 678 return self 679 680 681def makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 682 self = Root(full_system = full_system) 683 self.testsys = testSystem 684 self.drivesys = driveSystem 685 self.etherlink = EtherLink() 686 687 if hasattr(testSystem, 'realview'): 688 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 689 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 690 elif hasattr(testSystem, 'tsunami'): 691 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 692 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 693 else: 694 fatal("Don't know how to connect these system together") 695 696 if dumpfile: 697 self.etherdump = EtherDump(file=dumpfile) 698 self.etherlink.dump = Parent.etherdump 699 700 return self 701 702 703def makeDistRoot(testSystem, 704 rank, 705 size, 706 server_name, 707 server_port, 708 sync_repeat, 709 sync_start, 710 linkspeed, 711 linkdelay, 712 dumpfile): 713 self = Root(full_system = True) 714 self.testsys = testSystem 715 716 self.etherlink = DistEtherLink(speed = linkspeed, 717 delay = linkdelay, 718 dist_rank = rank, 719 dist_size = size, 720 server_name = server_name, 721 server_port = server_port, 722 sync_start = sync_start, 723 sync_repeat = sync_repeat) 724 725 if hasattr(testSystem, 'realview'): 726 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 727 elif hasattr(testSystem, 'tsunami'): 728 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 729 else: 730 fatal("Don't know how to connect DistEtherLink to this system") 731 732 if dumpfile: 733 self.etherdump = EtherDump(file=dumpfile) 734 self.etherlink.dump = Parent.etherdump 735 736 return self 737