FSConfig.py revision 11481:fc247b9c42b6
1# Copyright (c) 2010-2012, 2015 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 14# Copyright (c) 2006-2008 The Regents of The University of Michigan 15# All rights reserved. 16# 17# Redistribution and use in source and binary forms, with or without 18# modification, are permitted provided that the following conditions are 19# met: redistributions of source code must retain the above copyright 20# notice, this list of conditions and the following disclaimer; 21# redistributions in binary form must reproduce the above copyright 22# notice, this list of conditions and the following disclaimer in the 23# documentation and/or other materials provided with the distribution; 24# neither the name of the copyright holders nor the names of its 25# contributors may be used to endorse or promote products derived from 26# this software without specific prior written permission. 27# 28# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39# 40# Authors: Kevin Lim 41 42from m5.objects import * 43from Benchmarks import * 44from m5.util import * 45import PlatformConfig 46 47# Populate to reflect supported os types per target ISA 48os_types = { 'alpha' : [ 'linux' ], 49 'mips' : [ 'linux' ], 50 'sparc' : [ 'linux' ], 51 'x86' : [ 'linux' ], 52 'arm' : [ 'linux', 53 'android-gingerbread', 54 'android-ics', 55 'android-jellybean', 56 'android-kitkat' ], 57 } 58 59class CowIdeDisk(IdeDisk): 60 image = CowDiskImage(child=RawDiskImage(read_only=True), 61 read_only=False) 62 63 def childImage(self, ci): 64 self.image.child.image_file = ci 65 66class MemBus(SystemXBar): 67 badaddr_responder = BadAddr() 68 default = Self.badaddr_responder.pio 69 70def fillInCmdline(mdesc, template, **kwargs): 71 kwargs.setdefault('disk', mdesc.disk()) 72 kwargs.setdefault('rootdev', mdesc.rootdev()) 73 kwargs.setdefault('mem', mdesc.mem()) 74 kwargs.setdefault('script', mdesc.script()) 75 return template % kwargs 76 77def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None): 78 79 class BaseTsunami(Tsunami): 80 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 81 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 82 pci_func=0, pci_dev=0, pci_bus=0) 83 84 self = LinuxAlphaSystem() 85 if not mdesc: 86 # generic system 87 mdesc = SysConfig() 88 self.readfile = mdesc.script() 89 90 self.tsunami = BaseTsunami() 91 92 # Create the io bus to connect all device ports 93 self.iobus = IOXBar() 94 self.tsunami.attachIO(self.iobus) 95 96 self.tsunami.ide.pio = self.iobus.master 97 98 self.tsunami.ethernet.pio = self.iobus.master 99 100 if ruby: 101 # Store the dma devices for later connection to dma ruby ports. 102 # Append an underscore to dma_ports to avoid the SimObjectVector check. 103 self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 104 else: 105 self.membus = MemBus() 106 107 # By default the bridge responds to all addresses above the I/O 108 # base address (including the PCI config space) 109 IO_address_space_base = 0x80000000000 110 self.bridge = Bridge(delay='50ns', 111 ranges = [AddrRange(IO_address_space_base, Addr.max)]) 112 self.bridge.master = self.iobus.slave 113 self.bridge.slave = self.membus.master 114 115 self.tsunami.ide.dma = self.iobus.slave 116 self.tsunami.ethernet.dma = self.iobus.slave 117 118 self.system_port = self.membus.slave 119 120 self.mem_ranges = [AddrRange(mdesc.mem())] 121 self.disk0 = CowIdeDisk(driveID='master') 122 self.disk2 = CowIdeDisk(driveID='master') 123 self.disk0.childImage(mdesc.disk()) 124 self.disk2.childImage(disk('linux-bigswap2.img')) 125 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 126 read_only = True)) 127 self.intrctrl = IntrControl() 128 self.mem_mode = mem_mode 129 self.terminal = Terminal() 130 self.kernel = binary('vmlinux') 131 self.pal = binary('ts_osfpal') 132 self.console = binary('console') 133 if not cmdline: 134 cmdline = 'root=/dev/hda1 console=ttyS0' 135 self.boot_osflags = fillInCmdline(mdesc, cmdline) 136 137 return self 138 139def makeSparcSystem(mem_mode, mdesc=None, cmdline=None): 140 # Constants from iob.cc and uart8250.cc 141 iob_man_addr = 0x9800000000 142 uart_pio_size = 8 143 144 class CowMmDisk(MmDisk): 145 image = CowDiskImage(child=RawDiskImage(read_only=True), 146 read_only=False) 147 148 def childImage(self, ci): 149 self.image.child.image_file = ci 150 151 self = SparcSystem() 152 if not mdesc: 153 # generic system 154 mdesc = SysConfig() 155 self.readfile = mdesc.script() 156 self.iobus = IOXBar() 157 self.membus = MemBus() 158 self.bridge = Bridge(delay='50ns') 159 self.t1000 = T1000() 160 self.t1000.attachOnChipIO(self.membus) 161 self.t1000.attachIO(self.iobus) 162 self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 163 AddrRange(Addr('2GB'), size ='256MB')] 164 self.bridge.master = self.iobus.slave 165 self.bridge.slave = self.membus.master 166 self.rom.port = self.membus.master 167 self.nvram.port = self.membus.master 168 self.hypervisor_desc.port = self.membus.master 169 self.partition_desc.port = self.membus.master 170 self.intrctrl = IntrControl() 171 self.disk0 = CowMmDisk() 172 self.disk0.childImage(disk('disk.s10hw2')) 173 self.disk0.pio = self.iobus.master 174 175 # The puart0 and hvuart are placed on the IO bus, so create ranges 176 # for them. The remaining IO range is rather fragmented, so poke 177 # holes for the iob and partition descriptors etc. 178 self.bridge.ranges = \ 179 [ 180 AddrRange(self.t1000.puart0.pio_addr, 181 self.t1000.puart0.pio_addr + uart_pio_size - 1), 182 AddrRange(self.disk0.pio_addr, 183 self.t1000.fake_jbi.pio_addr + 184 self.t1000.fake_jbi.pio_size - 1), 185 AddrRange(self.t1000.fake_clk.pio_addr, 186 iob_man_addr - 1), 187 AddrRange(self.t1000.fake_l2_1.pio_addr, 188 self.t1000.fake_ssi.pio_addr + 189 self.t1000.fake_ssi.pio_size - 1), 190 AddrRange(self.t1000.hvuart.pio_addr, 191 self.t1000.hvuart.pio_addr + uart_pio_size - 1) 192 ] 193 self.reset_bin = binary('reset_new.bin') 194 self.hypervisor_bin = binary('q_new.bin') 195 self.openboot_bin = binary('openboot_new.bin') 196 self.nvram_bin = binary('nvram1') 197 self.hypervisor_desc_bin = binary('1up-hv.bin') 198 self.partition_desc_bin = binary('1up-md.bin') 199 200 self.system_port = self.membus.slave 201 202 return self 203 204def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None, 205 dtb_filename=None, bare_metal=False, cmdline=None, 206 external_memory=""): 207 assert machine_type 208 209 default_dtbs = { 210 "RealViewEB": None, 211 "RealViewPBX": None, 212 "VExpress_EMM": "vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb" % num_cpus, 213 "VExpress_EMM64": "vexpress.aarch64.20140821.dtb", 214 } 215 216 default_kernels = { 217 "RealViewEB": "vmlinux.arm.smp.fb.2.6.38.8", 218 "RealViewPBX": "vmlinux.arm.smp.fb.2.6.38.8", 219 "VExpress_EMM": "vmlinux.aarch32.ll_20131205.0-gem5", 220 "VExpress_EMM64": "vmlinux.aarch64.20140821", 221 } 222 223 pci_devices = [] 224 225 if bare_metal: 226 self = ArmSystem() 227 else: 228 self = LinuxArmSystem() 229 230 if not mdesc: 231 # generic system 232 mdesc = SysConfig() 233 234 self.readfile = mdesc.script() 235 self.iobus = IOXBar() 236 self.membus = MemBus() 237 self.membus.badaddr_responder.warn_access = "warn" 238 self.bridge = Bridge(delay='50ns') 239 self.bridge.master = self.iobus.slave 240 self.bridge.slave = self.membus.master 241 242 self.mem_mode = mem_mode 243 244 platform_class = PlatformConfig.get(machine_type) 245 # Resolve the real platform name, the original machine_type 246 # variable might have been an alias. 247 machine_type = platform_class.__name__ 248 self.realview = platform_class() 249 250 if not dtb_filename and not bare_metal: 251 try: 252 dtb_filename = default_dtbs[machine_type] 253 except KeyError: 254 fatal("No DTB specified and no default DTB known for '%s'" % \ 255 machine_type) 256 257 if isinstance(self.realview, VExpress_EMM64): 258 if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img': 259 print "Selected 64-bit ARM architecture, updating default disk image..." 260 mdesc.diskname = 'linaro-minimal-aarch64.img' 261 262 263 # Attach any PCI devices this platform supports 264 self.realview.attachPciDevices() 265 266 self.cf0 = CowIdeDisk(driveID='master') 267 self.cf0.childImage(mdesc.disk()) 268 # Old platforms have a built-in IDE or CF controller. Default to 269 # the IDE controller if both exist. New platforms expect the 270 # storage controller to be added from the config script. 271 if hasattr(self.realview, "ide"): 272 self.realview.ide.disks = [self.cf0] 273 elif hasattr(self.realview, "cf_ctrl"): 274 self.realview.cf_ctrl.disks = [self.cf0] 275 else: 276 self.pci_ide = IdeController(disks=[self.cf0]) 277 pci_devices.append(self.pci_ide) 278 279 self.mem_ranges = [] 280 size_remain = long(Addr(mdesc.mem())) 281 for region in self.realview._mem_regions: 282 if size_remain > long(region[1]): 283 self.mem_ranges.append(AddrRange(region[0], size=region[1])) 284 size_remain = size_remain - long(region[1]) 285 else: 286 self.mem_ranges.append(AddrRange(region[0], size=size_remain)) 287 size_remain = 0 288 break 289 warn("Memory size specified spans more than one region. Creating" \ 290 " another memory controller for that range.") 291 292 if size_remain > 0: 293 fatal("The currently selected ARM platforms doesn't support" \ 294 " the amount of DRAM you've selected. Please try" \ 295 " another platform") 296 297 if bare_metal: 298 # EOT character on UART will end the simulation 299 self.realview.uart.end_on_eot = True 300 else: 301 if machine_type in default_kernels: 302 self.kernel = binary(default_kernels[machine_type]) 303 304 if dtb_filename: 305 self.dtb_filename = binary(dtb_filename) 306 307 self.machine_type = machine_type if machine_type in ArmMachineType.map \ 308 else "DTOnly" 309 310 # Ensure that writes to the UART actually go out early in the boot 311 if not cmdline: 312 cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 313 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 314 'mem=%(mem)s root=%(rootdev)s' 315 316 # When using external memory, gem5 writes the boot loader to nvmem 317 # and then SST will read from it, but SST can only get to nvmem from 318 # iobus, as gem5's membus is only used for initialization and 319 # SST doesn't use it. Attaching nvmem to iobus solves this issue. 320 # During initialization, system_port -> membus -> iobus -> nvmem. 321 if external_memory: 322 self.realview.setupBootLoader(self.iobus, self, binary) 323 else: 324 self.realview.setupBootLoader(self.membus, self, binary) 325 self.gic_cpu_addr = self.realview.gic.cpu_addr 326 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 327 328 # This check is for users who have previously put 'android' in 329 # the disk image filename to tell the config scripts to 330 # prepare the kernel with android-specific boot options. That 331 # behavior has been replaced with a more explicit option per 332 # the error message below. The disk can have any name now and 333 # doesn't need to include 'android' substring. 334 if (os.path.split(mdesc.disk())[-1]).lower().count('android'): 335 if 'android' not in mdesc.os_type(): 336 fatal("It looks like you are trying to boot an Android " \ 337 "platform. To boot Android, you must specify " \ 338 "--os-type with an appropriate Android release on " \ 339 "the command line.") 340 341 # android-specific tweaks 342 if 'android' in mdesc.os_type(): 343 # generic tweaks 344 cmdline += " init=/init" 345 346 # release-specific tweaks 347 if 'kitkat' in mdesc.os_type(): 348 cmdline += " androidboot.hardware=gem5 qemu=1 qemu.gles=0 " + \ 349 "android.bootanim=0" 350 351 self.boot_osflags = fillInCmdline(mdesc, cmdline) 352 353 if external_memory: 354 # I/O traffic enters iobus 355 self.external_io = ExternalMaster(port_data="external_io", 356 port_type=external_memory) 357 self.external_io.port = self.iobus.slave 358 359 # Ensure iocache only receives traffic destined for (actual) memory. 360 self.iocache = ExternalSlave(port_data="iocache", 361 port_type=external_memory, 362 addr_ranges=self.mem_ranges) 363 self.iocache.port = self.iobus.master 364 365 # Let system_port get to nvmem and nothing else. 366 self.bridge.ranges = [self.realview.nvmem.range] 367 368 self.realview.attachOnChipIO(self.iobus) 369 else: 370 self.realview.attachOnChipIO(self.membus, self.bridge) 371 372 # Attach off-chip devices 373 self.realview.attachIO(self.iobus) 374 for dev_id, dev in enumerate(pci_devices): 375 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, dev_id + 1, 0) 376 self.realview.attachPciDevice(dev, self.iobus) 377 378 self.intrctrl = IntrControl() 379 self.terminal = Terminal() 380 self.vncserver = VncServer() 381 382 self.system_port = self.membus.slave 383 384 return self 385 386 387def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None): 388 class BaseMalta(Malta): 389 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 390 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 391 pci_func=0, pci_dev=0, pci_bus=0) 392 393 self = LinuxMipsSystem() 394 if not mdesc: 395 # generic system 396 mdesc = SysConfig() 397 self.readfile = mdesc.script() 398 self.iobus = IOXBar() 399 self.membus = MemBus() 400 self.bridge = Bridge(delay='50ns') 401 self.mem_ranges = [AddrRange('1GB')] 402 self.bridge.master = self.iobus.slave 403 self.bridge.slave = self.membus.master 404 self.disk0 = CowIdeDisk(driveID='master') 405 self.disk2 = CowIdeDisk(driveID='master') 406 self.disk0.childImage(mdesc.disk()) 407 self.disk2.childImage(disk('linux-bigswap2.img')) 408 self.malta = BaseMalta() 409 self.malta.attachIO(self.iobus) 410 self.malta.ide.pio = self.iobus.master 411 self.malta.ide.dma = self.iobus.slave 412 self.malta.ethernet.pio = self.iobus.master 413 self.malta.ethernet.dma = self.iobus.slave 414 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 415 read_only = True)) 416 self.intrctrl = IntrControl() 417 self.mem_mode = mem_mode 418 self.terminal = Terminal() 419 self.kernel = binary('mips/vmlinux') 420 self.console = binary('mips/console') 421 if not cmdline: 422 cmdline = 'root=/dev/hda1 console=ttyS0' 423 self.boot_osflags = fillInCmdline(mdesc, cmdline) 424 425 self.system_port = self.membus.slave 426 427 return self 428 429def x86IOAddress(port): 430 IO_address_space_base = 0x8000000000000000 431 return IO_address_space_base + port 432 433def connectX86ClassicSystem(x86_sys, numCPUs): 434 # Constants similar to x86_traits.hh 435 IO_address_space_base = 0x8000000000000000 436 pci_config_address_space_base = 0xc000000000000000 437 interrupts_address_space_base = 0xa000000000000000 438 APIC_range_size = 1 << 12; 439 440 x86_sys.membus = MemBus() 441 442 # North Bridge 443 x86_sys.iobus = IOXBar() 444 x86_sys.bridge = Bridge(delay='50ns') 445 x86_sys.bridge.master = x86_sys.iobus.slave 446 x86_sys.bridge.slave = x86_sys.membus.master 447 # Allow the bridge to pass through: 448 # 1) kernel configured PCI device memory map address: address range 449 # [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.) 450 # 2) the bridge to pass through the IO APIC (two pages, already contained in 1), 451 # 3) everything in the IO address range up to the local APIC, and 452 # 4) then the entire PCI address space and beyond. 453 x86_sys.bridge.ranges = \ 454 [ 455 AddrRange(0xC0000000, 0xFFFF0000), 456 AddrRange(IO_address_space_base, 457 interrupts_address_space_base - 1), 458 AddrRange(pci_config_address_space_base, 459 Addr.max) 460 ] 461 462 # Create a bridge from the IO bus to the memory bus to allow access to 463 # the local APIC (two pages) 464 x86_sys.apicbridge = Bridge(delay='50ns') 465 x86_sys.apicbridge.slave = x86_sys.iobus.master 466 x86_sys.apicbridge.master = x86_sys.membus.slave 467 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 468 interrupts_address_space_base + 469 numCPUs * APIC_range_size 470 - 1)] 471 472 # connect the io bus 473 x86_sys.pc.attachIO(x86_sys.iobus) 474 475 x86_sys.system_port = x86_sys.membus.slave 476 477def connectX86RubySystem(x86_sys): 478 # North Bridge 479 x86_sys.iobus = IOXBar() 480 481 # add the ide to the list of dma devices that later need to attach to 482 # dma controllers 483 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 484 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 485 486 487def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False): 488 if self == None: 489 self = X86System() 490 491 if not mdesc: 492 # generic system 493 mdesc = SysConfig() 494 self.readfile = mdesc.script() 495 496 self.mem_mode = mem_mode 497 498 # Physical memory 499 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 500 # for various devices. Hence, if the physical memory size is greater than 501 # 3GB, we need to split it into two parts. 502 excess_mem_size = \ 503 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 504 if excess_mem_size <= 0: 505 self.mem_ranges = [AddrRange(mdesc.mem())] 506 else: 507 warn("Physical memory size specified is %s which is greater than " \ 508 "3GB. Twice the number of memory controllers would be " \ 509 "created." % (mdesc.mem())) 510 511 self.mem_ranges = [AddrRange('3GB'), 512 AddrRange(Addr('4GB'), size = excess_mem_size)] 513 514 # Platform 515 self.pc = Pc() 516 517 # Create and connect the busses required by each memory system 518 if Ruby: 519 connectX86RubySystem(self) 520 else: 521 connectX86ClassicSystem(self, numCPUs) 522 523 self.intrctrl = IntrControl() 524 525 # Disks 526 disk0 = CowIdeDisk(driveID='master') 527 disk2 = CowIdeDisk(driveID='master') 528 disk0.childImage(mdesc.disk()) 529 disk2.childImage(disk('linux-bigswap2.img')) 530 self.pc.south_bridge.ide.disks = [disk0, disk2] 531 532 # Add in a Bios information structure. 533 structures = [X86SMBiosBiosInformation()] 534 self.smbios_table.structures = structures 535 536 # Set up the Intel MP table 537 base_entries = [] 538 ext_entries = [] 539 for i in xrange(numCPUs): 540 bp = X86IntelMPProcessor( 541 local_apic_id = i, 542 local_apic_version = 0x14, 543 enable = True, 544 bootstrap = (i == 0)) 545 base_entries.append(bp) 546 io_apic = X86IntelMPIOAPIC( 547 id = numCPUs, 548 version = 0x11, 549 enable = True, 550 address = 0xfec00000) 551 self.pc.south_bridge.io_apic.apic_id = io_apic.id 552 base_entries.append(io_apic) 553 # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)", 554 # but linux kernel cannot config PCI device if it was not connected to PCI bus, 555 # so we fix PCI bus id to 0, and ISA bus id to 1. 556 pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI ') 557 base_entries.append(pci_bus) 558 isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA ') 559 base_entries.append(isa_bus) 560 connect_busses = X86IntelMPBusHierarchy(bus_id=1, 561 subtractive_decode=True, parent_bus=0) 562 ext_entries.append(connect_busses) 563 pci_dev4_inta = X86IntelMPIOIntAssignment( 564 interrupt_type = 'INT', 565 polarity = 'ConformPolarity', 566 trigger = 'ConformTrigger', 567 source_bus_id = 0, 568 source_bus_irq = 0 + (4 << 2), 569 dest_io_apic_id = io_apic.id, 570 dest_io_apic_intin = 16) 571 base_entries.append(pci_dev4_inta) 572 def assignISAInt(irq, apicPin): 573 assign_8259_to_apic = X86IntelMPIOIntAssignment( 574 interrupt_type = 'ExtInt', 575 polarity = 'ConformPolarity', 576 trigger = 'ConformTrigger', 577 source_bus_id = 1, 578 source_bus_irq = irq, 579 dest_io_apic_id = io_apic.id, 580 dest_io_apic_intin = 0) 581 base_entries.append(assign_8259_to_apic) 582 assign_to_apic = X86IntelMPIOIntAssignment( 583 interrupt_type = 'INT', 584 polarity = 'ConformPolarity', 585 trigger = 'ConformTrigger', 586 source_bus_id = 1, 587 source_bus_irq = irq, 588 dest_io_apic_id = io_apic.id, 589 dest_io_apic_intin = apicPin) 590 base_entries.append(assign_to_apic) 591 assignISAInt(0, 2) 592 assignISAInt(1, 1) 593 for i in range(3, 15): 594 assignISAInt(i, i) 595 self.intel_mp_table.base_entries = base_entries 596 self.intel_mp_table.ext_entries = ext_entries 597 598def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False, 599 cmdline=None): 600 self = LinuxX86System() 601 602 # Build up the x86 system and then specialize it for Linux 603 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 604 605 # We assume below that there's at least 1MB of memory. We'll require 2 606 # just to avoid corner cases. 607 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 608 assert(phys_mem_size >= 0x200000) 609 assert(len(self.mem_ranges) <= 2) 610 611 entries = \ 612 [ 613 # Mark the first megabyte of memory as reserved 614 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 615 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 616 # Mark the rest of physical memory as available 617 X86E820Entry(addr = 0x100000, 618 size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 619 range_type = 1), 620 ] 621 622 # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force 623 # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this 624 # specific range can pass though bridge to iobus. 625 if len(self.mem_ranges) == 1: 626 entries.append(X86E820Entry(addr = self.mem_ranges[0].size(), 627 size='%dB' % (0xC0000000 - self.mem_ranges[0].size()), 628 range_type=2)) 629 630 # Reserve the last 16kB of the 32-bit address space for the m5op interface 631 entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2)) 632 633 # In case the physical memory is greater than 3GB, we split it into two 634 # parts and add a separate e820 entry for the second part. This entry 635 # starts at 0x100000000, which is the first address after the space 636 # reserved for devices. 637 if len(self.mem_ranges) == 2: 638 entries.append(X86E820Entry(addr = 0x100000000, 639 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 640 641 self.e820_table.entries = entries 642 643 # Command line 644 if not cmdline: 645 cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1' 646 self.boot_osflags = fillInCmdline(mdesc, cmdline) 647 self.kernel = binary('x86_64-vmlinux-2.6.22.9') 648 return self 649 650 651def makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 652 self = Root(full_system = full_system) 653 self.testsys = testSystem 654 self.drivesys = driveSystem 655 self.etherlink = EtherLink() 656 657 if hasattr(testSystem, 'realview'): 658 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 659 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 660 elif hasattr(testSystem, 'tsunami'): 661 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 662 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 663 else: 664 fatal("Don't know how to connect these system together") 665 666 if dumpfile: 667 self.etherdump = EtherDump(file=dumpfile) 668 self.etherlink.dump = Parent.etherdump 669 670 return self 671 672 673def makeDistRoot(testSystem, 674 rank, 675 size, 676 server_name, 677 server_port, 678 sync_repeat, 679 sync_start, 680 linkspeed, 681 linkdelay, 682 dumpfile): 683 self = Root(full_system = True) 684 self.testsys = testSystem 685 686 self.etherlink = DistEtherLink(speed = linkspeed, 687 delay = linkdelay, 688 dist_rank = rank, 689 dist_size = size, 690 server_name = server_name, 691 server_port = server_port, 692 sync_start = sync_start, 693 sync_repeat = sync_repeat) 694 695 if hasattr(testSystem, 'realview'): 696 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 697 elif hasattr(testSystem, 'tsunami'): 698 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 699 else: 700 fatal("Don't know how to connect DistEtherLink to this system") 701 702 if dumpfile: 703 self.etherdump = EtherDump(file=dumpfile) 704 self.etherlink.dump = Parent.etherdump 705 706 return self 707