FSConfig.py revision 10720:67b3e74de9ae 
1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
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8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
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11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
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18# modification, are permitted provided that the following conditions are
19# met: redistributions of source code must retain the above copyright
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32# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import *
45
46class CowIdeDisk(IdeDisk):
47    image = CowDiskImage(child=RawDiskImage(read_only=True),
48                         read_only=False)
49
50    def childImage(self, ci):
51        self.image.child.image_file = ci
52
53class MemBus(SystemXBar):
54    badaddr_responder = BadAddr()
55    default = Self.badaddr_responder.pio
56
57
58def fillInCmdline(mdesc, template, **kwargs):
59    kwargs.setdefault('disk', mdesc.disk())
60    kwargs.setdefault('rootdev', mdesc.rootdev())
61    kwargs.setdefault('mem', mdesc.mem())
62    kwargs.setdefault('script', mdesc.script())
63    return template % kwargs
64
65def makeLinuxAlphaSystem(mem_mode, mdesc=None, ruby=False, cmdline=None):
66
67    class BaseTsunami(Tsunami):
68        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
69        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
70                            pci_func=0, pci_dev=0, pci_bus=0)
71
72    self = LinuxAlphaSystem()
73    if not mdesc:
74        # generic system
75        mdesc = SysConfig()
76    self.readfile = mdesc.script()
77
78    self.tsunami = BaseTsunami()
79
80    # Create the io bus to connect all device ports
81    self.iobus = IOXBar()
82    self.tsunami.attachIO(self.iobus)
83
84    self.tsunami.ide.pio = self.iobus.master
85    self.tsunami.ide.config = self.iobus.master
86
87    self.tsunami.ethernet.pio = self.iobus.master
88    self.tsunami.ethernet.config = self.iobus.master
89
90    if ruby:
91        # Store the dma devices for later connection to dma ruby ports.
92        # Append an underscore to dma_ports to avoid the SimObjectVector check.
93        self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
94    else:
95        self.membus = MemBus()
96
97        # By default the bridge responds to all addresses above the I/O
98        # base address (including the PCI config space)
99        IO_address_space_base = 0x80000000000
100        self.bridge = Bridge(delay='50ns',
101                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
102        self.bridge.master = self.iobus.slave
103        self.bridge.slave = self.membus.master
104
105        self.tsunami.ide.dma = self.iobus.slave
106        self.tsunami.ethernet.dma = self.iobus.slave
107
108        self.system_port = self.membus.slave
109
110    self.mem_ranges = [AddrRange(mdesc.mem())]
111    self.disk0 = CowIdeDisk(driveID='master')
112    self.disk2 = CowIdeDisk(driveID='master')
113    self.disk0.childImage(mdesc.disk())
114    self.disk2.childImage(disk('linux-bigswap2.img'))
115    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
116                                               read_only = True))
117    self.intrctrl = IntrControl()
118    self.mem_mode = mem_mode
119    self.terminal = Terminal()
120    self.kernel = binary('vmlinux')
121    self.pal = binary('ts_osfpal')
122    self.console = binary('console')
123    if not cmdline:
124        cmdline = 'root=/dev/hda1 console=ttyS0'
125    self.boot_osflags = fillInCmdline(mdesc, cmdline)
126
127    return self
128
129def makeSparcSystem(mem_mode, mdesc=None):
130    # Constants from iob.cc and uart8250.cc
131    iob_man_addr = 0x9800000000
132    uart_pio_size = 8
133
134    class CowMmDisk(MmDisk):
135        image = CowDiskImage(child=RawDiskImage(read_only=True),
136                             read_only=False)
137
138        def childImage(self, ci):
139            self.image.child.image_file = ci
140
141    self = SparcSystem()
142    if not mdesc:
143        # generic system
144        mdesc = SysConfig()
145    self.readfile = mdesc.script()
146    self.iobus = IOXBar()
147    self.membus = MemBus()
148    self.bridge = Bridge(delay='50ns')
149    self.t1000 = T1000()
150    self.t1000.attachOnChipIO(self.membus)
151    self.t1000.attachIO(self.iobus)
152    self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
153                       AddrRange(Addr('2GB'), size ='256MB')]
154    self.bridge.master = self.iobus.slave
155    self.bridge.slave = self.membus.master
156    self.rom.port = self.membus.master
157    self.nvram.port = self.membus.master
158    self.hypervisor_desc.port = self.membus.master
159    self.partition_desc.port = self.membus.master
160    self.intrctrl = IntrControl()
161    self.disk0 = CowMmDisk()
162    self.disk0.childImage(disk('disk.s10hw2'))
163    self.disk0.pio = self.iobus.master
164
165    # The puart0 and hvuart are placed on the IO bus, so create ranges
166    # for them. The remaining IO range is rather fragmented, so poke
167    # holes for the iob and partition descriptors etc.
168    self.bridge.ranges = \
169        [
170        AddrRange(self.t1000.puart0.pio_addr,
171                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
172        AddrRange(self.disk0.pio_addr,
173                  self.t1000.fake_jbi.pio_addr +
174                  self.t1000.fake_jbi.pio_size - 1),
175        AddrRange(self.t1000.fake_clk.pio_addr,
176                  iob_man_addr - 1),
177        AddrRange(self.t1000.fake_l2_1.pio_addr,
178                  self.t1000.fake_ssi.pio_addr +
179                  self.t1000.fake_ssi.pio_size - 1),
180        AddrRange(self.t1000.hvuart.pio_addr,
181                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
182        ]
183    self.reset_bin = binary('reset_new.bin')
184    self.hypervisor_bin = binary('q_new.bin')
185    self.openboot_bin = binary('openboot_new.bin')
186    self.nvram_bin = binary('nvram1')
187    self.hypervisor_desc_bin = binary('1up-hv.bin')
188    self.partition_desc_bin = binary('1up-md.bin')
189
190    self.system_port = self.membus.slave
191
192    return self
193
194def makeArmSystem(mem_mode, machine_type, num_cpus=1, mdesc=None,
195                  dtb_filename=None, bare_metal=False, cmdline=None):
196    assert machine_type
197
198    if bare_metal:
199        self = ArmSystem()
200    else:
201        self = LinuxArmSystem()
202
203    if not mdesc:
204        # generic system
205        mdesc = SysConfig()
206
207    self.readfile = mdesc.script()
208    self.iobus = IOXBar()
209    self.membus = MemBus()
210    self.membus.badaddr_responder.warn_access = "warn"
211    self.bridge = Bridge(delay='50ns')
212    self.bridge.master = self.iobus.slave
213    self.bridge.slave = self.membus.master
214
215    self.mem_mode = mem_mode
216
217    if machine_type == "RealView_PBX":
218        self.realview = RealViewPBX()
219    elif machine_type == "RealView_EB":
220        self.realview = RealViewEB()
221    elif machine_type == "VExpress_EMM":
222        self.realview = VExpress_EMM()
223        if not dtb_filename:
224            dtb_filename = 'vexpress.aarch32.ll_20131205.0-gem5.%dcpu.dtb' % num_cpus
225    elif machine_type == "VExpress_EMM64":
226        self.realview = VExpress_EMM64()
227        if os.path.split(mdesc.disk())[-1] == 'linux-aarch32-ael.img':
228            print "Selected 64-bit ARM architecture, updating default disk image..."
229            mdesc.diskname = 'linaro-minimal-aarch64.img'
230        if not dtb_filename:
231            dtb_filename = 'vexpress.aarch64.20140821.dtb'
232    else:
233        print "Unknown Machine Type"
234        sys.exit(1)
235
236    self.cf0 = CowIdeDisk(driveID='master')
237    self.cf0.childImage(mdesc.disk())
238
239    # Attach any PCI devices this platform supports
240    self.realview.attachPciDevices()
241    # default to an IDE controller rather than a CF one
242    try:
243        self.realview.ide.disks = [self.cf0]
244    except:
245        self.realview.cf_ctrl.disks = [self.cf0]
246
247    self.mem_ranges = []
248    size_remain = long(Addr(mdesc.mem()))
249    for region in self.realview._mem_regions:
250        if size_remain > long(region[1]):
251            self.mem_ranges.append(AddrRange(region[0], size=region[1]))
252            size_remain = size_remain - long(region[1])
253        else:
254            self.mem_ranges.append(AddrRange(region[0], size=size_remain))
255            size_remain = 0
256            break
257        warn("Memory size specified spans more than one region. Creating" \
258             " another memory controller for that range.")
259
260    if size_remain > 0:
261        fatal("The currently selected ARM platforms doesn't support" \
262              " the amount of DRAM you've selected. Please try" \
263              " another platform")
264
265    if bare_metal:
266        # EOT character on UART will end the simulation
267        self.realview.uart.end_on_eot = True
268    else:
269        if machine_type == "VExpress_EMM64":
270            self.kernel = binary('vmlinux.aarch64.20140821')
271        elif machine_type == "VExpress_EMM":
272            self.kernel = binary('vmlinux.aarch32.ll_20131205.0-gem5')
273        else:
274            self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
275
276        if dtb_filename:
277            self.dtb_filename = binary(dtb_filename)
278        self.machine_type = machine_type
279        # Ensure that writes to the UART actually go out early in the boot
280        if not cmdline:
281            cmdline = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
282                      'lpj=19988480 norandmaps rw loglevel=8 ' + \
283                      'mem=%(mem)s root=%(rootdev)s'
284
285        self.realview.setupBootLoader(self.membus, self, binary)
286        self.gic_cpu_addr = self.realview.gic.cpu_addr
287        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
288
289        if mdesc.disk().lower().count('android'):
290            cmdline += " init=/init "
291        self.boot_osflags = fillInCmdline(mdesc, cmdline)
292    self.realview.attachOnChipIO(self.membus, self.bridge)
293    self.realview.attachIO(self.iobus)
294    self.intrctrl = IntrControl()
295    self.terminal = Terminal()
296    self.vncserver = VncServer()
297
298    self.system_port = self.membus.slave
299
300    return self
301
302
303def makeLinuxMipsSystem(mem_mode, mdesc=None, cmdline=None):
304    class BaseMalta(Malta):
305        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
306        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
307                            pci_func=0, pci_dev=0, pci_bus=0)
308
309    self = LinuxMipsSystem()
310    if not mdesc:
311        # generic system
312        mdesc = SysConfig()
313    self.readfile = mdesc.script()
314    self.iobus = IOXBar()
315    self.membus = MemBus()
316    self.bridge = Bridge(delay='50ns')
317    self.mem_ranges = [AddrRange('1GB')]
318    self.bridge.master = self.iobus.slave
319    self.bridge.slave = self.membus.master
320    self.disk0 = CowIdeDisk(driveID='master')
321    self.disk2 = CowIdeDisk(driveID='master')
322    self.disk0.childImage(mdesc.disk())
323    self.disk2.childImage(disk('linux-bigswap2.img'))
324    self.malta = BaseMalta()
325    self.malta.attachIO(self.iobus)
326    self.malta.ide.pio = self.iobus.master
327    self.malta.ide.config = self.iobus.master
328    self.malta.ide.dma = self.iobus.slave
329    self.malta.ethernet.pio = self.iobus.master
330    self.malta.ethernet.config = self.iobus.master
331    self.malta.ethernet.dma = self.iobus.slave
332    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
333                                               read_only = True))
334    self.intrctrl = IntrControl()
335    self.mem_mode = mem_mode
336    self.terminal = Terminal()
337    self.kernel = binary('mips/vmlinux')
338    self.console = binary('mips/console')
339    if not cmdline:
340        cmdline = 'root=/dev/hda1 console=ttyS0'
341    self.boot_osflags = fillInCmdline(mdesc, cmdline)
342
343    self.system_port = self.membus.slave
344
345    return self
346
347def x86IOAddress(port):
348    IO_address_space_base = 0x8000000000000000
349    return IO_address_space_base + port
350
351def connectX86ClassicSystem(x86_sys, numCPUs):
352    # Constants similar to x86_traits.hh
353    IO_address_space_base = 0x8000000000000000
354    pci_config_address_space_base = 0xc000000000000000
355    interrupts_address_space_base = 0xa000000000000000
356    APIC_range_size = 1 << 12;
357
358    x86_sys.membus = MemBus()
359
360    # North Bridge
361    x86_sys.iobus = IOXBar()
362    x86_sys.bridge = Bridge(delay='50ns')
363    x86_sys.bridge.master = x86_sys.iobus.slave
364    x86_sys.bridge.slave = x86_sys.membus.master
365    # Allow the bridge to pass through:
366    #  1) kernel configured PCI device memory map address: address range
367    #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
368    #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
369    #  3) everything in the IO address range up to the local APIC, and
370    #  4) then the entire PCI address space and beyond.
371    x86_sys.bridge.ranges = \
372        [
373        AddrRange(0xC0000000, 0xFFFF0000),
374        AddrRange(IO_address_space_base,
375                  interrupts_address_space_base - 1),
376        AddrRange(pci_config_address_space_base,
377                  Addr.max)
378        ]
379
380    # Create a bridge from the IO bus to the memory bus to allow access to
381    # the local APIC (two pages)
382    x86_sys.apicbridge = Bridge(delay='50ns')
383    x86_sys.apicbridge.slave = x86_sys.iobus.master
384    x86_sys.apicbridge.master = x86_sys.membus.slave
385    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
386                                           interrupts_address_space_base +
387                                           numCPUs * APIC_range_size
388                                           - 1)]
389
390    # connect the io bus
391    x86_sys.pc.attachIO(x86_sys.iobus)
392
393    x86_sys.system_port = x86_sys.membus.slave
394
395def connectX86RubySystem(x86_sys):
396    # North Bridge
397    x86_sys.iobus = IOXBar()
398
399    # add the ide to the list of dma devices that later need to attach to
400    # dma controllers
401    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
402    x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
403
404
405def makeX86System(mem_mode, numCPUs=1, mdesc=None, self=None, Ruby=False):
406    if self == None:
407        self = X86System()
408
409    if not mdesc:
410        # generic system
411        mdesc = SysConfig()
412    self.readfile = mdesc.script()
413
414    self.mem_mode = mem_mode
415
416    # Physical memory
417    # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
418    # for various devices.  Hence, if the physical memory size is greater than
419    # 3GB, we need to split it into two parts.
420    excess_mem_size = \
421        convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
422    if excess_mem_size <= 0:
423        self.mem_ranges = [AddrRange(mdesc.mem())]
424    else:
425        warn("Physical memory size specified is %s which is greater than " \
426             "3GB.  Twice the number of memory controllers would be " \
427             "created."  % (mdesc.mem()))
428
429        self.mem_ranges = [AddrRange('3GB'),
430            AddrRange(Addr('4GB'), size = excess_mem_size)]
431
432    # Platform
433    self.pc = Pc()
434
435    # Create and connect the busses required by each memory system
436    if Ruby:
437        connectX86RubySystem(self)
438    else:
439        connectX86ClassicSystem(self, numCPUs)
440
441    self.intrctrl = IntrControl()
442
443    # Disks
444    disk0 = CowIdeDisk(driveID='master')
445    disk2 = CowIdeDisk(driveID='master')
446    disk0.childImage(mdesc.disk())
447    disk2.childImage(disk('linux-bigswap2.img'))
448    self.pc.south_bridge.ide.disks = [disk0, disk2]
449
450    # Add in a Bios information structure.
451    structures = [X86SMBiosBiosInformation()]
452    self.smbios_table.structures = structures
453
454    # Set up the Intel MP table
455    base_entries = []
456    ext_entries = []
457    for i in xrange(numCPUs):
458        bp = X86IntelMPProcessor(
459                local_apic_id = i,
460                local_apic_version = 0x14,
461                enable = True,
462                bootstrap = (i == 0))
463        base_entries.append(bp)
464    io_apic = X86IntelMPIOAPIC(
465            id = numCPUs,
466            version = 0x11,
467            enable = True,
468            address = 0xfec00000)
469    self.pc.south_bridge.io_apic.apic_id = io_apic.id
470    base_entries.append(io_apic)
471    # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
472    # but linux kernel cannot config PCI device if it was not connected to PCI bus,
473    # so we fix PCI bus id to 0, and ISA bus id to 1.
474    pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI')
475    base_entries.append(pci_bus)
476    isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA')
477    base_entries.append(isa_bus)
478    connect_busses = X86IntelMPBusHierarchy(bus_id=1,
479            subtractive_decode=True, parent_bus=0)
480    ext_entries.append(connect_busses)
481    pci_dev4_inta = X86IntelMPIOIntAssignment(
482            interrupt_type = 'INT',
483            polarity = 'ConformPolarity',
484            trigger = 'ConformTrigger',
485            source_bus_id = 0,
486            source_bus_irq = 0 + (4 << 2),
487            dest_io_apic_id = io_apic.id,
488            dest_io_apic_intin = 16)
489    base_entries.append(pci_dev4_inta)
490    def assignISAInt(irq, apicPin):
491        assign_8259_to_apic = X86IntelMPIOIntAssignment(
492                interrupt_type = 'ExtInt',
493                polarity = 'ConformPolarity',
494                trigger = 'ConformTrigger',
495                source_bus_id = 1,
496                source_bus_irq = irq,
497                dest_io_apic_id = io_apic.id,
498                dest_io_apic_intin = 0)
499        base_entries.append(assign_8259_to_apic)
500        assign_to_apic = X86IntelMPIOIntAssignment(
501                interrupt_type = 'INT',
502                polarity = 'ConformPolarity',
503                trigger = 'ConformTrigger',
504                source_bus_id = 1,
505                source_bus_irq = irq,
506                dest_io_apic_id = io_apic.id,
507                dest_io_apic_intin = apicPin)
508        base_entries.append(assign_to_apic)
509    assignISAInt(0, 2)
510    assignISAInt(1, 1)
511    for i in range(3, 15):
512        assignISAInt(i, i)
513    self.intel_mp_table.base_entries = base_entries
514    self.intel_mp_table.ext_entries = ext_entries
515
516def makeLinuxX86System(mem_mode, numCPUs=1, mdesc=None, Ruby=False,
517                       cmdline=None):
518    self = LinuxX86System()
519
520    # Build up the x86 system and then specialize it for Linux
521    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
522
523    # We assume below that there's at least 1MB of memory. We'll require 2
524    # just to avoid corner cases.
525    phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
526    assert(phys_mem_size >= 0x200000)
527    assert(len(self.mem_ranges) <= 2)
528
529    entries = \
530       [
531        # Mark the first megabyte of memory as reserved
532        X86E820Entry(addr = 0, size = '639kB', range_type = 1),
533        X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
534        # Mark the rest of physical memory as available
535        X86E820Entry(addr = 0x100000,
536                size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
537                range_type = 1),
538        ]
539
540    # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
541    # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
542    # specific range can pass though bridge to iobus.
543    if len(self.mem_ranges) == 1:
544        entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
545            size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
546            range_type=2))
547
548    # Reserve the last 16kB of the 32-bit address space for the m5op interface
549    entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
550
551    # In case the physical memory is greater than 3GB, we split it into two
552    # parts and add a separate e820 entry for the second part.  This entry
553    # starts at 0x100000000,  which is the first address after the space
554    # reserved for devices.
555    if len(self.mem_ranges) == 2:
556        entries.append(X86E820Entry(addr = 0x100000000,
557            size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
558
559    self.e820_table.entries = entries
560
561    # Command line
562    if not cmdline:
563        cmdline = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 root=/dev/hda1'
564    self.boot_osflags = fillInCmdline(mdesc, cmdline)
565    self.kernel = binary('x86_64-vmlinux-2.6.22.9')
566    return self
567
568
569def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
570    self = Root(full_system = full_system)
571    self.testsys = testSystem
572    self.drivesys = driveSystem
573    self.etherlink = EtherLink()
574
575    if hasattr(testSystem, 'realview'):
576        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
577        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
578    elif hasattr(testSystem, 'tsunami'):
579        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
580        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
581    else:
582        fatal("Don't know how to connect these system together")
583
584    if dumpfile:
585        self.etherdump = EtherDump(file=dumpfile)
586        self.etherlink.dump = Parent.etherdump
587
588    return self
589