FSConfig.py revision 10507:f33fab6214c4 
1# Copyright (c) 2010-2012 ARM Limited
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3#
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13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
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39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import *
45
46class CowIdeDisk(IdeDisk):
47    image = CowDiskImage(child=RawDiskImage(read_only=True),
48                         read_only=False)
49
50    def childImage(self, ci):
51        self.image.child.image_file = ci
52
53class MemBus(CoherentXBar):
54    badaddr_responder = BadAddr()
55    default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False):
59
60    class BaseTsunami(Tsunami):
61        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63                            pci_func=0, pci_dev=0, pci_bus=0)
64
65    self = LinuxAlphaSystem()
66    if not mdesc:
67        # generic system
68        mdesc = SysConfig()
69    self.readfile = mdesc.script()
70
71    self.tsunami = BaseTsunami()
72
73    # Create the io bus to connect all device ports
74    self.iobus = NoncoherentXBar()
75    self.tsunami.attachIO(self.iobus)
76
77    self.tsunami.ide.pio = self.iobus.master
78    self.tsunami.ide.config = self.iobus.master
79
80    self.tsunami.ethernet.pio = self.iobus.master
81    self.tsunami.ethernet.config = self.iobus.master
82
83    if ruby:
84        # Store the dma devices for later connection to dma ruby ports.
85        # Append an underscore to dma_ports to avoid the SimObjectVector check.
86        self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
87    else:
88        self.membus = MemBus()
89
90        # By default the bridge responds to all addresses above the I/O
91        # base address (including the PCI config space)
92        IO_address_space_base = 0x80000000000
93        self.bridge = Bridge(delay='50ns',
94                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
95        self.bridge.master = self.iobus.slave
96        self.bridge.slave = self.membus.master
97
98        self.tsunami.ide.dma = self.iobus.slave
99        self.tsunami.ethernet.dma = self.iobus.slave
100
101        self.system_port = self.membus.slave
102
103    self.mem_ranges = [AddrRange(mdesc.mem())]
104    self.disk0 = CowIdeDisk(driveID='master')
105    self.disk2 = CowIdeDisk(driveID='master')
106    self.disk0.childImage(mdesc.disk())
107    self.disk2.childImage(disk('linux-bigswap2.img'))
108    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
109                                               read_only = True))
110    self.intrctrl = IntrControl()
111    self.mem_mode = mem_mode
112    self.terminal = Terminal()
113    self.kernel = binary('vmlinux')
114    self.pal = binary('ts_osfpal')
115    self.console = binary('console')
116    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
117
118    return self
119
120def makeSparcSystem(mem_mode, mdesc = None):
121    # Constants from iob.cc and uart8250.cc
122    iob_man_addr = 0x9800000000
123    uart_pio_size = 8
124
125    class CowMmDisk(MmDisk):
126        image = CowDiskImage(child=RawDiskImage(read_only=True),
127                             read_only=False)
128
129        def childImage(self, ci):
130            self.image.child.image_file = ci
131
132    self = SparcSystem()
133    if not mdesc:
134        # generic system
135        mdesc = SysConfig()
136    self.readfile = mdesc.script()
137    self.iobus = NoncoherentXBar()
138    self.membus = MemBus()
139    self.bridge = Bridge(delay='50ns')
140    self.t1000 = T1000()
141    self.t1000.attachOnChipIO(self.membus)
142    self.t1000.attachIO(self.iobus)
143    self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
144                       AddrRange(Addr('2GB'), size ='256MB')]
145    self.bridge.master = self.iobus.slave
146    self.bridge.slave = self.membus.master
147    self.rom.port = self.membus.master
148    self.nvram.port = self.membus.master
149    self.hypervisor_desc.port = self.membus.master
150    self.partition_desc.port = self.membus.master
151    self.intrctrl = IntrControl()
152    self.disk0 = CowMmDisk()
153    self.disk0.childImage(disk('disk.s10hw2'))
154    self.disk0.pio = self.iobus.master
155
156    # The puart0 and hvuart are placed on the IO bus, so create ranges
157    # for them. The remaining IO range is rather fragmented, so poke
158    # holes for the iob and partition descriptors etc.
159    self.bridge.ranges = \
160        [
161        AddrRange(self.t1000.puart0.pio_addr,
162                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
163        AddrRange(self.disk0.pio_addr,
164                  self.t1000.fake_jbi.pio_addr +
165                  self.t1000.fake_jbi.pio_size - 1),
166        AddrRange(self.t1000.fake_clk.pio_addr,
167                  iob_man_addr - 1),
168        AddrRange(self.t1000.fake_l2_1.pio_addr,
169                  self.t1000.fake_ssi.pio_addr +
170                  self.t1000.fake_ssi.pio_size - 1),
171        AddrRange(self.t1000.hvuart.pio_addr,
172                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
173        ]
174    self.reset_bin = binary('reset_new.bin')
175    self.hypervisor_bin = binary('q_new.bin')
176    self.openboot_bin = binary('openboot_new.bin')
177    self.nvram_bin = binary('nvram1')
178    self.hypervisor_desc_bin = binary('1up-hv.bin')
179    self.partition_desc_bin = binary('1up-md.bin')
180
181    self.system_port = self.membus.slave
182
183    return self
184
185def makeArmSystem(mem_mode, machine_type, mdesc = None,
186                  dtb_filename = None, bare_metal=False):
187    assert machine_type
188
189    if bare_metal:
190        self = ArmSystem()
191    else:
192        self = LinuxArmSystem()
193
194    if not mdesc:
195        # generic system
196        mdesc = SysConfig()
197
198    self.readfile = mdesc.script()
199    self.iobus = NoncoherentXBar()
200    self.membus = MemBus()
201    self.membus.badaddr_responder.warn_access = "warn"
202    self.bridge = Bridge(delay='50ns')
203    self.bridge.master = self.iobus.slave
204    self.bridge.slave = self.membus.master
205
206    self.mem_mode = mem_mode
207
208    if machine_type == "RealView_PBX":
209        self.realview = RealViewPBX()
210    elif machine_type == "RealView_EB":
211        self.realview = RealViewEB()
212    elif machine_type == "VExpress_ELT":
213        self.realview = VExpress_ELT()
214    elif machine_type == "VExpress_EMM":
215        self.realview = VExpress_EMM()
216    elif machine_type == "VExpress_EMM64":
217        self.realview = VExpress_EMM64()
218    else:
219        print "Unknown Machine Type"
220        sys.exit(1)
221
222    self.cf0 = CowIdeDisk(driveID='master')
223    self.cf0.childImage(mdesc.disk())
224
225    # Attach any PCI devices this platform supports
226    self.realview.attachPciDevices()
227    # default to an IDE controller rather than a CF one
228    try:
229        self.realview.ide.disks = [self.cf0]
230    except:
231        self.realview.cf_ctrl.disks = [self.cf0]
232
233    self.mem_ranges = []
234    size_remain = long(Addr(mdesc.mem()))
235    for region in self.realview._mem_regions:
236        if size_remain > long(region[1]):
237            self.mem_ranges.append(AddrRange(region[0], size=region[1]))
238            size_remain = size_remain - long(region[1])
239        else:
240            self.mem_ranges.append(AddrRange(region[0], size=size_remain))
241            size_remain = 0
242            break
243        warn("Memory size specified spans more than one region. Creating" \
244             " another memory controller for that range.")
245
246    if size_remain > 0:
247        fatal("The currently selected ARM platforms doesn't support" \
248              " the amount of DRAM you've selected. Please try" \
249              " another platform")
250
251    if bare_metal:
252        # EOT character on UART will end the simulation
253        self.realview.uart.end_on_eot = True
254    else:
255        if machine_type == "VExpress_EMM64":
256            self.kernel = binary('vmlinux-3.16-aarch64-vexpress-emm64-pcie')
257        elif machine_type == "VExpress_EMM":
258            self.kernel = binary('vmlinux-3.3-arm-vexpress-emm-pcie')
259        else:
260            self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
261
262        if dtb_filename:
263            self.dtb_filename = binary(dtb_filename)
264        self.machine_type = machine_type
265        # Ensure that writes to the UART actually go out early in the boot
266        boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
267                     'lpj=19988480 norandmaps rw loglevel=8 ' + \
268                     'mem=%s root=/dev/sda1' % mdesc.mem()
269
270        self.realview.setupBootLoader(self.membus, self, binary)
271        self.gic_cpu_addr = self.realview.gic.cpu_addr
272        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
273
274        if mdesc.disk().lower().count('android'):
275            boot_flags += " init=/init "
276        self.boot_osflags = boot_flags
277    self.realview.attachOnChipIO(self.membus, self.bridge)
278    self.realview.attachIO(self.iobus)
279    self.intrctrl = IntrControl()
280    self.terminal = Terminal()
281    self.vncserver = VncServer()
282
283    self.system_port = self.membus.slave
284
285    return self
286
287
288def makeLinuxMipsSystem(mem_mode, mdesc = None):
289    class BaseMalta(Malta):
290        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
291        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
292                            pci_func=0, pci_dev=0, pci_bus=0)
293
294    self = LinuxMipsSystem()
295    if not mdesc:
296        # generic system
297        mdesc = SysConfig()
298    self.readfile = mdesc.script()
299    self.iobus = NoncoherentXBar()
300    self.membus = MemBus()
301    self.bridge = Bridge(delay='50ns')
302    self.mem_ranges = [AddrRange('1GB')]
303    self.bridge.master = self.iobus.slave
304    self.bridge.slave = self.membus.master
305    self.disk0 = CowIdeDisk(driveID='master')
306    self.disk2 = CowIdeDisk(driveID='master')
307    self.disk0.childImage(mdesc.disk())
308    self.disk2.childImage(disk('linux-bigswap2.img'))
309    self.malta = BaseMalta()
310    self.malta.attachIO(self.iobus)
311    self.malta.ide.pio = self.iobus.master
312    self.malta.ide.config = self.iobus.master
313    self.malta.ide.dma = self.iobus.slave
314    self.malta.ethernet.pio = self.iobus.master
315    self.malta.ethernet.config = self.iobus.master
316    self.malta.ethernet.dma = self.iobus.slave
317    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
318                                               read_only = True))
319    self.intrctrl = IntrControl()
320    self.mem_mode = mem_mode
321    self.terminal = Terminal()
322    self.kernel = binary('mips/vmlinux')
323    self.console = binary('mips/console')
324    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
325
326    self.system_port = self.membus.slave
327
328    return self
329
330def x86IOAddress(port):
331    IO_address_space_base = 0x8000000000000000
332    return IO_address_space_base + port
333
334def connectX86ClassicSystem(x86_sys, numCPUs):
335    # Constants similar to x86_traits.hh
336    IO_address_space_base = 0x8000000000000000
337    pci_config_address_space_base = 0xc000000000000000
338    interrupts_address_space_base = 0xa000000000000000
339    APIC_range_size = 1 << 12;
340
341    x86_sys.membus = MemBus()
342
343    # North Bridge
344    x86_sys.iobus = NoncoherentXBar()
345    x86_sys.bridge = Bridge(delay='50ns')
346    x86_sys.bridge.master = x86_sys.iobus.slave
347    x86_sys.bridge.slave = x86_sys.membus.master
348    # Allow the bridge to pass through:
349    #  1) kernel configured PCI device memory map address: address range
350    #     [0xC0000000, 0xFFFF0000). (The upper 64kB are reserved for m5ops.)
351    #  2) the bridge to pass through the IO APIC (two pages, already contained in 1),
352    #  3) everything in the IO address range up to the local APIC, and
353    #  4) then the entire PCI address space and beyond.
354    x86_sys.bridge.ranges = \
355        [
356        AddrRange(0xC0000000, 0xFFFF0000),
357        AddrRange(IO_address_space_base,
358                  interrupts_address_space_base - 1),
359        AddrRange(pci_config_address_space_base,
360                  Addr.max)
361        ]
362
363    # Create a bridge from the IO bus to the memory bus to allow access to
364    # the local APIC (two pages)
365    x86_sys.apicbridge = Bridge(delay='50ns')
366    x86_sys.apicbridge.slave = x86_sys.iobus.master
367    x86_sys.apicbridge.master = x86_sys.membus.slave
368    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
369                                           interrupts_address_space_base +
370                                           numCPUs * APIC_range_size
371                                           - 1)]
372
373    # connect the io bus
374    x86_sys.pc.attachIO(x86_sys.iobus)
375
376    x86_sys.system_port = x86_sys.membus.slave
377
378def connectX86RubySystem(x86_sys):
379    # North Bridge
380    x86_sys.iobus = NoncoherentXBar()
381
382    # add the ide to the list of dma devices that later need to attach to
383    # dma controllers
384    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
385    x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
386
387
388def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
389                  Ruby = False):
390    if self == None:
391        self = X86System()
392
393    if not mdesc:
394        # generic system
395        mdesc = SysConfig()
396    self.readfile = mdesc.script()
397
398    self.mem_mode = mem_mode
399
400    # Physical memory
401    # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
402    # for various devices.  Hence, if the physical memory size is greater than
403    # 3GB, we need to split it into two parts.
404    excess_mem_size = \
405        convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
406    if excess_mem_size <= 0:
407        self.mem_ranges = [AddrRange(mdesc.mem())]
408    else:
409        warn("Physical memory size specified is %s which is greater than " \
410             "3GB.  Twice the number of memory controllers would be " \
411             "created."  % (mdesc.mem()))
412
413        self.mem_ranges = [AddrRange('3GB'),
414            AddrRange(Addr('4GB'), size = excess_mem_size)]
415
416    # Platform
417    self.pc = Pc()
418
419    # Create and connect the busses required by each memory system
420    if Ruby:
421        connectX86RubySystem(self)
422    else:
423        connectX86ClassicSystem(self, numCPUs)
424
425    self.intrctrl = IntrControl()
426
427    # Disks
428    disk0 = CowIdeDisk(driveID='master')
429    disk2 = CowIdeDisk(driveID='master')
430    disk0.childImage(mdesc.disk())
431    disk2.childImage(disk('linux-bigswap2.img'))
432    self.pc.south_bridge.ide.disks = [disk0, disk2]
433
434    # Add in a Bios information structure.
435    structures = [X86SMBiosBiosInformation()]
436    self.smbios_table.structures = structures
437
438    # Set up the Intel MP table
439    base_entries = []
440    ext_entries = []
441    for i in xrange(numCPUs):
442        bp = X86IntelMPProcessor(
443                local_apic_id = i,
444                local_apic_version = 0x14,
445                enable = True,
446                bootstrap = (i == 0))
447        base_entries.append(bp)
448    io_apic = X86IntelMPIOAPIC(
449            id = numCPUs,
450            version = 0x11,
451            enable = True,
452            address = 0xfec00000)
453    self.pc.south_bridge.io_apic.apic_id = io_apic.id
454    base_entries.append(io_apic)
455    # In gem5 Pc::calcPciConfigAddr(), it required "assert(bus==0)",
456    # but linux kernel cannot config PCI device if it was not connected to PCI bus,
457    # so we fix PCI bus id to 0, and ISA bus id to 1.
458    pci_bus = X86IntelMPBus(bus_id = 0, bus_type='PCI')
459    base_entries.append(pci_bus)
460    isa_bus = X86IntelMPBus(bus_id = 1, bus_type='ISA')
461    base_entries.append(isa_bus)
462    connect_busses = X86IntelMPBusHierarchy(bus_id=1,
463            subtractive_decode=True, parent_bus=0)
464    ext_entries.append(connect_busses)
465    pci_dev4_inta = X86IntelMPIOIntAssignment(
466            interrupt_type = 'INT',
467            polarity = 'ConformPolarity',
468            trigger = 'ConformTrigger',
469            source_bus_id = 0,
470            source_bus_irq = 0 + (4 << 2),
471            dest_io_apic_id = io_apic.id,
472            dest_io_apic_intin = 16)
473    base_entries.append(pci_dev4_inta)
474    def assignISAInt(irq, apicPin):
475        assign_8259_to_apic = X86IntelMPIOIntAssignment(
476                interrupt_type = 'ExtInt',
477                polarity = 'ConformPolarity',
478                trigger = 'ConformTrigger',
479                source_bus_id = 1,
480                source_bus_irq = irq,
481                dest_io_apic_id = io_apic.id,
482                dest_io_apic_intin = 0)
483        base_entries.append(assign_8259_to_apic)
484        assign_to_apic = X86IntelMPIOIntAssignment(
485                interrupt_type = 'INT',
486                polarity = 'ConformPolarity',
487                trigger = 'ConformTrigger',
488                source_bus_id = 1,
489                source_bus_irq = irq,
490                dest_io_apic_id = io_apic.id,
491                dest_io_apic_intin = apicPin)
492        base_entries.append(assign_to_apic)
493    assignISAInt(0, 2)
494    assignISAInt(1, 1)
495    for i in range(3, 15):
496        assignISAInt(i, i)
497    self.intel_mp_table.base_entries = base_entries
498    self.intel_mp_table.ext_entries = ext_entries
499
500def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
501                       Ruby = False):
502    self = LinuxX86System()
503
504    # Build up the x86 system and then specialize it for Linux
505    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
506
507    # We assume below that there's at least 1MB of memory. We'll require 2
508    # just to avoid corner cases.
509    phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
510    assert(phys_mem_size >= 0x200000)
511    assert(len(self.mem_ranges) <= 2)
512
513    entries = \
514       [
515        # Mark the first megabyte of memory as reserved
516        X86E820Entry(addr = 0, size = '639kB', range_type = 1),
517        X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
518        # Mark the rest of physical memory as available
519        X86E820Entry(addr = 0x100000,
520                size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
521                range_type = 1),
522        ]
523
524    # Mark [mem_size, 3GB) as reserved if memory less than 3GB, which force
525    # IO devices to be mapped to [0xC0000000, 0xFFFF0000). Requests to this
526    # specific range can pass though bridge to iobus.
527    if len(self.mem_ranges) == 1:
528        entries.append(X86E820Entry(addr = self.mem_ranges[0].size(),
529            size='%dB' % (0xC0000000 - self.mem_ranges[0].size()),
530            range_type=2))
531
532    # Reserve the last 16kB of the 32-bit address space for the m5op interface
533    entries.append(X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2))
534
535    # In case the physical memory is greater than 3GB, we split it into two
536    # parts and add a separate e820 entry for the second part.  This entry
537    # starts at 0x100000000,  which is the first address after the space
538    # reserved for devices.
539    if len(self.mem_ranges) == 2:
540        entries.append(X86E820Entry(addr = 0x100000000,
541            size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
542
543    self.e820_table.entries = entries
544
545    # Command line
546    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
547                        'root=/dev/hda1'
548    self.kernel = binary('x86_64-vmlinux-2.6.22.9')
549    return self
550
551
552def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
553    self = Root(full_system = full_system)
554    self.testsys = testSystem
555    self.drivesys = driveSystem
556    self.etherlink = EtherLink()
557
558    if hasattr(testSystem, 'realview'):
559        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
560        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
561    elif hasattr(testSystem, 'tsunami'):
562        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
563        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
564    else:
565        fatal("Don't know how to connect these system together")
566
567    if dumpfile:
568        self.etherdump = EtherDump(file=dumpfile)
569        self.etherlink.dump = Parent.etherdump
570
571    return self
572