FSConfig.py revision 10224:54d3ef2009a2 
1# Copyright (c) 2010-2012 ARM Limited
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3#
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13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
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34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import *
45
46class CowIdeDisk(IdeDisk):
47    image = CowDiskImage(child=RawDiskImage(read_only=True),
48                         read_only=False)
49
50    def childImage(self, ci):
51        self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54    badaddr_responder = BadAddr()
55    default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False):
59
60    class BaseTsunami(Tsunami):
61        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63                            pci_func=0, pci_dev=0, pci_bus=0)
64
65    self = LinuxAlphaSystem()
66    if not mdesc:
67        # generic system
68        mdesc = SysConfig()
69    self.readfile = mdesc.script()
70
71    self.tsunami = BaseTsunami()
72
73    # Create the io bus to connect all device ports
74    self.iobus = NoncoherentBus()
75    self.tsunami.attachIO(self.iobus)
76
77    self.tsunami.ide.pio = self.iobus.master
78    self.tsunami.ide.config = self.iobus.master
79
80    self.tsunami.ethernet.pio = self.iobus.master
81    self.tsunami.ethernet.config = self.iobus.master
82
83    if ruby:
84        # Store the dma devices for later connection to dma ruby ports.
85        # Append an underscore to dma_ports to avoid the SimObjectVector check.
86        self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
87    else:
88        self.membus = MemBus()
89
90        # By default the bridge responds to all addresses above the I/O
91        # base address (including the PCI config space)
92        IO_address_space_base = 0x80000000000
93        self.bridge = Bridge(delay='50ns',
94                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
95        self.bridge.master = self.iobus.slave
96        self.bridge.slave = self.membus.master
97
98        self.tsunami.ide.dma = self.iobus.slave
99        self.tsunami.ethernet.dma = self.iobus.slave
100
101        self.system_port = self.membus.slave
102
103    self.mem_ranges = [AddrRange(mdesc.mem())]
104    self.disk0 = CowIdeDisk(driveID='master')
105    self.disk2 = CowIdeDisk(driveID='master')
106    self.disk0.childImage(mdesc.disk())
107    self.disk2.childImage(disk('linux-bigswap2.img'))
108    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
109                                               read_only = True))
110    self.intrctrl = IntrControl()
111    self.mem_mode = mem_mode
112    self.terminal = Terminal()
113    self.kernel = binary('vmlinux')
114    self.pal = binary('ts_osfpal')
115    self.console = binary('console')
116    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
117
118    return self
119
120def makeSparcSystem(mem_mode, mdesc = None):
121    # Constants from iob.cc and uart8250.cc
122    iob_man_addr = 0x9800000000
123    uart_pio_size = 8
124
125    class CowMmDisk(MmDisk):
126        image = CowDiskImage(child=RawDiskImage(read_only=True),
127                             read_only=False)
128
129        def childImage(self, ci):
130            self.image.child.image_file = ci
131
132    self = SparcSystem()
133    if not mdesc:
134        # generic system
135        mdesc = SysConfig()
136    self.readfile = mdesc.script()
137    self.iobus = NoncoherentBus()
138    self.membus = MemBus()
139    self.bridge = Bridge(delay='50ns')
140    self.t1000 = T1000()
141    self.t1000.attachOnChipIO(self.membus)
142    self.t1000.attachIO(self.iobus)
143    self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
144                       AddrRange(Addr('2GB'), size ='256MB')]
145    self.bridge.master = self.iobus.slave
146    self.bridge.slave = self.membus.master
147    self.rom.port = self.membus.master
148    self.nvram.port = self.membus.master
149    self.hypervisor_desc.port = self.membus.master
150    self.partition_desc.port = self.membus.master
151    self.intrctrl = IntrControl()
152    self.disk0 = CowMmDisk()
153    self.disk0.childImage(disk('disk.s10hw2'))
154    self.disk0.pio = self.iobus.master
155
156    # The puart0 and hvuart are placed on the IO bus, so create ranges
157    # for them. The remaining IO range is rather fragmented, so poke
158    # holes for the iob and partition descriptors etc.
159    self.bridge.ranges = \
160        [
161        AddrRange(self.t1000.puart0.pio_addr,
162                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
163        AddrRange(self.disk0.pio_addr,
164                  self.t1000.fake_jbi.pio_addr +
165                  self.t1000.fake_jbi.pio_size - 1),
166        AddrRange(self.t1000.fake_clk.pio_addr,
167                  iob_man_addr - 1),
168        AddrRange(self.t1000.fake_l2_1.pio_addr,
169                  self.t1000.fake_ssi.pio_addr +
170                  self.t1000.fake_ssi.pio_size - 1),
171        AddrRange(self.t1000.hvuart.pio_addr,
172                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
173        ]
174    self.reset_bin = binary('reset_new.bin')
175    self.hypervisor_bin = binary('q_new.bin')
176    self.openboot_bin = binary('openboot_new.bin')
177    self.nvram_bin = binary('nvram1')
178    self.hypervisor_desc_bin = binary('1up-hv.bin')
179    self.partition_desc_bin = binary('1up-md.bin')
180
181    self.system_port = self.membus.slave
182
183    return self
184
185def makeArmSystem(mem_mode, machine_type, mdesc = None,
186                  dtb_filename = None, bare_metal=False):
187    assert machine_type
188
189    if bare_metal:
190        self = ArmSystem()
191    else:
192        self = LinuxArmSystem()
193
194    if not mdesc:
195        # generic system
196        mdesc = SysConfig()
197
198    self.readfile = mdesc.script()
199    self.iobus = NoncoherentBus()
200    self.membus = MemBus()
201    self.membus.badaddr_responder.warn_access = "warn"
202    self.bridge = Bridge(delay='50ns')
203    self.bridge.master = self.iobus.slave
204    self.bridge.slave = self.membus.master
205
206    self.mem_mode = mem_mode
207
208    if machine_type == "RealView_PBX":
209        self.realview = RealViewPBX()
210    elif machine_type == "RealView_EB":
211        self.realview = RealViewEB()
212    elif machine_type == "VExpress_ELT":
213        self.realview = VExpress_ELT()
214    elif machine_type == "VExpress_EMM":
215        self.realview = VExpress_EMM()
216    elif machine_type == "VExpress_EMM64":
217        self.realview = VExpress_EMM64()
218    else:
219        print "Unknown Machine Type"
220        sys.exit(1)
221
222    self.cf0 = CowIdeDisk(driveID='master')
223    self.cf0.childImage(mdesc.disk())
224    # default to an IDE controller rather than a CF one
225    # assuming we've got one; EMM64 is an exception for the moment
226    if machine_type != "VExpress_EMM64":
227        try:
228            self.realview.ide.disks = [self.cf0]
229        except:
230            self.realview.cf_ctrl.disks = [self.cf0]
231    else:
232        self.realview.cf_ctrl.disks = [self.cf0]
233
234    if bare_metal:
235        # EOT character on UART will end the simulation
236        self.realview.uart.end_on_eot = True
237        self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
238                                     size = mdesc.mem())]
239    else:
240        if machine_type == "VExpress_EMM64":
241            self.kernel = binary('vmlinux-3.14-aarch64-vexpress-emm64')
242        elif machine_type == "VExpress_EMM":
243            self.kernel = binary('vmlinux-3.3-arm-vexpress-emm-pcie')
244        else:
245            self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
246
247        if dtb_filename:
248            self.dtb_filename = binary(dtb_filename)
249        self.machine_type = machine_type
250        if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
251            print "The currently selected ARM platforms doesn't support"
252            print " the amount of DRAM you've selected. Please try"
253            print " another platform"
254            sys.exit(1)
255
256        # Ensure that writes to the UART actually go out early in the boot
257        boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
258                     'lpj=19988480 norandmaps rw loglevel=8 ' + \
259                     'mem=%s root=/dev/sda1' % mdesc.mem()
260
261        self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
262                                     size = mdesc.mem())]
263        self.realview.setupBootLoader(self.membus, self, binary)
264        self.gic_cpu_addr = self.realview.gic.cpu_addr
265        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
266
267        if mdesc.disk().lower().count('android'):
268            boot_flags += " init=/init "
269        self.boot_osflags = boot_flags
270    self.realview.attachOnChipIO(self.membus, self.bridge)
271    self.realview.attachIO(self.iobus)
272    self.intrctrl = IntrControl()
273    self.terminal = Terminal()
274    self.vncserver = VncServer()
275
276    self.system_port = self.membus.slave
277
278    return self
279
280
281def makeLinuxMipsSystem(mem_mode, mdesc = None):
282    class BaseMalta(Malta):
283        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
284        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
285                            pci_func=0, pci_dev=0, pci_bus=0)
286
287    self = LinuxMipsSystem()
288    if not mdesc:
289        # generic system
290        mdesc = SysConfig()
291    self.readfile = mdesc.script()
292    self.iobus = NoncoherentBus()
293    self.membus = MemBus()
294    self.bridge = Bridge(delay='50ns')
295    self.mem_ranges = [AddrRange('1GB')]
296    self.bridge.master = self.iobus.slave
297    self.bridge.slave = self.membus.master
298    self.disk0 = CowIdeDisk(driveID='master')
299    self.disk2 = CowIdeDisk(driveID='master')
300    self.disk0.childImage(mdesc.disk())
301    self.disk2.childImage(disk('linux-bigswap2.img'))
302    self.malta = BaseMalta()
303    self.malta.attachIO(self.iobus)
304    self.malta.ide.pio = self.iobus.master
305    self.malta.ide.config = self.iobus.master
306    self.malta.ide.dma = self.iobus.slave
307    self.malta.ethernet.pio = self.iobus.master
308    self.malta.ethernet.config = self.iobus.master
309    self.malta.ethernet.dma = self.iobus.slave
310    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
311                                               read_only = True))
312    self.intrctrl = IntrControl()
313    self.mem_mode = mem_mode
314    self.terminal = Terminal()
315    self.kernel = binary('mips/vmlinux')
316    self.console = binary('mips/console')
317    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
318
319    self.system_port = self.membus.slave
320
321    return self
322
323def x86IOAddress(port):
324    IO_address_space_base = 0x8000000000000000
325    return IO_address_space_base + port
326
327def connectX86ClassicSystem(x86_sys, numCPUs):
328    # Constants similar to x86_traits.hh
329    IO_address_space_base = 0x8000000000000000
330    pci_config_address_space_base = 0xc000000000000000
331    interrupts_address_space_base = 0xa000000000000000
332    APIC_range_size = 1 << 12;
333
334    x86_sys.membus = MemBus()
335
336    # North Bridge
337    x86_sys.iobus = NoncoherentBus()
338    x86_sys.bridge = Bridge(delay='50ns')
339    x86_sys.bridge.master = x86_sys.iobus.slave
340    x86_sys.bridge.slave = x86_sys.membus.master
341    # Allow the bridge to pass through the IO APIC (two pages),
342    # everything in the IO address range up to the local APIC, and
343    # then the entire PCI address space and beyond
344    x86_sys.bridge.ranges = \
345        [
346        AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
347                  x86_sys.pc.south_bridge.io_apic.pio_addr +
348                  APIC_range_size - 1),
349        AddrRange(IO_address_space_base,
350                  interrupts_address_space_base - 1),
351        AddrRange(pci_config_address_space_base,
352                  Addr.max)
353        ]
354
355    # Create a bridge from the IO bus to the memory bus to allow access to
356    # the local APIC (two pages)
357    x86_sys.apicbridge = Bridge(delay='50ns')
358    x86_sys.apicbridge.slave = x86_sys.iobus.master
359    x86_sys.apicbridge.master = x86_sys.membus.slave
360    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
361                                           interrupts_address_space_base +
362                                           numCPUs * APIC_range_size
363                                           - 1)]
364
365    # connect the io bus
366    x86_sys.pc.attachIO(x86_sys.iobus)
367
368    x86_sys.system_port = x86_sys.membus.slave
369
370def connectX86RubySystem(x86_sys):
371    # North Bridge
372    x86_sys.iobus = NoncoherentBus()
373
374    # add the ide to the list of dma devices that later need to attach to
375    # dma controllers
376    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
377    x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports)
378
379
380def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
381                  Ruby = False):
382    if self == None:
383        self = X86System()
384
385    if not mdesc:
386        # generic system
387        mdesc = SysConfig()
388    self.readfile = mdesc.script()
389
390    self.mem_mode = mem_mode
391
392    # Physical memory
393    # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
394    # for various devices.  Hence, if the physical memory size is greater than
395    # 3GB, we need to split it into two parts.
396    excess_mem_size = \
397        convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
398    if excess_mem_size <= 0:
399        self.mem_ranges = [AddrRange(mdesc.mem())]
400    else:
401        warn("Physical memory size specified is %s which is greater than " \
402             "3GB.  Twice the number of memory controllers would be " \
403             "created."  % (mdesc.mem()))
404
405        self.mem_ranges = [AddrRange('3GB'),
406            AddrRange(Addr('4GB'), size = excess_mem_size)]
407
408    # Platform
409    self.pc = Pc()
410
411    # Create and connect the busses required by each memory system
412    if Ruby:
413        connectX86RubySystem(self)
414    else:
415        connectX86ClassicSystem(self, numCPUs)
416
417    self.intrctrl = IntrControl()
418
419    # Disks
420    disk0 = CowIdeDisk(driveID='master')
421    disk2 = CowIdeDisk(driveID='master')
422    disk0.childImage(mdesc.disk())
423    disk2.childImage(disk('linux-bigswap2.img'))
424    self.pc.south_bridge.ide.disks = [disk0, disk2]
425
426    # Add in a Bios information structure.
427    structures = [X86SMBiosBiosInformation()]
428    self.smbios_table.structures = structures
429
430    # Set up the Intel MP table
431    base_entries = []
432    ext_entries = []
433    for i in xrange(numCPUs):
434        bp = X86IntelMPProcessor(
435                local_apic_id = i,
436                local_apic_version = 0x14,
437                enable = True,
438                bootstrap = (i == 0))
439        base_entries.append(bp)
440    io_apic = X86IntelMPIOAPIC(
441            id = numCPUs,
442            version = 0x11,
443            enable = True,
444            address = 0xfec00000)
445    self.pc.south_bridge.io_apic.apic_id = io_apic.id
446    base_entries.append(io_apic)
447    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
448    base_entries.append(isa_bus)
449    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
450    base_entries.append(pci_bus)
451    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
452            subtractive_decode=True, parent_bus=1)
453    ext_entries.append(connect_busses)
454    pci_dev4_inta = X86IntelMPIOIntAssignment(
455            interrupt_type = 'INT',
456            polarity = 'ConformPolarity',
457            trigger = 'ConformTrigger',
458            source_bus_id = 1,
459            source_bus_irq = 0 + (4 << 2),
460            dest_io_apic_id = io_apic.id,
461            dest_io_apic_intin = 16)
462    base_entries.append(pci_dev4_inta)
463    def assignISAInt(irq, apicPin):
464        assign_8259_to_apic = X86IntelMPIOIntAssignment(
465                interrupt_type = 'ExtInt',
466                polarity = 'ConformPolarity',
467                trigger = 'ConformTrigger',
468                source_bus_id = 0,
469                source_bus_irq = irq,
470                dest_io_apic_id = io_apic.id,
471                dest_io_apic_intin = 0)
472        base_entries.append(assign_8259_to_apic)
473        assign_to_apic = X86IntelMPIOIntAssignment(
474                interrupt_type = 'INT',
475                polarity = 'ConformPolarity',
476                trigger = 'ConformTrigger',
477                source_bus_id = 0,
478                source_bus_irq = irq,
479                dest_io_apic_id = io_apic.id,
480                dest_io_apic_intin = apicPin)
481        base_entries.append(assign_to_apic)
482    assignISAInt(0, 2)
483    assignISAInt(1, 1)
484    for i in range(3, 15):
485        assignISAInt(i, i)
486    self.intel_mp_table.base_entries = base_entries
487    self.intel_mp_table.ext_entries = ext_entries
488
489def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
490                       Ruby = False):
491    self = LinuxX86System()
492
493    # Build up the x86 system and then specialize it for Linux
494    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
495
496    # We assume below that there's at least 1MB of memory. We'll require 2
497    # just to avoid corner cases.
498    phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
499    assert(phys_mem_size >= 0x200000)
500    assert(len(self.mem_ranges) <= 2)
501
502    entries = \
503       [
504        # Mark the first megabyte of memory as reserved
505        X86E820Entry(addr = 0, size = '639kB', range_type = 1),
506        X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
507        # Mark the rest of physical memory as available
508        X86E820Entry(addr = 0x100000,
509                size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
510                range_type = 1),
511        # Reserve the last 16kB of the 32-bit address space for the
512        # m5op interface
513        X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2),
514        ]
515
516    # In case the physical memory is greater than 3GB, we split it into two
517    # parts and add a separate e820 entry for the second part.  This entry
518    # starts at 0x100000000,  which is the first address after the space
519    # reserved for devices.
520    if len(self.mem_ranges) == 2:
521        entries.append(X86E820Entry(addr = 0x100000000,
522            size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
523
524    self.e820_table.entries = entries
525
526    # Command line
527    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
528                        'root=/dev/hda1'
529    self.kernel = binary('x86_64-vmlinux-2.6.22.9')
530    return self
531
532
533def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
534    self = Root(full_system = full_system)
535    self.testsys = testSystem
536    self.drivesys = driveSystem
537    self.etherlink = EtherLink()
538
539    if hasattr(testSystem, 'realview'):
540        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
541        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
542    elif hasattr(testSystem, 'tsunami'):
543        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
544        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
545    else:
546        fatal("Don't know how to connect these system together")
547
548    if dumpfile:
549        self.etherdump = EtherDump(file=dumpfile)
550        self.etherlink.dump = Parent.etherdump
551
552    return self
553