FSConfig.py revision 10118:5e1f04b4d5e4
111569Sgabor.dozsa@arm.com# Copyright (c) 2010-2012 ARM Limited 211569Sgabor.dozsa@arm.com# All rights reserved. 311569Sgabor.dozsa@arm.com# 411569Sgabor.dozsa@arm.com# The license below extends only to copyright in the software and shall 511569Sgabor.dozsa@arm.com# not be construed as granting a license to any other intellectual 611569Sgabor.dozsa@arm.com# property including but not limited to intellectual property relating 711569Sgabor.dozsa@arm.com# to a hardware implementation of the functionality of the software 811569Sgabor.dozsa@arm.com# licensed hereunder. You may use the software subject to the license 911569Sgabor.dozsa@arm.com# terms below provided that you ensure that this notice is replicated 1011569Sgabor.dozsa@arm.com# unmodified and in its entirety in all distributions of the software, 1111569Sgabor.dozsa@arm.com# modified or unmodified, in source code or in binary form. 1211569Sgabor.dozsa@arm.com# 1311569Sgabor.dozsa@arm.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 1411569Sgabor.dozsa@arm.com# Copyright (c) 2006-2008 The Regents of The University of Michigan 1511569Sgabor.dozsa@arm.com# All rights reserved. 1611569Sgabor.dozsa@arm.com# 1711569Sgabor.dozsa@arm.com# Redistribution and use in source and binary forms, with or without 1811569Sgabor.dozsa@arm.com# modification, are permitted provided that the following conditions are 1911569Sgabor.dozsa@arm.com# met: redistributions of source code must retain the above copyright 2011569Sgabor.dozsa@arm.com# notice, this list of conditions and the following disclaimer; 2111569Sgabor.dozsa@arm.com# redistributions in binary form must reproduce the above copyright 2211569Sgabor.dozsa@arm.com# notice, this list of conditions and the following disclaimer in the 2311569Sgabor.dozsa@arm.com# documentation and/or other materials provided with the distribution; 2411569Sgabor.dozsa@arm.com# neither the name of the copyright holders nor the names of its 2511569Sgabor.dozsa@arm.com# contributors may be used to endorse or promote products derived from 2611569Sgabor.dozsa@arm.com# this software without specific prior written permission. 2711569Sgabor.dozsa@arm.com# 2811569Sgabor.dozsa@arm.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2911569Sgabor.dozsa@arm.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3011569Sgabor.dozsa@arm.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3111569Sgabor.dozsa@arm.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3211569Sgabor.dozsa@arm.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3311569Sgabor.dozsa@arm.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3411569Sgabor.dozsa@arm.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3511569Sgabor.dozsa@arm.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3611569Sgabor.dozsa@arm.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3711569Sgabor.dozsa@arm.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3811569Sgabor.dozsa@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3911569Sgabor.dozsa@arm.com# 4011569Sgabor.dozsa@arm.com# Authors: Kevin Lim 4111569Sgabor.dozsa@arm.com 4211569Sgabor.dozsa@arm.comfrom m5.objects import * 4311569Sgabor.dozsa@arm.comfrom Benchmarks import * 4411569Sgabor.dozsa@arm.comfrom m5.util import * 4511630Sgabor.dozsa@arm.com 4611569Sgabor.dozsa@arm.comclass CowIdeDisk(IdeDisk): 4711569Sgabor.dozsa@arm.com image = CowDiskImage(child=RawDiskImage(read_only=True), 4811569Sgabor.dozsa@arm.com read_only=False) 4911569Sgabor.dozsa@arm.com 5011569Sgabor.dozsa@arm.com def childImage(self, ci): 5111569Sgabor.dozsa@arm.com self.image.child.image_file = ci 5211569Sgabor.dozsa@arm.com 5311569Sgabor.dozsa@arm.comclass MemBus(CoherentBus): 5411569Sgabor.dozsa@arm.com badaddr_responder = BadAddr() 5511569Sgabor.dozsa@arm.com default = Self.badaddr_responder.pio 5611569Sgabor.dozsa@arm.com 5711569Sgabor.dozsa@arm.com 5811569Sgabor.dozsa@arm.comdef makeLinuxAlphaSystem(mem_mode, mdesc = None, ruby = False): 5911569Sgabor.dozsa@arm.com 6011569Sgabor.dozsa@arm.com class BaseTsunami(Tsunami): 6111569Sgabor.dozsa@arm.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 6211569Sgabor.dozsa@arm.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 6311569Sgabor.dozsa@arm.com pci_func=0, pci_dev=0, pci_bus=0) 6411569Sgabor.dozsa@arm.com 6511569Sgabor.dozsa@arm.com self = LinuxAlphaSystem() 6611569Sgabor.dozsa@arm.com if not mdesc: 6711569Sgabor.dozsa@arm.com # generic system 6811569Sgabor.dozsa@arm.com mdesc = SysConfig() 6911569Sgabor.dozsa@arm.com self.readfile = mdesc.script() 7011569Sgabor.dozsa@arm.com 7111569Sgabor.dozsa@arm.com self.tsunami = BaseTsunami() 7211569Sgabor.dozsa@arm.com 7311569Sgabor.dozsa@arm.com # Create the io bus to connect all device ports 7411569Sgabor.dozsa@arm.com self.iobus = NoncoherentBus() 7511569Sgabor.dozsa@arm.com self.tsunami.attachIO(self.iobus) 7611569Sgabor.dozsa@arm.com 7711569Sgabor.dozsa@arm.com self.tsunami.ide.pio = self.iobus.master 7811569Sgabor.dozsa@arm.com self.tsunami.ide.config = self.iobus.master 7911569Sgabor.dozsa@arm.com 8011569Sgabor.dozsa@arm.com self.tsunami.ethernet.pio = self.iobus.master 8111569Sgabor.dozsa@arm.com self.tsunami.ethernet.config = self.iobus.master 8211569Sgabor.dozsa@arm.com 8311569Sgabor.dozsa@arm.com if ruby: 8411569Sgabor.dozsa@arm.com # Store the dma devices for later connection to dma ruby ports. 8511569Sgabor.dozsa@arm.com # Append an underscore to dma_ports to avoid the SimObjectVector check. 8611569Sgabor.dozsa@arm.com self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma] 8711569Sgabor.dozsa@arm.com else: 8811569Sgabor.dozsa@arm.com self.membus = MemBus() 8911569Sgabor.dozsa@arm.com 9011569Sgabor.dozsa@arm.com # By default the bridge responds to all addresses above the I/O 9111569Sgabor.dozsa@arm.com # base address (including the PCI config space) 9211569Sgabor.dozsa@arm.com IO_address_space_base = 0x80000000000 9311569Sgabor.dozsa@arm.com self.bridge = Bridge(delay='50ns', 9411569Sgabor.dozsa@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 9511569Sgabor.dozsa@arm.com self.bridge.master = self.iobus.slave 9611569Sgabor.dozsa@arm.com self.bridge.slave = self.membus.master 9711569Sgabor.dozsa@arm.com 9811569Sgabor.dozsa@arm.com self.tsunami.ide.dma = self.iobus.slave 9911569Sgabor.dozsa@arm.com self.tsunami.ethernet.dma = self.iobus.slave 10011569Sgabor.dozsa@arm.com 10111569Sgabor.dozsa@arm.com self.system_port = self.membus.slave 10211630Sgabor.dozsa@arm.com 10311630Sgabor.dozsa@arm.com self.mem_ranges = [AddrRange(mdesc.mem())] 10411630Sgabor.dozsa@arm.com self.disk0 = CowIdeDisk(driveID='master') 10511630Sgabor.dozsa@arm.com self.disk2 = CowIdeDisk(driveID='master') 10611630Sgabor.dozsa@arm.com self.disk0.childImage(mdesc.disk()) 10711630Sgabor.dozsa@arm.com self.disk2.childImage(disk('linux-bigswap2.img')) 10811630Sgabor.dozsa@arm.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 10911630Sgabor.dozsa@arm.com read_only = True)) 11011630Sgabor.dozsa@arm.com self.intrctrl = IntrControl() 11111630Sgabor.dozsa@arm.com self.mem_mode = mem_mode 11211630Sgabor.dozsa@arm.com self.terminal = Terminal() 11311630Sgabor.dozsa@arm.com self.kernel = binary('vmlinux') 11411630Sgabor.dozsa@arm.com self.pal = binary('ts_osfpal') 11511630Sgabor.dozsa@arm.com self.console = binary('console') 11611630Sgabor.dozsa@arm.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 11711630Sgabor.dozsa@arm.com 11811630Sgabor.dozsa@arm.com return self 11911630Sgabor.dozsa@arm.com 12011630Sgabor.dozsa@arm.comdef makeSparcSystem(mem_mode, mdesc = None): 12111630Sgabor.dozsa@arm.com # Constants from iob.cc and uart8250.cc 12211630Sgabor.dozsa@arm.com iob_man_addr = 0x9800000000 12311630Sgabor.dozsa@arm.com uart_pio_size = 8 12411630Sgabor.dozsa@arm.com 12511630Sgabor.dozsa@arm.com class CowMmDisk(MmDisk): 12611630Sgabor.dozsa@arm.com image = CowDiskImage(child=RawDiskImage(read_only=True), 12711630Sgabor.dozsa@arm.com read_only=False) 12811630Sgabor.dozsa@arm.com 12911630Sgabor.dozsa@arm.com def childImage(self, ci): 13011630Sgabor.dozsa@arm.com self.image.child.image_file = ci 13111630Sgabor.dozsa@arm.com 13211630Sgabor.dozsa@arm.com self = SparcSystem() 13311630Sgabor.dozsa@arm.com if not mdesc: 13411630Sgabor.dozsa@arm.com # generic system 13511630Sgabor.dozsa@arm.com mdesc = SysConfig() 13611630Sgabor.dozsa@arm.com self.readfile = mdesc.script() 13711630Sgabor.dozsa@arm.com self.iobus = NoncoherentBus() 13811630Sgabor.dozsa@arm.com self.membus = MemBus() 13911630Sgabor.dozsa@arm.com self.bridge = Bridge(delay='50ns') 14011630Sgabor.dozsa@arm.com self.t1000 = T1000() 14111630Sgabor.dozsa@arm.com self.t1000.attachOnChipIO(self.membus) 14211630Sgabor.dozsa@arm.com self.t1000.attachIO(self.iobus) 14311630Sgabor.dozsa@arm.com self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'), 14411630Sgabor.dozsa@arm.com AddrRange(Addr('2GB'), size ='256MB')] 14511630Sgabor.dozsa@arm.com self.bridge.master = self.iobus.slave 14611630Sgabor.dozsa@arm.com self.bridge.slave = self.membus.master 14711630Sgabor.dozsa@arm.com self.rom.port = self.membus.master 14811630Sgabor.dozsa@arm.com self.nvram.port = self.membus.master 14911630Sgabor.dozsa@arm.com self.hypervisor_desc.port = self.membus.master 15011630Sgabor.dozsa@arm.com self.partition_desc.port = self.membus.master 15111630Sgabor.dozsa@arm.com self.intrctrl = IntrControl() 15211630Sgabor.dozsa@arm.com self.disk0 = CowMmDisk() 15311630Sgabor.dozsa@arm.com self.disk0.childImage(disk('disk.s10hw2')) 15411630Sgabor.dozsa@arm.com self.disk0.pio = self.iobus.master 15511630Sgabor.dozsa@arm.com 15611630Sgabor.dozsa@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 15711630Sgabor.dozsa@arm.com # for them. The remaining IO range is rather fragmented, so poke 15811630Sgabor.dozsa@arm.com # holes for the iob and partition descriptors etc. 15911630Sgabor.dozsa@arm.com self.bridge.ranges = \ 16011630Sgabor.dozsa@arm.com [ 16111630Sgabor.dozsa@arm.com AddrRange(self.t1000.puart0.pio_addr, 16211630Sgabor.dozsa@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 16311630Sgabor.dozsa@arm.com AddrRange(self.disk0.pio_addr, 16411630Sgabor.dozsa@arm.com self.t1000.fake_jbi.pio_addr + 16511630Sgabor.dozsa@arm.com self.t1000.fake_jbi.pio_size - 1), 16611630Sgabor.dozsa@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 16711630Sgabor.dozsa@arm.com iob_man_addr - 1), 16811630Sgabor.dozsa@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 16911569Sgabor.dozsa@arm.com self.t1000.fake_ssi.pio_addr + 17011569Sgabor.dozsa@arm.com self.t1000.fake_ssi.pio_size - 1), 17111569Sgabor.dozsa@arm.com AddrRange(self.t1000.hvuart.pio_addr, 17211630Sgabor.dozsa@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 17311630Sgabor.dozsa@arm.com ] 17411569Sgabor.dozsa@arm.com self.reset_bin = binary('reset_new.bin') 17511630Sgabor.dozsa@arm.com self.hypervisor_bin = binary('q_new.bin') 17611630Sgabor.dozsa@arm.com self.openboot_bin = binary('openboot_new.bin') 17711630Sgabor.dozsa@arm.com self.nvram_bin = binary('nvram1') 17811569Sgabor.dozsa@arm.com self.hypervisor_desc_bin = binary('1up-hv.bin') 17911630Sgabor.dozsa@arm.com self.partition_desc_bin = binary('1up-md.bin') 18011569Sgabor.dozsa@arm.com 18111630Sgabor.dozsa@arm.com self.system_port = self.membus.slave 18211630Sgabor.dozsa@arm.com 18311569Sgabor.dozsa@arm.com return self 18411630Sgabor.dozsa@arm.com 18511569Sgabor.dozsa@arm.comdef makeArmSystem(mem_mode, machine_type, mdesc = None, 18611630Sgabor.dozsa@arm.com dtb_filename = None, bare_metal=False): 18711630Sgabor.dozsa@arm.com assert machine_type 18811630Sgabor.dozsa@arm.com 18911569Sgabor.dozsa@arm.com if bare_metal: 19011630Sgabor.dozsa@arm.com self = ArmSystem() 19111630Sgabor.dozsa@arm.com else: 19211630Sgabor.dozsa@arm.com self = LinuxArmSystem() 19311630Sgabor.dozsa@arm.com 19411630Sgabor.dozsa@arm.com if not mdesc: 19511630Sgabor.dozsa@arm.com # generic system 19611630Sgabor.dozsa@arm.com mdesc = SysConfig() 19711630Sgabor.dozsa@arm.com 19811630Sgabor.dozsa@arm.com self.readfile = mdesc.script() 19911630Sgabor.dozsa@arm.com self.iobus = NoncoherentBus() 20011569Sgabor.dozsa@arm.com self.membus = MemBus() 20111569Sgabor.dozsa@arm.com self.membus.badaddr_responder.warn_access = "warn" 20211569Sgabor.dozsa@arm.com self.bridge = Bridge(delay='50ns') 20311569Sgabor.dozsa@arm.com self.bridge.master = self.iobus.slave 20411569Sgabor.dozsa@arm.com self.bridge.slave = self.membus.master 20511569Sgabor.dozsa@arm.com 20611569Sgabor.dozsa@arm.com self.mem_mode = mem_mode 20711569Sgabor.dozsa@arm.com 20811569Sgabor.dozsa@arm.com if machine_type == "RealView_PBX": 20911569Sgabor.dozsa@arm.com self.realview = RealViewPBX() 21011569Sgabor.dozsa@arm.com elif machine_type == "RealView_EB": 21111569Sgabor.dozsa@arm.com self.realview = RealViewEB() 21211569Sgabor.dozsa@arm.com elif machine_type == "VExpress_ELT": 21311569Sgabor.dozsa@arm.com self.realview = VExpress_ELT() 21411569Sgabor.dozsa@arm.com elif machine_type == "VExpress_EMM": 21511569Sgabor.dozsa@arm.com self.realview = VExpress_EMM() 21611569Sgabor.dozsa@arm.com elif machine_type == "VExpress_EMM64": 21711630Sgabor.dozsa@arm.com self.realview = VExpress_EMM64() 21811630Sgabor.dozsa@arm.com else: 21911630Sgabor.dozsa@arm.com print "Unknown Machine Type" 22011630Sgabor.dozsa@arm.com sys.exit(1) 22111630Sgabor.dozsa@arm.com 22211630Sgabor.dozsa@arm.com self.cf0 = CowIdeDisk(driveID='master') 22311630Sgabor.dozsa@arm.com self.cf0.childImage(mdesc.disk()) 22411630Sgabor.dozsa@arm.com # default to an IDE controller rather than a CF one 22511630Sgabor.dozsa@arm.com # assuming we've got one; EMM64 is an exception for the moment 22611630Sgabor.dozsa@arm.com if machine_type != "VExpress_EMM64": 22711630Sgabor.dozsa@arm.com try: 22811630Sgabor.dozsa@arm.com self.realview.ide.disks = [self.cf0] 22911630Sgabor.dozsa@arm.com except: 23011630Sgabor.dozsa@arm.com self.realview.cf_ctrl.disks = [self.cf0] 23111630Sgabor.dozsa@arm.com else: 23211630Sgabor.dozsa@arm.com self.realview.cf_ctrl.disks = [self.cf0] 23311630Sgabor.dozsa@arm.com 23411630Sgabor.dozsa@arm.com if bare_metal: 23511630Sgabor.dozsa@arm.com # EOT character on UART will end the simulation 23611630Sgabor.dozsa@arm.com self.realview.uart.end_on_eot = True 23711630Sgabor.dozsa@arm.com self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 23811630Sgabor.dozsa@arm.com size = mdesc.mem())] 23911630Sgabor.dozsa@arm.com else: 24011630Sgabor.dozsa@arm.com self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 24111630Sgabor.dozsa@arm.com if dtb_filename: 24211630Sgabor.dozsa@arm.com self.dtb_filename = binary(dtb_filename) 24311630Sgabor.dozsa@arm.com self.machine_type = machine_type 24411630Sgabor.dozsa@arm.com if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): 24511630Sgabor.dozsa@arm.com print "The currently selected ARM platforms doesn't support" 24611630Sgabor.dozsa@arm.com print " the amount of DRAM you've selected. Please try" 24711630Sgabor.dozsa@arm.com print " another platform" 24811630Sgabor.dozsa@arm.com sys.exit(1) 24911630Sgabor.dozsa@arm.com 25011630Sgabor.dozsa@arm.com # Ensure that writes to the UART actually go out early in the boot 25111630Sgabor.dozsa@arm.com boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \ 25211630Sgabor.dozsa@arm.com 'lpj=19988480 norandmaps rw loglevel=8 ' + \ 25311630Sgabor.dozsa@arm.com 'mem=%s root=/dev/sda1' % mdesc.mem() 25411630Sgabor.dozsa@arm.com 25511630Sgabor.dozsa@arm.com self.mem_ranges = [AddrRange(self.realview.mem_start_addr, 256 size = mdesc.mem())] 257 self.realview.setupBootLoader(self.membus, self, binary) 258 self.gic_cpu_addr = self.realview.gic.cpu_addr 259 self.flags_addr = self.realview.realview_io.pio_addr + 0x30 260 261 if mdesc.disk().lower().count('android'): 262 boot_flags += " init=/init " 263 self.boot_osflags = boot_flags 264 self.realview.attachOnChipIO(self.membus, self.bridge) 265 self.realview.attachIO(self.iobus) 266 self.intrctrl = IntrControl() 267 self.terminal = Terminal() 268 self.vncserver = VncServer() 269 270 self.system_port = self.membus.slave 271 272 return self 273 274 275def makeLinuxMipsSystem(mem_mode, mdesc = None): 276 class BaseMalta(Malta): 277 ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 278 ide = IdeController(disks=[Parent.disk0, Parent.disk2], 279 pci_func=0, pci_dev=0, pci_bus=0) 280 281 self = LinuxMipsSystem() 282 if not mdesc: 283 # generic system 284 mdesc = SysConfig() 285 self.readfile = mdesc.script() 286 self.iobus = NoncoherentBus() 287 self.membus = MemBus() 288 self.bridge = Bridge(delay='50ns') 289 self.mem_ranges = [AddrRange('1GB')] 290 self.bridge.master = self.iobus.slave 291 self.bridge.slave = self.membus.master 292 self.disk0 = CowIdeDisk(driveID='master') 293 self.disk2 = CowIdeDisk(driveID='master') 294 self.disk0.childImage(mdesc.disk()) 295 self.disk2.childImage(disk('linux-bigswap2.img')) 296 self.malta = BaseMalta() 297 self.malta.attachIO(self.iobus) 298 self.malta.ide.pio = self.iobus.master 299 self.malta.ide.config = self.iobus.master 300 self.malta.ide.dma = self.iobus.slave 301 self.malta.ethernet.pio = self.iobus.master 302 self.malta.ethernet.config = self.iobus.master 303 self.malta.ethernet.dma = self.iobus.slave 304 self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 305 read_only = True)) 306 self.intrctrl = IntrControl() 307 self.mem_mode = mem_mode 308 self.terminal = Terminal() 309 self.kernel = binary('mips/vmlinux') 310 self.console = binary('mips/console') 311 self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 312 313 self.system_port = self.membus.slave 314 315 return self 316 317def x86IOAddress(port): 318 IO_address_space_base = 0x8000000000000000 319 return IO_address_space_base + port 320 321def connectX86ClassicSystem(x86_sys, numCPUs): 322 # Constants similar to x86_traits.hh 323 IO_address_space_base = 0x8000000000000000 324 pci_config_address_space_base = 0xc000000000000000 325 interrupts_address_space_base = 0xa000000000000000 326 APIC_range_size = 1 << 12; 327 328 x86_sys.membus = MemBus() 329 330 # North Bridge 331 x86_sys.iobus = NoncoherentBus() 332 x86_sys.bridge = Bridge(delay='50ns') 333 x86_sys.bridge.master = x86_sys.iobus.slave 334 x86_sys.bridge.slave = x86_sys.membus.master 335 # Allow the bridge to pass through the IO APIC (two pages), 336 # everything in the IO address range up to the local APIC, and 337 # then the entire PCI address space and beyond 338 x86_sys.bridge.ranges = \ 339 [ 340 AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 341 x86_sys.pc.south_bridge.io_apic.pio_addr + 342 APIC_range_size - 1), 343 AddrRange(IO_address_space_base, 344 interrupts_address_space_base - 1), 345 AddrRange(pci_config_address_space_base, 346 Addr.max) 347 ] 348 349 # Create a bridge from the IO bus to the memory bus to allow access to 350 # the local APIC (two pages) 351 x86_sys.apicbridge = Bridge(delay='50ns') 352 x86_sys.apicbridge.slave = x86_sys.iobus.master 353 x86_sys.apicbridge.master = x86_sys.membus.slave 354 x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base, 355 interrupts_address_space_base + 356 numCPUs * APIC_range_size 357 - 1)] 358 359 # connect the io bus 360 x86_sys.pc.attachIO(x86_sys.iobus) 361 362 x86_sys.system_port = x86_sys.membus.slave 363 364def connectX86RubySystem(x86_sys): 365 # North Bridge 366 x86_sys.iobus = NoncoherentBus() 367 368 # add the ide to the list of dma devices that later need to attach to 369 # dma controllers 370 x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma] 371 x86_sys.pc.attachIO(x86_sys.iobus, x86_sys._dma_ports) 372 373 374def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, 375 Ruby = False): 376 if self == None: 377 self = X86System() 378 379 if not mdesc: 380 # generic system 381 mdesc = SysConfig() 382 self.readfile = mdesc.script() 383 384 self.mem_mode = mem_mode 385 386 # Physical memory 387 # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved 388 # for various devices. Hence, if the physical memory size is greater than 389 # 3GB, we need to split it into two parts. 390 excess_mem_size = \ 391 convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB') 392 if excess_mem_size <= 0: 393 self.mem_ranges = [AddrRange(mdesc.mem())] 394 else: 395 warn("Physical memory size specified is %s which is greater than " \ 396 "3GB. Twice the number of memory controllers would be " \ 397 "created." % (mdesc.mem())) 398 399 self.mem_ranges = [AddrRange('3GB'), 400 AddrRange(Addr('4GB'), size = excess_mem_size)] 401 402 # Platform 403 self.pc = Pc() 404 405 # Create and connect the busses required by each memory system 406 if Ruby: 407 connectX86RubySystem(self) 408 else: 409 connectX86ClassicSystem(self, numCPUs) 410 411 self.intrctrl = IntrControl() 412 413 # Disks 414 disk0 = CowIdeDisk(driveID='master') 415 disk2 = CowIdeDisk(driveID='master') 416 disk0.childImage(mdesc.disk()) 417 disk2.childImage(disk('linux-bigswap2.img')) 418 self.pc.south_bridge.ide.disks = [disk0, disk2] 419 420 # Add in a Bios information structure. 421 structures = [X86SMBiosBiosInformation()] 422 self.smbios_table.structures = structures 423 424 # Set up the Intel MP table 425 base_entries = [] 426 ext_entries = [] 427 for i in xrange(numCPUs): 428 bp = X86IntelMPProcessor( 429 local_apic_id = i, 430 local_apic_version = 0x14, 431 enable = True, 432 bootstrap = (i == 0)) 433 base_entries.append(bp) 434 io_apic = X86IntelMPIOAPIC( 435 id = numCPUs, 436 version = 0x11, 437 enable = True, 438 address = 0xfec00000) 439 self.pc.south_bridge.io_apic.apic_id = io_apic.id 440 base_entries.append(io_apic) 441 isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 442 base_entries.append(isa_bus) 443 pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 444 base_entries.append(pci_bus) 445 connect_busses = X86IntelMPBusHierarchy(bus_id=0, 446 subtractive_decode=True, parent_bus=1) 447 ext_entries.append(connect_busses) 448 pci_dev4_inta = X86IntelMPIOIntAssignment( 449 interrupt_type = 'INT', 450 polarity = 'ConformPolarity', 451 trigger = 'ConformTrigger', 452 source_bus_id = 1, 453 source_bus_irq = 0 + (4 << 2), 454 dest_io_apic_id = io_apic.id, 455 dest_io_apic_intin = 16) 456 base_entries.append(pci_dev4_inta) 457 def assignISAInt(irq, apicPin): 458 assign_8259_to_apic = X86IntelMPIOIntAssignment( 459 interrupt_type = 'ExtInt', 460 polarity = 'ConformPolarity', 461 trigger = 'ConformTrigger', 462 source_bus_id = 0, 463 source_bus_irq = irq, 464 dest_io_apic_id = io_apic.id, 465 dest_io_apic_intin = 0) 466 base_entries.append(assign_8259_to_apic) 467 assign_to_apic = X86IntelMPIOIntAssignment( 468 interrupt_type = 'INT', 469 polarity = 'ConformPolarity', 470 trigger = 'ConformTrigger', 471 source_bus_id = 0, 472 source_bus_irq = irq, 473 dest_io_apic_id = io_apic.id, 474 dest_io_apic_intin = apicPin) 475 base_entries.append(assign_to_apic) 476 assignISAInt(0, 2) 477 assignISAInt(1, 1) 478 for i in range(3, 15): 479 assignISAInt(i, i) 480 self.intel_mp_table.base_entries = base_entries 481 self.intel_mp_table.ext_entries = ext_entries 482 483def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, 484 Ruby = False): 485 self = LinuxX86System() 486 487 # Build up the x86 system and then specialize it for Linux 488 makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 489 490 # We assume below that there's at least 1MB of memory. We'll require 2 491 # just to avoid corner cases. 492 phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges)) 493 assert(phys_mem_size >= 0x200000) 494 assert(len(self.mem_ranges) <= 2) 495 496 entries = \ 497 [ 498 # Mark the first megabyte of memory as reserved 499 X86E820Entry(addr = 0, size = '639kB', range_type = 1), 500 X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2), 501 # Mark the rest of physical memory as available 502 X86E820Entry(addr = 0x100000, 503 size = '%dB' % (self.mem_ranges[0].size() - 0x100000), 504 range_type = 1), 505 # Reserve the last 16kB of the 32-bit address space for the 506 # m5op interface 507 X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2), 508 ] 509 510 # In case the physical memory is greater than 3GB, we split it into two 511 # parts and add a separate e820 entry for the second part. This entry 512 # starts at 0x100000000, which is the first address after the space 513 # reserved for devices. 514 if len(self.mem_ranges) == 2: 515 entries.append(X86E820Entry(addr = 0x100000000, 516 size = '%dB' % (self.mem_ranges[1].size()), range_type = 1)) 517 518 self.e820_table.entries = entries 519 520 # Command line 521 self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 522 'root=/dev/hda1' 523 self.kernel = binary('x86_64-vmlinux-2.6.22.9') 524 return self 525 526 527def makeDualRoot(full_system, testSystem, driveSystem, dumpfile): 528 self = Root(full_system = full_system) 529 self.testsys = testSystem 530 self.drivesys = driveSystem 531 self.etherlink = EtherLink() 532 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 533 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 534 535 if hasattr(testSystem, 'realview'): 536 self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 537 self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 538 elif hasattr(testSystem, 'tsunami'): 539 self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 540 self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 541 else: 542 fatal("Don't know how to connect these system together") 543 544 if dumpfile: 545 self.etherdump = EtherDump(file=dumpfile) 546 self.etherlink.dump = Parent.etherdump 547 548 return self 549