FSConfig.py revision 10071:6234ea863e76 
1# Copyright (c) 2010-2012 ARM Limited
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13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
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39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import *
45
46class CowIdeDisk(IdeDisk):
47    image = CowDiskImage(child=RawDiskImage(read_only=True),
48                         read_only=False)
49
50    def childImage(self, ci):
51        self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54    badaddr_responder = BadAddr()
55    default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59    IO_address_space_base = 0x80000000000
60    class BaseTsunami(Tsunami):
61        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63                            pci_func=0, pci_dev=0, pci_bus=0)
64
65    self = LinuxAlphaSystem()
66    if not mdesc:
67        # generic system
68        mdesc = SysConfig()
69    self.readfile = mdesc.script()
70    self.iobus = NoncoherentBus()
71    self.membus = MemBus()
72    # By default the bridge responds to all addresses above the I/O
73    # base address (including the PCI config space)
74    self.bridge = Bridge(delay='50ns',
75                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
76    self.mem_ranges = [AddrRange(mdesc.mem())]
77    self.bridge.master = self.iobus.slave
78    self.bridge.slave = self.membus.master
79    self.disk0 = CowIdeDisk(driveID='master')
80    self.disk2 = CowIdeDisk(driveID='master')
81    self.disk0.childImage(mdesc.disk())
82    self.disk2.childImage(disk('linux-bigswap2.img'))
83    self.tsunami = BaseTsunami()
84    self.tsunami.attachIO(self.iobus)
85    self.tsunami.ide.pio = self.iobus.master
86    self.tsunami.ide.config = self.iobus.master
87    self.tsunami.ide.dma = self.iobus.slave
88    self.tsunami.ethernet.pio = self.iobus.master
89    self.tsunami.ethernet.config = self.iobus.master
90    self.tsunami.ethernet.dma = self.iobus.slave
91    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
92                                               read_only = True))
93    self.intrctrl = IntrControl()
94    self.mem_mode = mem_mode
95    self.terminal = Terminal()
96    self.kernel = binary('vmlinux')
97    self.pal = binary('ts_osfpal')
98    self.console = binary('console')
99    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
100
101    self.system_port = self.membus.slave
102
103    return self
104
105def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
106    class BaseTsunami(Tsunami):
107        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
108        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
109                            pci_func=0, pci_dev=0, pci_bus=0)
110    self = LinuxAlphaSystem()
111    self.mem_ranges = [AddrRange(mdesc.mem())]
112    if not mdesc:
113        # generic system
114        mdesc = SysConfig()
115    self.readfile = mdesc.script()
116
117    # Create pio bus to connect all device pio ports to rubymem's pio port
118    self.piobus = NoncoherentBus()
119
120    self.disk0 = CowIdeDisk(driveID='master')
121    self.disk2 = CowIdeDisk(driveID='master')
122    self.disk0.childImage(mdesc.disk())
123    self.disk2.childImage(disk('linux-bigswap2.img'))
124    self.tsunami = BaseTsunami()
125    self.tsunami.attachIO(self.piobus)
126    self.tsunami.ide.pio = self.piobus.master
127    self.tsunami.ide.config = self.piobus.master
128    self.tsunami.ethernet.pio = self.piobus.master
129    self.tsunami.ethernet.config = self.piobus.master
130
131    #
132    # Store the dma devices for later connection to dma ruby ports.
133    # Append an underscore to dma_devices to avoid the SimObjectVector check.
134    #
135    self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
136
137    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
138                                               read_only = True))
139    self.intrctrl = IntrControl()
140    self.mem_mode = mem_mode
141    self.terminal = Terminal()
142    self.kernel = binary('vmlinux')
143    self.pal = binary('ts_osfpal')
144    self.console = binary('console')
145    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
146
147    return self
148
149def makeSparcSystem(mem_mode, mdesc = None):
150    # Constants from iob.cc and uart8250.cc
151    iob_man_addr = 0x9800000000
152    uart_pio_size = 8
153
154    class CowMmDisk(MmDisk):
155        image = CowDiskImage(child=RawDiskImage(read_only=True),
156                             read_only=False)
157
158        def childImage(self, ci):
159            self.image.child.image_file = ci
160
161    self = SparcSystem()
162    if not mdesc:
163        # generic system
164        mdesc = SysConfig()
165    self.readfile = mdesc.script()
166    self.iobus = NoncoherentBus()
167    self.membus = MemBus()
168    self.bridge = Bridge(delay='50ns')
169    self.t1000 = T1000()
170    self.t1000.attachOnChipIO(self.membus)
171    self.t1000.attachIO(self.iobus)
172    self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
173                       AddrRange(Addr('2GB'), size ='256MB')]
174    self.bridge.master = self.iobus.slave
175    self.bridge.slave = self.membus.master
176    self.rom.port = self.membus.master
177    self.nvram.port = self.membus.master
178    self.hypervisor_desc.port = self.membus.master
179    self.partition_desc.port = self.membus.master
180    self.intrctrl = IntrControl()
181    self.disk0 = CowMmDisk()
182    self.disk0.childImage(disk('disk.s10hw2'))
183    self.disk0.pio = self.iobus.master
184
185    # The puart0 and hvuart are placed on the IO bus, so create ranges
186    # for them. The remaining IO range is rather fragmented, so poke
187    # holes for the iob and partition descriptors etc.
188    self.bridge.ranges = \
189        [
190        AddrRange(self.t1000.puart0.pio_addr,
191                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
192        AddrRange(self.disk0.pio_addr,
193                  self.t1000.fake_jbi.pio_addr +
194                  self.t1000.fake_jbi.pio_size - 1),
195        AddrRange(self.t1000.fake_clk.pio_addr,
196                  iob_man_addr - 1),
197        AddrRange(self.t1000.fake_l2_1.pio_addr,
198                  self.t1000.fake_ssi.pio_addr +
199                  self.t1000.fake_ssi.pio_size - 1),
200        AddrRange(self.t1000.hvuart.pio_addr,
201                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
202        ]
203    self.reset_bin = binary('reset_new.bin')
204    self.hypervisor_bin = binary('q_new.bin')
205    self.openboot_bin = binary('openboot_new.bin')
206    self.nvram_bin = binary('nvram1')
207    self.hypervisor_desc_bin = binary('1up-hv.bin')
208    self.partition_desc_bin = binary('1up-md.bin')
209
210    self.system_port = self.membus.slave
211
212    return self
213
214def makeArmSystem(mem_mode, machine_type, mdesc = None,
215                  dtb_filename = None, bare_metal=False):
216    assert machine_type
217
218    if bare_metal:
219        self = ArmSystem()
220    else:
221        self = LinuxArmSystem()
222
223    if not mdesc:
224        # generic system
225        mdesc = SysConfig()
226
227    self.readfile = mdesc.script()
228    self.iobus = NoncoherentBus()
229    self.membus = MemBus()
230    self.membus.badaddr_responder.warn_access = "warn"
231    self.bridge = Bridge(delay='50ns')
232    self.bridge.master = self.iobus.slave
233    self.bridge.slave = self.membus.master
234
235    self.mem_mode = mem_mode
236
237    if machine_type == "RealView_PBX":
238        self.realview = RealViewPBX()
239    elif machine_type == "RealView_EB":
240        self.realview = RealViewEB()
241    elif machine_type == "VExpress_ELT":
242        self.realview = VExpress_ELT()
243    elif machine_type == "VExpress_EMM":
244        self.realview = VExpress_EMM()
245    elif machine_type == "VExpress_EMM64":
246        self.realview = VExpress_EMM64()
247    else:
248        print "Unknown Machine Type"
249        sys.exit(1)
250
251    self.cf0 = CowIdeDisk(driveID='master')
252    self.cf0.childImage(mdesc.disk())
253    # default to an IDE controller rather than a CF one
254    # assuming we've got one; EMM64 is an exception for the moment
255    if machine_type != "VExpress_EMM64":
256        try:
257            self.realview.ide.disks = [self.cf0]
258        except:
259            self.realview.cf_ctrl.disks = [self.cf0]
260    else:
261        self.realview.cf_ctrl.disks = [self.cf0]
262
263    if bare_metal:
264        # EOT character on UART will end the simulation
265        self.realview.uart.end_on_eot = True
266        self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
267                                     size = mdesc.mem())]
268    else:
269        self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
270        if dtb_filename:
271            self.dtb_filename = binary(dtb_filename)
272        self.machine_type = machine_type
273        if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
274            print "The currently selected ARM platforms doesn't support"
275            print " the amount of DRAM you've selected. Please try"
276            print " another platform"
277            sys.exit(1)
278
279        # Ensure that writes to the UART actually go out early in the boot
280        boot_flags = 'earlyprintk=pl011,0x1c090000 console=ttyAMA0 ' + \
281                     'lpj=19988480 norandmaps rw loglevel=8 ' + \
282                     'mem=%s root=/dev/sda1' % mdesc.mem()
283
284        self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
285                                     size = mdesc.mem())]
286        self.realview.setupBootLoader(self.membus, self, binary)
287        self.gic_cpu_addr = self.realview.gic.cpu_addr
288        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
289
290        if mdesc.disk().lower().count('android'):
291            boot_flags += " init=/init "
292        self.boot_osflags = boot_flags
293    self.realview.attachOnChipIO(self.membus, self.bridge)
294    self.realview.attachIO(self.iobus)
295    self.intrctrl = IntrControl()
296    self.terminal = Terminal()
297    self.vncserver = VncServer()
298
299    self.system_port = self.membus.slave
300
301    return self
302
303
304def makeLinuxMipsSystem(mem_mode, mdesc = None):
305    class BaseMalta(Malta):
306        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
307        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
308                            pci_func=0, pci_dev=0, pci_bus=0)
309
310    self = LinuxMipsSystem()
311    if not mdesc:
312        # generic system
313        mdesc = SysConfig()
314    self.readfile = mdesc.script()
315    self.iobus = NoncoherentBus()
316    self.membus = MemBus()
317    self.bridge = Bridge(delay='50ns')
318    self.mem_ranges = [AddrRange('1GB')]
319    self.bridge.master = self.iobus.slave
320    self.bridge.slave = self.membus.master
321    self.disk0 = CowIdeDisk(driveID='master')
322    self.disk2 = CowIdeDisk(driveID='master')
323    self.disk0.childImage(mdesc.disk())
324    self.disk2.childImage(disk('linux-bigswap2.img'))
325    self.malta = BaseMalta()
326    self.malta.attachIO(self.iobus)
327    self.malta.ide.pio = self.iobus.master
328    self.malta.ide.config = self.iobus.master
329    self.malta.ide.dma = self.iobus.slave
330    self.malta.ethernet.pio = self.iobus.master
331    self.malta.ethernet.config = self.iobus.master
332    self.malta.ethernet.dma = self.iobus.slave
333    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
334                                               read_only = True))
335    self.intrctrl = IntrControl()
336    self.mem_mode = mem_mode
337    self.terminal = Terminal()
338    self.kernel = binary('mips/vmlinux')
339    self.console = binary('mips/console')
340    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
341
342    self.system_port = self.membus.slave
343
344    return self
345
346def x86IOAddress(port):
347    IO_address_space_base = 0x8000000000000000
348    return IO_address_space_base + port
349
350def connectX86ClassicSystem(x86_sys, numCPUs):
351    # Constants similar to x86_traits.hh
352    IO_address_space_base = 0x8000000000000000
353    pci_config_address_space_base = 0xc000000000000000
354    interrupts_address_space_base = 0xa000000000000000
355    APIC_range_size = 1 << 12;
356
357    x86_sys.membus = MemBus()
358
359    # North Bridge
360    x86_sys.iobus = NoncoherentBus()
361    x86_sys.bridge = Bridge(delay='50ns')
362    x86_sys.bridge.master = x86_sys.iobus.slave
363    x86_sys.bridge.slave = x86_sys.membus.master
364    # Allow the bridge to pass through the IO APIC (two pages),
365    # everything in the IO address range up to the local APIC, and
366    # then the entire PCI address space and beyond
367    x86_sys.bridge.ranges = \
368        [
369        AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
370                  x86_sys.pc.south_bridge.io_apic.pio_addr +
371                  APIC_range_size - 1),
372        AddrRange(IO_address_space_base,
373                  interrupts_address_space_base - 1),
374        AddrRange(pci_config_address_space_base,
375                  Addr.max)
376        ]
377
378    # Create a bridge from the IO bus to the memory bus to allow access to
379    # the local APIC (two pages)
380    x86_sys.apicbridge = Bridge(delay='50ns')
381    x86_sys.apicbridge.slave = x86_sys.iobus.master
382    x86_sys.apicbridge.master = x86_sys.membus.slave
383    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
384                                           interrupts_address_space_base +
385                                           numCPUs * APIC_range_size
386                                           - 1)]
387
388    # connect the io bus
389    x86_sys.pc.attachIO(x86_sys.iobus)
390
391    x86_sys.system_port = x86_sys.membus.slave
392
393def connectX86RubySystem(x86_sys):
394    # North Bridge
395    x86_sys.piobus = NoncoherentBus()
396
397    # add the ide to the list of dma devices that later need to attach to
398    # dma controllers
399    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
400    x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
401
402
403def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
404                  Ruby = False):
405    if self == None:
406        self = X86System()
407
408    if not mdesc:
409        # generic system
410        mdesc = SysConfig()
411    self.readfile = mdesc.script()
412
413    self.mem_mode = mem_mode
414
415    # Physical memory
416    # On the PC platform, the memory region 0xC0000000-0xFFFFFFFF is reserved
417    # for various devices.  Hence, if the physical memory size is greater than
418    # 3GB, we need to split it into two parts.
419    excess_mem_size = \
420        convert.toMemorySize(mdesc.mem()) - convert.toMemorySize('3GB')
421    if excess_mem_size <= 0:
422        self.mem_ranges = [AddrRange(mdesc.mem())]
423    else:
424        warn("Physical memory size specified is %s which is greater than " \
425             "3GB.  Twice the number of memory controllers would be " \
426             "created."  % (mdesc.mem()))
427
428        self.mem_ranges = [AddrRange('3GB'),
429            AddrRange(Addr('4GB'), size = excess_mem_size)]
430
431    # Platform
432    self.pc = Pc()
433
434    # Create and connect the busses required by each memory system
435    if Ruby:
436        connectX86RubySystem(self)
437    else:
438        connectX86ClassicSystem(self, numCPUs)
439
440    self.intrctrl = IntrControl()
441
442    # Disks
443    disk0 = CowIdeDisk(driveID='master')
444    disk2 = CowIdeDisk(driveID='master')
445    disk0.childImage(mdesc.disk())
446    disk2.childImage(disk('linux-bigswap2.img'))
447    self.pc.south_bridge.ide.disks = [disk0, disk2]
448
449    # Add in a Bios information structure.
450    structures = [X86SMBiosBiosInformation()]
451    self.smbios_table.structures = structures
452
453    # Set up the Intel MP table
454    base_entries = []
455    ext_entries = []
456    for i in xrange(numCPUs):
457        bp = X86IntelMPProcessor(
458                local_apic_id = i,
459                local_apic_version = 0x14,
460                enable = True,
461                bootstrap = (i == 0))
462        base_entries.append(bp)
463    io_apic = X86IntelMPIOAPIC(
464            id = numCPUs,
465            version = 0x11,
466            enable = True,
467            address = 0xfec00000)
468    self.pc.south_bridge.io_apic.apic_id = io_apic.id
469    base_entries.append(io_apic)
470    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
471    base_entries.append(isa_bus)
472    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
473    base_entries.append(pci_bus)
474    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
475            subtractive_decode=True, parent_bus=1)
476    ext_entries.append(connect_busses)
477    pci_dev4_inta = X86IntelMPIOIntAssignment(
478            interrupt_type = 'INT',
479            polarity = 'ConformPolarity',
480            trigger = 'ConformTrigger',
481            source_bus_id = 1,
482            source_bus_irq = 0 + (4 << 2),
483            dest_io_apic_id = io_apic.id,
484            dest_io_apic_intin = 16)
485    base_entries.append(pci_dev4_inta)
486    def assignISAInt(irq, apicPin):
487        assign_8259_to_apic = X86IntelMPIOIntAssignment(
488                interrupt_type = 'ExtInt',
489                polarity = 'ConformPolarity',
490                trigger = 'ConformTrigger',
491                source_bus_id = 0,
492                source_bus_irq = irq,
493                dest_io_apic_id = io_apic.id,
494                dest_io_apic_intin = 0)
495        base_entries.append(assign_8259_to_apic)
496        assign_to_apic = X86IntelMPIOIntAssignment(
497                interrupt_type = 'INT',
498                polarity = 'ConformPolarity',
499                trigger = 'ConformTrigger',
500                source_bus_id = 0,
501                source_bus_irq = irq,
502                dest_io_apic_id = io_apic.id,
503                dest_io_apic_intin = apicPin)
504        base_entries.append(assign_to_apic)
505    assignISAInt(0, 2)
506    assignISAInt(1, 1)
507    for i in range(3, 15):
508        assignISAInt(i, i)
509    self.intel_mp_table.base_entries = base_entries
510    self.intel_mp_table.ext_entries = ext_entries
511
512def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
513                       Ruby = False):
514    self = LinuxX86System()
515
516    # Build up the x86 system and then specialize it for Linux
517    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
518
519    # We assume below that there's at least 1MB of memory. We'll require 2
520    # just to avoid corner cases.
521    phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
522    assert(phys_mem_size >= 0x200000)
523    assert(len(self.mem_ranges) <= 2)
524
525    entries = \
526       [
527        # Mark the first megabyte of memory as reserved
528        X86E820Entry(addr = 0, size = '639kB', range_type = 1),
529        X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
530        # Mark the rest of physical memory as available
531        X86E820Entry(addr = 0x100000,
532                size = '%dB' % (self.mem_ranges[0].size() - 0x100000),
533                range_type = 1),
534        # Reserve the last 16kB of the 32-bit address space for the
535        # m5op interface
536        X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2),
537        ]
538
539    # In case the physical memory is greater than 3GB, we split it into two
540    # parts and add a separate e820 entry for the second part.  This entry
541    # starts at 0x100000000,  which is the first address after the space
542    # reserved for devices.
543    if len(self.mem_ranges) == 2:
544        entries.append(X86E820Entry(addr = 0x100000000,
545            size = '%dB' % (self.mem_ranges[1].size()), range_type = 1))
546
547    self.e820_table.entries = entries
548
549    # Command line
550    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
551                        'root=/dev/hda1'
552    self.kernel = binary('x86_64-vmlinux-2.6.22.9')
553    return self
554
555
556def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
557    self = Root(full_system = full_system)
558    self.testsys = testSystem
559    self.drivesys = driveSystem
560    self.etherlink = EtherLink()
561    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
562    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
563
564    if hasattr(testSystem, 'realview'):
565        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
566        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
567    elif hasattr(testSystem, 'tsunami'):
568        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
569        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
570    else:
571        fatal("Don't know how to connect these system together")
572
573    if dumpfile:
574        self.etherdump = EtherDump(file=dumpfile)
575        self.etherlink.dump = Parent.etherdump
576
577    return self
578