FSConfig.py revision 10003:459491344fcf 
1# Copyright (c) 2010-2012 ARM Limited
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3#
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5# not be construed as granting a license to any other intellectual
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13# Copyright (c) 2010-2011 Advanced Micro Devices, Inc.
14# Copyright (c) 2006-2008 The Regents of The University of Michigan
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34# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39#
40# Authors: Kevin Lim
41
42from m5.objects import *
43from Benchmarks import *
44from m5.util import convert
45
46class CowIdeDisk(IdeDisk):
47    image = CowDiskImage(child=RawDiskImage(read_only=True),
48                         read_only=False)
49
50    def childImage(self, ci):
51        self.image.child.image_file = ci
52
53class MemBus(CoherentBus):
54    badaddr_responder = BadAddr()
55    default = Self.badaddr_responder.pio
56
57
58def makeLinuxAlphaSystem(mem_mode, mdesc = None):
59    IO_address_space_base = 0x80000000000
60    class BaseTsunami(Tsunami):
61        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
62        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
63                            pci_func=0, pci_dev=0, pci_bus=0)
64
65    self = LinuxAlphaSystem()
66    if not mdesc:
67        # generic system
68        mdesc = SysConfig()
69    self.readfile = mdesc.script()
70    self.iobus = NoncoherentBus()
71    self.membus = MemBus()
72    # By default the bridge responds to all addresses above the I/O
73    # base address (including the PCI config space)
74    self.bridge = Bridge(delay='50ns',
75                         ranges = [AddrRange(IO_address_space_base, Addr.max)])
76    self.mem_ranges = [AddrRange(mdesc.mem())]
77    self.bridge.master = self.iobus.slave
78    self.bridge.slave = self.membus.master
79    self.disk0 = CowIdeDisk(driveID='master')
80    self.disk2 = CowIdeDisk(driveID='master')
81    self.disk0.childImage(mdesc.disk())
82    self.disk2.childImage(disk('linux-bigswap2.img'))
83    self.tsunami = BaseTsunami()
84    self.tsunami.attachIO(self.iobus)
85    self.tsunami.ide.pio = self.iobus.master
86    self.tsunami.ide.config = self.iobus.master
87    self.tsunami.ide.dma = self.iobus.slave
88    self.tsunami.ethernet.pio = self.iobus.master
89    self.tsunami.ethernet.config = self.iobus.master
90    self.tsunami.ethernet.dma = self.iobus.slave
91    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
92                                               read_only = True))
93    self.intrctrl = IntrControl()
94    self.mem_mode = mem_mode
95    self.terminal = Terminal()
96    self.kernel = binary('vmlinux')
97    self.pal = binary('ts_osfpal')
98    self.console = binary('console')
99    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
100
101    self.system_port = self.membus.slave
102
103    return self
104
105def makeLinuxAlphaRubySystem(mem_mode, mdesc = None):
106    class BaseTsunami(Tsunami):
107        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
108        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
109                            pci_func=0, pci_dev=0, pci_bus=0)
110    self = LinuxAlphaSystem()
111    self.mem_ranges = [AddrRange(mdesc.mem())]
112    if not mdesc:
113        # generic system
114        mdesc = SysConfig()
115    self.readfile = mdesc.script()
116
117    # Create pio bus to connect all device pio ports to rubymem's pio port
118    self.piobus = NoncoherentBus()
119
120    self.disk0 = CowIdeDisk(driveID='master')
121    self.disk2 = CowIdeDisk(driveID='master')
122    self.disk0.childImage(mdesc.disk())
123    self.disk2.childImage(disk('linux-bigswap2.img'))
124    self.tsunami = BaseTsunami()
125    self.tsunami.attachIO(self.piobus)
126    self.tsunami.ide.pio = self.piobus.master
127    self.tsunami.ide.config = self.piobus.master
128    self.tsunami.ethernet.pio = self.piobus.master
129    self.tsunami.ethernet.config = self.piobus.master
130
131    #
132    # Store the dma devices for later connection to dma ruby ports.
133    # Append an underscore to dma_devices to avoid the SimObjectVector check.
134    #
135    self._dma_ports = [self.tsunami.ide.dma, self.tsunami.ethernet.dma]
136
137    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
138                                               read_only = True))
139    self.intrctrl = IntrControl()
140    self.mem_mode = mem_mode
141    self.terminal = Terminal()
142    self.kernel = binary('vmlinux')
143    self.pal = binary('ts_osfpal')
144    self.console = binary('console')
145    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
146
147    return self
148
149def makeSparcSystem(mem_mode, mdesc = None):
150    # Constants from iob.cc and uart8250.cc
151    iob_man_addr = 0x9800000000
152    uart_pio_size = 8
153
154    class CowMmDisk(MmDisk):
155        image = CowDiskImage(child=RawDiskImage(read_only=True),
156                             read_only=False)
157
158        def childImage(self, ci):
159            self.image.child.image_file = ci
160
161    self = SparcSystem()
162    if not mdesc:
163        # generic system
164        mdesc = SysConfig()
165    self.readfile = mdesc.script()
166    self.iobus = NoncoherentBus()
167    self.membus = MemBus()
168    self.bridge = Bridge(delay='50ns')
169    self.t1000 = T1000()
170    self.t1000.attachOnChipIO(self.membus)
171    self.t1000.attachIO(self.iobus)
172    self.mem_ranges = [AddrRange(Addr('1MB'), size = '64MB'),
173                       AddrRange(Addr('2GB'), size ='256MB')]
174    self.bridge.master = self.iobus.slave
175    self.bridge.slave = self.membus.master
176    self.rom.port = self.membus.master
177    self.nvram.port = self.membus.master
178    self.hypervisor_desc.port = self.membus.master
179    self.partition_desc.port = self.membus.master
180    self.intrctrl = IntrControl()
181    self.disk0 = CowMmDisk()
182    self.disk0.childImage(disk('disk.s10hw2'))
183    self.disk0.pio = self.iobus.master
184
185    # The puart0 and hvuart are placed on the IO bus, so create ranges
186    # for them. The remaining IO range is rather fragmented, so poke
187    # holes for the iob and partition descriptors etc.
188    self.bridge.ranges = \
189        [
190        AddrRange(self.t1000.puart0.pio_addr,
191                  self.t1000.puart0.pio_addr + uart_pio_size - 1),
192        AddrRange(self.disk0.pio_addr,
193                  self.t1000.fake_jbi.pio_addr +
194                  self.t1000.fake_jbi.pio_size - 1),
195        AddrRange(self.t1000.fake_clk.pio_addr,
196                  iob_man_addr - 1),
197        AddrRange(self.t1000.fake_l2_1.pio_addr,
198                  self.t1000.fake_ssi.pio_addr +
199                  self.t1000.fake_ssi.pio_size - 1),
200        AddrRange(self.t1000.hvuart.pio_addr,
201                  self.t1000.hvuart.pio_addr + uart_pio_size - 1)
202        ]
203    self.reset_bin = binary('reset_new.bin')
204    self.hypervisor_bin = binary('q_new.bin')
205    self.openboot_bin = binary('openboot_new.bin')
206    self.nvram_bin = binary('nvram1')
207    self.hypervisor_desc_bin = binary('1up-hv.bin')
208    self.partition_desc_bin = binary('1up-md.bin')
209
210    self.system_port = self.membus.slave
211
212    return self
213
214def makeArmSystem(mem_mode, machine_type, mdesc = None,
215                  dtb_filename = None, bare_metal=False):
216    assert machine_type
217
218    if bare_metal:
219        self = ArmSystem()
220    else:
221        self = LinuxArmSystem()
222
223    if not mdesc:
224        # generic system
225        mdesc = SysConfig()
226
227    self.readfile = mdesc.script()
228    self.iobus = NoncoherentBus()
229    self.membus = MemBus()
230    self.membus.badaddr_responder.warn_access = "warn"
231    self.bridge = Bridge(delay='50ns')
232    self.bridge.master = self.iobus.slave
233    self.bridge.slave = self.membus.master
234
235    self.mem_mode = mem_mode
236
237    if machine_type == "RealView_PBX":
238        self.realview = RealViewPBX()
239    elif machine_type == "RealView_EB":
240        self.realview = RealViewEB()
241    elif machine_type == "VExpress_ELT":
242        self.realview = VExpress_ELT()
243    elif machine_type == "VExpress_EMM":
244        self.realview = VExpress_EMM()
245        self.load_addr_mask = 0xffffffff
246    else:
247        print "Unknown Machine Type"
248        sys.exit(1)
249
250    self.cf0 = CowIdeDisk(driveID='master')
251    self.cf0.childImage(mdesc.disk())
252    # default to an IDE controller rather than a CF one
253    # assuming we've got one
254    try:
255        self.realview.ide.disks = [self.cf0]
256    except:
257        self.realview.cf_ctrl.disks = [self.cf0]
258
259    if bare_metal:
260        # EOT character on UART will end the simulation
261        self.realview.uart.end_on_eot = True
262        self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
263                                     size = mdesc.mem())]
264    else:
265        self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8')
266        if dtb_filename:
267            self.dtb_filename = binary(dtb_filename)
268        self.machine_type = machine_type
269        if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size):
270            print "The currently selected ARM platforms doesn't support"
271            print " the amount of DRAM you've selected. Please try"
272            print " another platform"
273            sys.exit(1)
274
275        boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \
276                     'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem()
277        self.mem_ranges = [AddrRange(self.realview.mem_start_addr,
278                                     size = mdesc.mem())]
279        self.realview.setupBootLoader(self.membus, self, binary)
280        self.gic_cpu_addr = self.realview.gic.cpu_addr
281        self.flags_addr = self.realview.realview_io.pio_addr + 0x30
282
283        if mdesc.disk().lower().count('android'):
284            boot_flags += " init=/init "
285        self.boot_osflags = boot_flags
286    self.realview.attachOnChipIO(self.membus, self.bridge)
287    self.realview.attachIO(self.iobus)
288    self.intrctrl = IntrControl()
289    self.terminal = Terminal()
290    self.vncserver = VncServer()
291
292    self.system_port = self.membus.slave
293
294    return self
295
296
297def makeLinuxMipsSystem(mem_mode, mdesc = None):
298    class BaseMalta(Malta):
299        ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
300        ide = IdeController(disks=[Parent.disk0, Parent.disk2],
301                            pci_func=0, pci_dev=0, pci_bus=0)
302
303    self = LinuxMipsSystem()
304    if not mdesc:
305        # generic system
306        mdesc = SysConfig()
307    self.readfile = mdesc.script()
308    self.iobus = NoncoherentBus()
309    self.membus = MemBus()
310    self.bridge = Bridge(delay='50ns')
311    self.mem_ranges = [AddrRange('1GB')]
312    self.bridge.master = self.iobus.slave
313    self.bridge.slave = self.membus.master
314    self.disk0 = CowIdeDisk(driveID='master')
315    self.disk2 = CowIdeDisk(driveID='master')
316    self.disk0.childImage(mdesc.disk())
317    self.disk2.childImage(disk('linux-bigswap2.img'))
318    self.malta = BaseMalta()
319    self.malta.attachIO(self.iobus)
320    self.malta.ide.pio = self.iobus.master
321    self.malta.ide.config = self.iobus.master
322    self.malta.ide.dma = self.iobus.slave
323    self.malta.ethernet.pio = self.iobus.master
324    self.malta.ethernet.config = self.iobus.master
325    self.malta.ethernet.dma = self.iobus.slave
326    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
327                                               read_only = True))
328    self.intrctrl = IntrControl()
329    self.mem_mode = mem_mode
330    self.terminal = Terminal()
331    self.kernel = binary('mips/vmlinux')
332    self.console = binary('mips/console')
333    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
334
335    self.system_port = self.membus.slave
336
337    return self
338
339def x86IOAddress(port):
340    IO_address_space_base = 0x8000000000000000
341    return IO_address_space_base + port
342
343def connectX86ClassicSystem(x86_sys, numCPUs):
344    # Constants similar to x86_traits.hh
345    IO_address_space_base = 0x8000000000000000
346    pci_config_address_space_base = 0xc000000000000000
347    interrupts_address_space_base = 0xa000000000000000
348    APIC_range_size = 1 << 12;
349
350    x86_sys.membus = MemBus()
351
352    # North Bridge
353    x86_sys.iobus = NoncoherentBus()
354    x86_sys.bridge = Bridge(delay='50ns')
355    x86_sys.bridge.master = x86_sys.iobus.slave
356    x86_sys.bridge.slave = x86_sys.membus.master
357    # Allow the bridge to pass through the IO APIC (two pages),
358    # everything in the IO address range up to the local APIC, and
359    # then the entire PCI address space and beyond
360    x86_sys.bridge.ranges = \
361        [
362        AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr,
363                  x86_sys.pc.south_bridge.io_apic.pio_addr +
364                  APIC_range_size - 1),
365        AddrRange(IO_address_space_base,
366                  interrupts_address_space_base - 1),
367        AddrRange(pci_config_address_space_base,
368                  Addr.max)
369        ]
370
371    # Create a bridge from the IO bus to the memory bus to allow access to
372    # the local APIC (two pages)
373    x86_sys.apicbridge = Bridge(delay='50ns')
374    x86_sys.apicbridge.slave = x86_sys.iobus.master
375    x86_sys.apicbridge.master = x86_sys.membus.slave
376    x86_sys.apicbridge.ranges = [AddrRange(interrupts_address_space_base,
377                                           interrupts_address_space_base +
378                                           numCPUs * APIC_range_size
379                                           - 1)]
380
381    # connect the io bus
382    x86_sys.pc.attachIO(x86_sys.iobus)
383
384    x86_sys.system_port = x86_sys.membus.slave
385
386def connectX86RubySystem(x86_sys):
387    # North Bridge
388    x86_sys.piobus = NoncoherentBus()
389
390    # add the ide to the list of dma devices that later need to attach to
391    # dma controllers
392    x86_sys._dma_ports = [x86_sys.pc.south_bridge.ide.dma]
393    x86_sys.pc.attachIO(x86_sys.piobus, x86_sys._dma_ports)
394
395
396def makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None,
397                  Ruby = False):
398    if self == None:
399        self = X86System()
400
401    if not mdesc:
402        # generic system
403        mdesc = SysConfig()
404    self.readfile = mdesc.script()
405
406    self.mem_mode = mem_mode
407
408    # Physical memory
409    self.mem_ranges = [AddrRange(mdesc.mem())]
410
411    # Platform
412    self.pc = Pc()
413
414    # Create and connect the busses required by each memory system
415    if Ruby:
416        connectX86RubySystem(self)
417    else:
418        connectX86ClassicSystem(self, numCPUs)
419
420    self.intrctrl = IntrControl()
421
422    # Disks
423    disk0 = CowIdeDisk(driveID='master')
424    disk2 = CowIdeDisk(driveID='master')
425    disk0.childImage(mdesc.disk())
426    disk2.childImage(disk('linux-bigswap2.img'))
427    self.pc.south_bridge.ide.disks = [disk0, disk2]
428
429    # Add in a Bios information structure.
430    structures = [X86SMBiosBiosInformation()]
431    self.smbios_table.structures = structures
432
433    # Set up the Intel MP table
434    base_entries = []
435    ext_entries = []
436    for i in xrange(numCPUs):
437        bp = X86IntelMPProcessor(
438                local_apic_id = i,
439                local_apic_version = 0x14,
440                enable = True,
441                bootstrap = (i == 0))
442        base_entries.append(bp)
443    io_apic = X86IntelMPIOAPIC(
444            id = numCPUs,
445            version = 0x11,
446            enable = True,
447            address = 0xfec00000)
448    self.pc.south_bridge.io_apic.apic_id = io_apic.id
449    base_entries.append(io_apic)
450    isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA')
451    base_entries.append(isa_bus)
452    pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI')
453    base_entries.append(pci_bus)
454    connect_busses = X86IntelMPBusHierarchy(bus_id=0,
455            subtractive_decode=True, parent_bus=1)
456    ext_entries.append(connect_busses)
457    pci_dev4_inta = X86IntelMPIOIntAssignment(
458            interrupt_type = 'INT',
459            polarity = 'ConformPolarity',
460            trigger = 'ConformTrigger',
461            source_bus_id = 1,
462            source_bus_irq = 0 + (4 << 2),
463            dest_io_apic_id = io_apic.id,
464            dest_io_apic_intin = 16)
465    base_entries.append(pci_dev4_inta)
466    def assignISAInt(irq, apicPin):
467        assign_8259_to_apic = X86IntelMPIOIntAssignment(
468                interrupt_type = 'ExtInt',
469                polarity = 'ConformPolarity',
470                trigger = 'ConformTrigger',
471                source_bus_id = 0,
472                source_bus_irq = irq,
473                dest_io_apic_id = io_apic.id,
474                dest_io_apic_intin = 0)
475        base_entries.append(assign_8259_to_apic)
476        assign_to_apic = X86IntelMPIOIntAssignment(
477                interrupt_type = 'INT',
478                polarity = 'ConformPolarity',
479                trigger = 'ConformTrigger',
480                source_bus_id = 0,
481                source_bus_irq = irq,
482                dest_io_apic_id = io_apic.id,
483                dest_io_apic_intin = apicPin)
484        base_entries.append(assign_to_apic)
485    assignISAInt(0, 2)
486    assignISAInt(1, 1)
487    for i in range(3, 15):
488        assignISAInt(i, i)
489    self.intel_mp_table.base_entries = base_entries
490    self.intel_mp_table.ext_entries = ext_entries
491
492def makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None,
493                       Ruby = False):
494    self = LinuxX86System()
495
496    # Build up the x86 system and then specialize it for Linux
497    makeX86System(mem_mode, numCPUs, mdesc, self, Ruby)
498
499    # We assume below that there's at least 1MB of memory. We'll require 2
500    # just to avoid corner cases.
501    phys_mem_size = sum(map(lambda r: r.size(), self.mem_ranges))
502    assert(phys_mem_size >= 0x200000)
503
504    self.e820_table.entries = \
505       [
506        # Mark the first megabyte of memory as reserved
507        X86E820Entry(addr = 0, size = '639kB', range_type = 1),
508        X86E820Entry(addr = 0x9fc00, size = '385kB', range_type = 2),
509        # Mark the rest as available
510        X86E820Entry(addr = 0x100000,
511                size = '%dB' % (phys_mem_size - 0x100000),
512                range_type = 1),
513        # Reserve the last 16kB of the 32-bit address space for the
514        # m5op interface
515        X86E820Entry(addr=0xFFFF0000, size='64kB', range_type=2),
516        ]
517
518    # Command line
519    self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \
520                        'root=/dev/hda1'
521    self.kernel = binary('x86_64-vmlinux-2.6.22.9')
522    return self
523
524
525def makeDualRoot(full_system, testSystem, driveSystem, dumpfile):
526    self = Root(full_system = full_system)
527    self.testsys = testSystem
528    self.drivesys = driveSystem
529    self.etherlink = EtherLink()
530    self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
531    self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
532
533    if hasattr(testSystem, 'realview'):
534        self.etherlink.int0 = Parent.testsys.realview.ethernet.interface
535        self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface
536    elif hasattr(testSystem, 'tsunami'):
537        self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface
538        self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface
539    else:
540        fatal("Don't know how to connect these system together")
541
542    if dumpfile:
543        self.etherdump = EtherDump(file=dumpfile)
544        self.etherlink.dump = Parent.etherdump
545
546    return self
547