FSConfig.py revision 8714
18706Sandreas.hansson@arm.com# Copyright (c) 2010-2012 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 137905SBrad.Beckmann@amd.com# Copyright (c) 2010-2011 Advanced Micro Devices, Inc. 145323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 152934Sktlim@umich.edu# All rights reserved. 162934Sktlim@umich.edu# 172934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 182934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 192934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 202934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 212934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 222934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 232934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 242934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 252934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 262934Sktlim@umich.edu# this software without specific prior written permission. 272934Sktlim@umich.edu# 282934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392934Sktlim@umich.edu# 402934Sktlim@umich.edu# Authors: Kevin Lim 412934Sktlim@umich.edu 422934Sktlim@umich.edufrom m5.objects import * 432995Ssaidi@eecs.umich.edufrom Benchmarks import * 448528SAli.Saidi@ARM.comfrom m5.util import convert 452934Sktlim@umich.edu 462934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 472934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 482934Sktlim@umich.edu read_only=False) 492934Sktlim@umich.edu 502934Sktlim@umich.edu def childImage(self, ci): 512934Sktlim@umich.edu self.image.child.image_file = ci 522934Sktlim@umich.edu 536122SSteve.Reinhardt@amd.comclass MemBus(Bus): 546122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 556122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 566122SSteve.Reinhardt@amd.com 576122SSteve.Reinhardt@amd.com 584520Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 598713Sandreas.hansson@arm.com IO_address_space_base = 0x80000000000 604520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 614982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 624520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 634520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 642934Sktlim@umich.edu 652934Sktlim@umich.edu self = LinuxAlphaSystem() 663005Sstever@eecs.umich.edu if not mdesc: 673005Sstever@eecs.umich.edu # generic system 683304Sstever@eecs.umich.edu mdesc = SysConfig() 692995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 702934Sktlim@umich.edu self.iobus = Bus(bus_id=0) 716122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 728713Sandreas.hansson@arm.com # By default the bridge responds to all addresses above the I/O 738713Sandreas.hansson@arm.com # base address (including the PCI config space) 748713Sandreas.hansson@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns', 758713Sandreas.hansson@arm.com ranges = [AddrRange(IO_address_space_base, Addr.max)]) 765266Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 778713Sandreas.hansson@arm.com self.bridge.master = self.iobus.port 788713Sandreas.hansson@arm.com self.bridge.slave = self.membus.port 792934Sktlim@umich.edu self.physmem.port = self.membus.port 802934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 812934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 822995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 832934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 842934Sktlim@umich.edu self.tsunami = BaseTsunami() 852934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 862934Sktlim@umich.edu self.tsunami.ide.pio = self.iobus.port 878714Sandreas.hansson@arm.com self.tsunami.ide.config = self.iobus.port 888714Sandreas.hansson@arm.com self.tsunami.ide.dma = self.iobus.port 892934Sktlim@umich.edu self.tsunami.ethernet.pio = self.iobus.port 908714Sandreas.hansson@arm.com self.tsunami.ethernet.config = self.iobus.port 918714Sandreas.hansson@arm.com self.tsunami.ethernet.dma = self.iobus.port 922995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 932934Sktlim@umich.edu read_only = True)) 942934Sktlim@umich.edu self.intrctrl = IntrControl() 952953Sktlim@umich.edu self.mem_mode = mem_mode 965478Snate@binkert.org self.terminal = Terminal() 972934Sktlim@umich.edu self.kernel = binary('vmlinux') 983449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 992934Sktlim@umich.edu self.console = binary('console') 1002934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1012934Sktlim@umich.edu 1028706Sandreas.hansson@arm.com self.system_port = self.membus.port 1038706Sandreas.hansson@arm.com 1042934Sktlim@umich.edu return self 1052934Sktlim@umich.edu 1067014SBrad.Beckmann@amd.comdef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 1076765SBrad.Beckmann@amd.com class BaseTsunami(Tsunami): 1086765SBrad.Beckmann@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 1096765SBrad.Beckmann@amd.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 1106765SBrad.Beckmann@amd.com pci_func=0, pci_dev=0, pci_bus=0) 1116765SBrad.Beckmann@amd.com 1127014SBrad.Beckmann@amd.com physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1137014SBrad.Beckmann@amd.com self = LinuxAlphaSystem(physmem = physmem) 1146765SBrad.Beckmann@amd.com if not mdesc: 1156765SBrad.Beckmann@amd.com # generic system 1166765SBrad.Beckmann@amd.com mdesc = SysConfig() 1176765SBrad.Beckmann@amd.com self.readfile = mdesc.script() 1186765SBrad.Beckmann@amd.com 1196765SBrad.Beckmann@amd.com # Create pio bus to connect all device pio ports to rubymem's pio port 1206765SBrad.Beckmann@amd.com self.piobus = Bus(bus_id=0) 1216893SBrad.Beckmann@amd.com 1226893SBrad.Beckmann@amd.com # 1236893SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 1246893SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 1256893SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 1266893SBrad.Beckmann@amd.com # 1277014SBrad.Beckmann@amd.com self.piobus.port = physmem.port 1286893SBrad.Beckmann@amd.com 1296765SBrad.Beckmann@amd.com self.disk0 = CowIdeDisk(driveID='master') 1306765SBrad.Beckmann@amd.com self.disk2 = CowIdeDisk(driveID='master') 1316765SBrad.Beckmann@amd.com self.disk0.childImage(mdesc.disk()) 1326765SBrad.Beckmann@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 1336765SBrad.Beckmann@amd.com self.tsunami = BaseTsunami() 1346765SBrad.Beckmann@amd.com self.tsunami.attachIO(self.piobus) 1356765SBrad.Beckmann@amd.com self.tsunami.ide.pio = self.piobus.port 1368714Sandreas.hansson@arm.com self.tsunami.ide.config = self.piobus.port 1378714Sandreas.hansson@arm.com self.tsunami.ide.dma = self.piobus.port 1386765SBrad.Beckmann@amd.com self.tsunami.ethernet.pio = self.piobus.port 1398714Sandreas.hansson@arm.com self.tsunami.ethernet.config = self.piobus.port 1408714Sandreas.hansson@arm.com self.tsunami.ethernet.dma = self.piobus.port 1416765SBrad.Beckmann@amd.com 1426893SBrad.Beckmann@amd.com # 1437633SBrad.Beckmann@amd.com # Store the dma devices for later connection to dma ruby ports. 1447633SBrad.Beckmann@amd.com # Append an underscore to dma_devices to avoid the SimObjectVector check. 1456893SBrad.Beckmann@amd.com # 1467633SBrad.Beckmann@amd.com self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet] 1476765SBrad.Beckmann@amd.com 1486765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1496765SBrad.Beckmann@amd.com read_only = True)) 1506765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1516765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1526765SBrad.Beckmann@amd.com self.terminal = Terminal() 1536765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1546765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1556765SBrad.Beckmann@amd.com self.console = binary('console') 1566765SBrad.Beckmann@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1576765SBrad.Beckmann@amd.com 1586765SBrad.Beckmann@amd.com return self 1596765SBrad.Beckmann@amd.com 1603584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 1618713Sandreas.hansson@arm.com # Constants from iob.cc and uart8250.cc 1628713Sandreas.hansson@arm.com iob_man_addr = 0x9800000000 1638713Sandreas.hansson@arm.com uart_pio_size = 8 1648713Sandreas.hansson@arm.com 1654486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1664486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1674486Sbinkertn@umich.edu read_only=False) 1684486Sbinkertn@umich.edu 1694486Sbinkertn@umich.edu def childImage(self, ci): 1704486Sbinkertn@umich.edu self.image.child.image_file = ci 1714486Sbinkertn@umich.edu 1723584Ssaidi@eecs.umich.edu self = SparcSystem() 1733584Ssaidi@eecs.umich.edu if not mdesc: 1743584Ssaidi@eecs.umich.edu # generic system 1753584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1763584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 1773743Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 1786122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 1794972Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1803743Sgblack@eecs.umich.edu self.t1000 = T1000() 1814104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1823743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1833823Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 1843814Ssaidi@eecs.umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1858713Sandreas.hansson@arm.com self.bridge.master = self.iobus.port 1868713Sandreas.hansson@arm.com self.bridge.slave = self.membus.port 1873584Ssaidi@eecs.umich.edu self.physmem.port = self.membus.port 1883814Ssaidi@eecs.umich.edu self.physmem2.port = self.membus.port 1893584Ssaidi@eecs.umich.edu self.rom.port = self.membus.port 1903745Sgblack@eecs.umich.edu self.nvram.port = self.membus.port 1913745Sgblack@eecs.umich.edu self.hypervisor_desc.port = self.membus.port 1923745Sgblack@eecs.umich.edu self.partition_desc.port = self.membus.port 1933584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1943898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1953898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1963898Ssaidi@eecs.umich.edu self.disk0.pio = self.iobus.port 1978713Sandreas.hansson@arm.com 1988713Sandreas.hansson@arm.com # The puart0 and hvuart are placed on the IO bus, so create ranges 1998713Sandreas.hansson@arm.com # for them. The remaining IO range is rather fragmented, so poke 2008713Sandreas.hansson@arm.com # holes for the iob and partition descriptors etc. 2018713Sandreas.hansson@arm.com self.bridge.ranges = \ 2028713Sandreas.hansson@arm.com [ 2038713Sandreas.hansson@arm.com AddrRange(self.t1000.puart0.pio_addr, 2048713Sandreas.hansson@arm.com self.t1000.puart0.pio_addr + uart_pio_size - 1), 2058713Sandreas.hansson@arm.com AddrRange(self.disk0.pio_addr, 2068713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_addr + 2078713Sandreas.hansson@arm.com self.t1000.fake_jbi.pio_size - 1), 2088713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_clk.pio_addr, 2098713Sandreas.hansson@arm.com iob_man_addr - 1), 2108713Sandreas.hansson@arm.com AddrRange(self.t1000.fake_l2_1.pio_addr, 2118713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_addr + 2128713Sandreas.hansson@arm.com self.t1000.fake_ssi.pio_size - 1), 2138713Sandreas.hansson@arm.com AddrRange(self.t1000.hvuart.pio_addr, 2148713Sandreas.hansson@arm.com self.t1000.hvuart.pio_addr + uart_pio_size - 1) 2158713Sandreas.hansson@arm.com ] 2164103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 2174103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 2184103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 2193745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 2203745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 2213745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 2223584Ssaidi@eecs.umich.edu 2238706Sandreas.hansson@arm.com self.system_port = self.membus.port 2248706Sandreas.hansson@arm.com 2253584Ssaidi@eecs.umich.edu return self 2263584Ssaidi@eecs.umich.edu 2278061SAli.Saidi@ARM.comdef makeArmSystem(mem_mode, machine_type, mdesc = None, bare_metal=False): 2288061SAli.Saidi@ARM.com assert machine_type 2298061SAli.Saidi@ARM.com 2307586SAli.Saidi@arm.com if bare_metal: 2317586SAli.Saidi@arm.com self = ArmSystem() 2327586SAli.Saidi@arm.com else: 2337586SAli.Saidi@arm.com self = LinuxArmSystem() 2347586SAli.Saidi@arm.com 2357586SAli.Saidi@arm.com if not mdesc: 2367586SAli.Saidi@arm.com # generic system 2377586SAli.Saidi@arm.com mdesc = SysConfig() 2387586SAli.Saidi@arm.com 2397586SAli.Saidi@arm.com self.readfile = mdesc.script() 2407586SAli.Saidi@arm.com self.iobus = Bus(bus_id=0) 2417586SAli.Saidi@arm.com self.membus = MemBus(bus_id=1) 2427586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2437586SAli.Saidi@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2448713Sandreas.hansson@arm.com self.bridge.master = self.iobus.port 2458713Sandreas.hansson@arm.com self.bridge.slave = self.membus.port 2467586SAli.Saidi@arm.com 2477586SAli.Saidi@arm.com self.mem_mode = mem_mode 2487586SAli.Saidi@arm.com 2497586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2507586SAli.Saidi@arm.com self.realview = RealViewPBX() 2517586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2527586SAli.Saidi@arm.com self.realview = RealViewEB() 2538525SAli.Saidi@ARM.com elif machine_type == "VExpress_ELT": 2548525SAli.Saidi@ARM.com self.realview = VExpress_ELT() 2557586SAli.Saidi@arm.com else: 2567586SAli.Saidi@arm.com print "Unknown Machine Type" 2577586SAli.Saidi@arm.com sys.exit(1) 2587586SAli.Saidi@arm.com 2598528SAli.Saidi@ARM.com self.cf0 = CowIdeDisk(driveID='master') 2608528SAli.Saidi@ARM.com self.cf0.childImage(mdesc.disk()) 2618528SAli.Saidi@ARM.com # default to an IDE controller rather than a CF one 2628528SAli.Saidi@ARM.com # assuming we've got one 2638528SAli.Saidi@ARM.com try: 2648528SAli.Saidi@ARM.com self.realview.ide.disks = [self.cf0] 2658528SAli.Saidi@ARM.com except: 2668528SAli.Saidi@ARM.com self.realview.cf_ctrl.disks = [self.cf0] 2678528SAli.Saidi@ARM.com 2688061SAli.Saidi@ARM.com if bare_metal: 2698061SAli.Saidi@ARM.com # EOT character on UART will end the simulation 2708061SAli.Saidi@ARM.com self.realview.uart.end_on_eot = True 2718528SAli.Saidi@ARM.com self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())), 2728212SAli.Saidi@ARM.com zero = True) 2738061SAli.Saidi@ARM.com else: 2748528SAli.Saidi@ARM.com self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') 2757586SAli.Saidi@arm.com self.machine_type = machine_type 2768528SAli.Saidi@ARM.com if convert.toMemorySize(mdesc.mem()) > convert.toMemorySize('256MB'): 2778528SAli.Saidi@ARM.com print "The currently implemented ARM platforms only easily support 256MB of DRAM" 2788528SAli.Saidi@ARM.com print "It might be possible to get some more by using 256MB@0x30000000, but this" 2798528SAli.Saidi@ARM.com print "is untested and may require some heroics" 2808528SAli.Saidi@ARM.com 2818212SAli.Saidi@ARM.com boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ 2828528SAli.Saidi@ARM.com 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() 2838528SAli.Saidi@ARM.com 2848528SAli.Saidi@ARM.com self.physmem = PhysicalMemory(range = AddrRange(Addr(mdesc.mem())), 2858528SAli.Saidi@ARM.com zero = True) 2868528SAli.Saidi@ARM.com self.nvmem = PhysicalMemory(range = AddrRange(Addr('2GB'), 2878528SAli.Saidi@ARM.com size = '64MB'), zero = True) 2888528SAli.Saidi@ARM.com self.nvmem.port = self.membus.port 2898528SAli.Saidi@ARM.com self.boot_loader = binary('boot.arm') 2908528SAli.Saidi@ARM.com self.boot_loader_mem = self.nvmem 2918528SAli.Saidi@ARM.com self.gic_cpu_addr = self.realview.gic.cpu_addr 2928528SAli.Saidi@ARM.com self.flags_addr = self.realview.realview_io.pio_addr + 0x30 2938287SAli.Saidi@ARM.com 2948643Satgutier@umich.edu if mdesc.disk().lower().count('android'): 2958595SAli.Saidi@ARM.com boot_flags += " init=/init " 2968212SAli.Saidi@ARM.com self.boot_osflags = boot_flags 2977586SAli.Saidi@arm.com 2988145SAli.Saidi@ARM.com self.physmem.port = self.membus.port 2998713Sandreas.hansson@arm.com self.realview.attachOnChipIO(self.membus, self.bridge) 3007586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 3017586SAli.Saidi@arm.com self.intrctrl = IntrControl() 3027586SAli.Saidi@arm.com self.terminal = Terminal() 3037949SAli.Saidi@ARM.com self.vncserver = VncServer() 3047586SAli.Saidi@arm.com 3058706Sandreas.hansson@arm.com self.system_port = self.membus.port 3068706Sandreas.hansson@arm.com 3077586SAli.Saidi@arm.com return self 3087586SAli.Saidi@arm.com 3097586SAli.Saidi@arm.com 3105222Sksewell@umich.edudef makeLinuxMipsSystem(mem_mode, mdesc = None): 3115222Sksewell@umich.edu class BaseMalta(Malta): 3125222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 3135222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 3145222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 3155222Sksewell@umich.edu 3165222Sksewell@umich.edu self = LinuxMipsSystem() 3175222Sksewell@umich.edu if not mdesc: 3185222Sksewell@umich.edu # generic system 3195222Sksewell@umich.edu mdesc = SysConfig() 3205222Sksewell@umich.edu self.readfile = mdesc.script() 3215222Sksewell@umich.edu self.iobus = Bus(bus_id=0) 3226122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 3235222Sksewell@umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 3245222Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange('1GB')) 3258713Sandreas.hansson@arm.com self.bridge.master = self.iobus.port 3268713Sandreas.hansson@arm.com self.bridge.slave = self.membus.port 3275222Sksewell@umich.edu self.physmem.port = self.membus.port 3285222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 3295222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 3305222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 3315222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 3325222Sksewell@umich.edu self.malta = BaseMalta() 3335222Sksewell@umich.edu self.malta.attachIO(self.iobus) 3345222Sksewell@umich.edu self.malta.ide.pio = self.iobus.port 3358714Sandreas.hansson@arm.com self.malta.ide.config = self.iobus.port 3368714Sandreas.hansson@arm.com self.malta.ide.dma = self.iobus.port 3375222Sksewell@umich.edu self.malta.ethernet.pio = self.iobus.port 3388714Sandreas.hansson@arm.com self.malta.ethernet.config = self.iobus.port 3398714Sandreas.hansson@arm.com self.malta.ethernet.dma = self.iobus.port 3405222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 3415222Sksewell@umich.edu read_only = True)) 3425222Sksewell@umich.edu self.intrctrl = IntrControl() 3435222Sksewell@umich.edu self.mem_mode = mem_mode 3445478Snate@binkert.org self.terminal = Terminal() 3455222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 3465222Sksewell@umich.edu self.console = binary('mips/console') 3475222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 3485222Sksewell@umich.edu 3498706Sandreas.hansson@arm.com self.system_port = self.membus.port 3508706Sandreas.hansson@arm.com 3515222Sksewell@umich.edu return self 3525222Sksewell@umich.edu 3535323Sgblack@eecs.umich.edudef x86IOAddress(port): 3545357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 3558323Ssteve.reinhardt@amd.com return IO_address_space_base + port 3565323Sgblack@eecs.umich.edu 3577905SBrad.Beckmann@amd.comdef connectX86ClassicSystem(x86_sys): 3588713Sandreas.hansson@arm.com # Constants similar to x86_traits.hh 3598713Sandreas.hansson@arm.com IO_address_space_base = 0x8000000000000000 3608713Sandreas.hansson@arm.com pci_config_address_space_base = 0xc000000000000000 3618713Sandreas.hansson@arm.com interrupts_address_space_base = 0xa000000000000000 3628713Sandreas.hansson@arm.com APIC_range_size = 1 << 12; 3638713Sandreas.hansson@arm.com 3647905SBrad.Beckmann@amd.com x86_sys.membus = MemBus(bus_id=1) 3657905SBrad.Beckmann@amd.com x86_sys.physmem.port = x86_sys.membus.port 3667905SBrad.Beckmann@amd.com 3677905SBrad.Beckmann@amd.com # North Bridge 3687905SBrad.Beckmann@amd.com x86_sys.iobus = Bus(bus_id=0) 3697905SBrad.Beckmann@amd.com x86_sys.bridge = Bridge(delay='50ns', nack_delay='4ns') 3708713Sandreas.hansson@arm.com x86_sys.bridge.master = x86_sys.iobus.port 3718713Sandreas.hansson@arm.com x86_sys.bridge.slave = x86_sys.membus.port 3728713Sandreas.hansson@arm.com # Allow the bridge to pass through the IO APIC (two pages), 3738713Sandreas.hansson@arm.com # everything in the IO address range up to the local APIC, and 3748713Sandreas.hansson@arm.com # then the entire PCI address space and beyond 3758713Sandreas.hansson@arm.com x86_sys.bridge.ranges = \ 3768713Sandreas.hansson@arm.com [ 3778713Sandreas.hansson@arm.com AddrRange(x86_sys.pc.south_bridge.io_apic.pio_addr, 3788713Sandreas.hansson@arm.com x86_sys.pc.south_bridge.io_apic.pio_addr + 3798713Sandreas.hansson@arm.com APIC_range_size - 1), 3808713Sandreas.hansson@arm.com AddrRange(IO_address_space_base, 3818713Sandreas.hansson@arm.com interrupts_address_space_base - 1), 3828713Sandreas.hansson@arm.com AddrRange(pci_config_address_space_base, 3838713Sandreas.hansson@arm.com Addr.max) 3848713Sandreas.hansson@arm.com ] 3858713Sandreas.hansson@arm.com 3868713Sandreas.hansson@arm.com # Create a bridge from the IO bus to the memory bus to allow access to 3878713Sandreas.hansson@arm.com # the local APIC (two pages) 3888713Sandreas.hansson@arm.com x86_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns') 3898713Sandreas.hansson@arm.com x86_sys.iobridge.slave = x86_sys.iobus.port 3908713Sandreas.hansson@arm.com x86_sys.iobridge.master = x86_sys.membus.port 3918713Sandreas.hansson@arm.com x86_sys.iobridge.ranges = [AddrRange(interrupts_address_space_base, 3928713Sandreas.hansson@arm.com interrupts_address_space_base + 3938713Sandreas.hansson@arm.com APIC_range_size - 1)] 3947905SBrad.Beckmann@amd.com 3957905SBrad.Beckmann@amd.com # connect the io bus 3967905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.iobus) 3977905SBrad.Beckmann@amd.com 3988706Sandreas.hansson@arm.com x86_sys.system_port = x86_sys.membus.port 3998706Sandreas.hansson@arm.com 4007905SBrad.Beckmann@amd.comdef connectX86RubySystem(x86_sys): 4017905SBrad.Beckmann@amd.com # North Bridge 4027905SBrad.Beckmann@amd.com x86_sys.piobus = Bus(bus_id=0) 4037905SBrad.Beckmann@amd.com 4047905SBrad.Beckmann@amd.com # 4057905SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 4067905SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 4077905SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 4087905SBrad.Beckmann@amd.com # 4097905SBrad.Beckmann@amd.com x86_sys.piobus.port = x86_sys.physmem.port 4107905SBrad.Beckmann@amd.com 4117905SBrad.Beckmann@amd.com x86_sys.pc.attachIO(x86_sys.piobus) 4127905SBrad.Beckmann@amd.com 4137905SBrad.Beckmann@amd.com 4147905SBrad.Beckmann@amd.comdef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None, Ruby = False): 4155613Sgblack@eecs.umich.edu if self == None: 4165613Sgblack@eecs.umich.edu self = X86System() 4175613Sgblack@eecs.umich.edu 4185133Sgblack@eecs.umich.edu if not mdesc: 4195133Sgblack@eecs.umich.edu # generic system 4205133Sgblack@eecs.umich.edu mdesc = SysConfig() 4215133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 4225133Sgblack@eecs.umich.edu 4236802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 4246802Sgblack@eecs.umich.edu 4255133Sgblack@eecs.umich.edu # Physical memory 4265450Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 4275613Sgblack@eecs.umich.edu 4285613Sgblack@eecs.umich.edu # Platform 4295638Sgblack@eecs.umich.edu self.pc = Pc() 4307905SBrad.Beckmann@amd.com 4317905SBrad.Beckmann@amd.com # Create and connect the busses required by each memory system 4327905SBrad.Beckmann@amd.com if Ruby: 4337905SBrad.Beckmann@amd.com connectX86RubySystem(self) 4347937SBrad.Beckmann@amd.com # add the ide to the list of dma devices that later need to attach to 4357937SBrad.Beckmann@amd.com # dma controllers 4367937SBrad.Beckmann@amd.com self._dma_devices = [self.pc.south_bridge.ide] 4377905SBrad.Beckmann@amd.com else: 4387905SBrad.Beckmann@amd.com connectX86ClassicSystem(self) 4395613Sgblack@eecs.umich.edu 4405613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 4415613Sgblack@eecs.umich.edu 4425841Sgblack@eecs.umich.edu # Disks 4435841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 4445841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 4455841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 4465841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 4475841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 4485841Sgblack@eecs.umich.edu 4495615Sgblack@eecs.umich.edu # Add in a Bios information structure. 4505615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 4515615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 4525615Sgblack@eecs.umich.edu 4535641Sgblack@eecs.umich.edu # Set up the Intel MP table 4548323Ssteve.reinhardt@amd.com base_entries = [] 4558323Ssteve.reinhardt@amd.com ext_entries = [] 4566135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 4576135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 4586135Sgblack@eecs.umich.edu local_apic_id = i, 4596135Sgblack@eecs.umich.edu local_apic_version = 0x14, 4606135Sgblack@eecs.umich.edu enable = True, 4616135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 4628323Ssteve.reinhardt@amd.com base_entries.append(bp) 4635644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 4646135Sgblack@eecs.umich.edu id = numCPUs, 4655644Sgblack@eecs.umich.edu version = 0x11, 4665644Sgblack@eecs.umich.edu enable = True, 4675644Sgblack@eecs.umich.edu address = 0xfec00000) 4686135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 4698323Ssteve.reinhardt@amd.com base_entries.append(io_apic) 4705644Sgblack@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 4718323Ssteve.reinhardt@amd.com base_entries.append(isa_bus) 4725843Sgblack@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 4738323Ssteve.reinhardt@amd.com base_entries.append(pci_bus) 4745843Sgblack@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 4755843Sgblack@eecs.umich.edu subtractive_decode=True, parent_bus=1) 4768323Ssteve.reinhardt@amd.com ext_entries.append(connect_busses) 4775843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 4785843Sgblack@eecs.umich.edu interrupt_type = 'INT', 4795843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4805843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4815843Sgblack@eecs.umich.edu source_bus_id = 1, 4825843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 4836044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4845843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 4858323Ssteve.reinhardt@amd.com base_entries.append(pci_dev4_inta) 4866135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 4876135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 4886135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 4896135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4906135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 4916135Sgblack@eecs.umich.edu source_bus_id = 0, 4926135Sgblack@eecs.umich.edu source_bus_irq = irq, 4936135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 4946135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 4958323Ssteve.reinhardt@amd.com base_entries.append(assign_8259_to_apic) 4966135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 4976135Sgblack@eecs.umich.edu interrupt_type = 'INT', 4986135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 4996135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 5006135Sgblack@eecs.umich.edu source_bus_id = 0, 5016135Sgblack@eecs.umich.edu source_bus_irq = irq, 5026135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 5036135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 5048323Ssteve.reinhardt@amd.com base_entries.append(assign_to_apic) 5056135Sgblack@eecs.umich.edu assignISAInt(0, 2) 5066135Sgblack@eecs.umich.edu assignISAInt(1, 1) 5076135Sgblack@eecs.umich.edu for i in range(3, 15): 5086135Sgblack@eecs.umich.edu assignISAInt(i, i) 5098323Ssteve.reinhardt@amd.com self.intel_mp_table.base_entries = base_entries 5108323Ssteve.reinhardt@amd.com self.intel_mp_table.ext_entries = ext_entries 5115641Sgblack@eecs.umich.edu 5127925Sgblack@eecs.umich.edudef setWorkCountOptions(system, options): 5137925Sgblack@eecs.umich.edu if options.work_item_id != None: 5147925Sgblack@eecs.umich.edu system.work_item_id = options.work_item_id 5157925Sgblack@eecs.umich.edu if options.work_begin_cpu_id_exit != None: 5167925Sgblack@eecs.umich.edu system.work_begin_cpu_id_exit = options.work_begin_cpu_id_exit 5177925Sgblack@eecs.umich.edu if options.work_end_exit_count != None: 5187925Sgblack@eecs.umich.edu system.work_end_exit_count = options.work_end_exit_count 5197925Sgblack@eecs.umich.edu if options.work_end_checkpoint_count != None: 5207925Sgblack@eecs.umich.edu system.work_end_ckpt_count = options.work_end_checkpoint_count 5217925Sgblack@eecs.umich.edu if options.work_begin_exit_count != None: 5227925Sgblack@eecs.umich.edu system.work_begin_exit_count = options.work_begin_exit_count 5237925Sgblack@eecs.umich.edu if options.work_begin_checkpoint_count != None: 5247925Sgblack@eecs.umich.edu system.work_begin_ckpt_count = options.work_begin_checkpoint_count 5257925Sgblack@eecs.umich.edu if options.work_cpus_checkpoint_count != None: 5267925Sgblack@eecs.umich.edu system.work_cpus_ckpt_count = options.work_cpus_checkpoint_count 5277925Sgblack@eecs.umich.edu 5287925Sgblack@eecs.umich.edu 5297925Sgblack@eecs.umich.edudef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None, Ruby = False): 5305613Sgblack@eecs.umich.edu self = LinuxX86System() 5315613Sgblack@eecs.umich.edu 5327905SBrad.Beckmann@amd.com # Build up the x86 system and then specialize it for Linux 5337905SBrad.Beckmann@amd.com makeX86System(mem_mode, numCPUs, mdesc, self, Ruby) 5345613Sgblack@eecs.umich.edu 5355450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 5365450Sgblack@eecs.umich.edu # just to avoid corner cases. 5377069Snate@binkert.org assert(self.physmem.range.second.getValue() >= 0x200000) 5385450Sgblack@eecs.umich.edu 5398323Ssteve.reinhardt@amd.com self.e820_table.entries = \ 5408323Ssteve.reinhardt@amd.com [ 5418323Ssteve.reinhardt@amd.com # Mark the first megabyte of memory as reserved 5428323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0, size = '1MB', range_type = 2), 5438323Ssteve.reinhardt@amd.com # Mark the rest as available 5448323Ssteve.reinhardt@amd.com X86E820Entry(addr = 0x100000, 5456072Sgblack@eecs.umich.edu size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 5468323Ssteve.reinhardt@amd.com range_type = 1) 5478323Ssteve.reinhardt@amd.com ] 5485450Sgblack@eecs.umich.edu 5495330Sgblack@eecs.umich.edu # Command line 5505847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 5515845Sgblack@eecs.umich.edu 'root=/dev/hda1' 5525133Sgblack@eecs.umich.edu return self 5535133Sgblack@eecs.umich.edu 5543584Ssaidi@eecs.umich.edu 5553025Ssaidi@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile): 5562934Sktlim@umich.edu self = Root() 5572995Ssaidi@eecs.umich.edu self.testsys = testSystem 5582995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 5594981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 5604981Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5614981Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5624981Ssaidi@eecs.umich.edu 5638661SAli.Saidi@ARM.com if hasattr(testSystem, 'realview'): 5648661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.realview.ethernet.interface 5658661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.realview.ethernet.interface 5668661SAli.Saidi@ARM.com elif hasattr(testSystem, 'tsunami'): 5678661SAli.Saidi@ARM.com self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 5688661SAli.Saidi@ARM.com self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 5698661SAli.Saidi@ARM.com else: 5708661SAli.Saidi@ARM.com fatal("Don't know how to connect these system together") 5718661SAli.Saidi@ARM.com 5723025Ssaidi@eecs.umich.edu if dumpfile: 5733025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 5743025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 5752934Sktlim@umich.edu 5762934Sktlim@umich.edu return self 5775253Sksewell@umich.edu 5785263Sksewell@umich.edudef setMipsOptions(TestCPUClass): 5795253Sksewell@umich.edu #CP0 Configuration 5805253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 5815253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 5825253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 5835253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 5845253Sksewell@umich.edu 5855253Sksewell@umich.edu #CP0 Interrupt Control 5865253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 5875253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 5885253Sksewell@umich.edu 5895253Sksewell@umich.edu # Config Register 5905253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 5915253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 5925253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 5935253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 5945253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 5955253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 5965253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 5975253Sksewell@umich.edu 5985253Sksewell@umich.edu #Config 1 Register 5995253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 6005253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 6015253Sksewell@umich.edu # ***VERY IMPORTANT*** 6025253Sksewell@umich.edu # Remember to modify CP0_Config1 according to cache specs 6035253Sksewell@umich.edu # Examine file ../common/Cache.py 6045253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 6055253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 6065253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 6075253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 6085253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 6095253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 6105253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 6115253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 6125253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 6135253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 6145253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 6155253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 6165253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 6175253Sksewell@umich.edu 6185253Sksewell@umich.edu #Config 2 Register 6195253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 6205253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 6215253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 6225253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 6235253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 6245253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 6255253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 6265253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 6275253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 6285253Sksewell@umich.edu 6295253Sksewell@umich.edu 6305253Sksewell@umich.edu #Config 3 Register 6315253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 6325253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 6335253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 6345253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 6355253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 6365253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 6375253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 6385253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 6395253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 6405253Sksewell@umich.edu 6415253Sksewell@umich.edu #SRS Ctl - HSS 6425253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 6435253Sksewell@umich.edu 6445253Sksewell@umich.edu 6455253Sksewell@umich.edu #TestCPUClass.CoreParams.tlb = TLB() 6465253Sksewell@umich.edu #TestCPUClass.CoreParams.UnifiedTLB = 1 647