FSConfig.py revision 7750
17586SAli.Saidi@arm.com# Copyright (c) 2010 ARM Limited 27586SAli.Saidi@arm.com# All rights reserved. 37586SAli.Saidi@arm.com# 47586SAli.Saidi@arm.com# The license below extends only to copyright in the software and shall 57586SAli.Saidi@arm.com# not be construed as granting a license to any other intellectual 67586SAli.Saidi@arm.com# property including but not limited to intellectual property relating 77586SAli.Saidi@arm.com# to a hardware implementation of the functionality of the software 87586SAli.Saidi@arm.com# licensed hereunder. You may use the software subject to the license 97586SAli.Saidi@arm.com# terms below provided that you ensure that this notice is replicated 107586SAli.Saidi@arm.com# unmodified and in its entirety in all distributions of the software, 117586SAli.Saidi@arm.com# modified or unmodified, in source code or in binary form. 127586SAli.Saidi@arm.com# 135323Sgblack@eecs.umich.edu# Copyright (c) 2006-2008 The Regents of The University of Michigan 142934Sktlim@umich.edu# All rights reserved. 152934Sktlim@umich.edu# 162934Sktlim@umich.edu# Redistribution and use in source and binary forms, with or without 172934Sktlim@umich.edu# modification, are permitted provided that the following conditions are 182934Sktlim@umich.edu# met: redistributions of source code must retain the above copyright 192934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer; 202934Sktlim@umich.edu# redistributions in binary form must reproduce the above copyright 212934Sktlim@umich.edu# notice, this list of conditions and the following disclaimer in the 222934Sktlim@umich.edu# documentation and/or other materials provided with the distribution; 232934Sktlim@umich.edu# neither the name of the copyright holders nor the names of its 242934Sktlim@umich.edu# contributors may be used to endorse or promote products derived from 252934Sktlim@umich.edu# this software without specific prior written permission. 262934Sktlim@umich.edu# 272934Sktlim@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282934Sktlim@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292934Sktlim@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302934Sktlim@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312934Sktlim@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322934Sktlim@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332934Sktlim@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342934Sktlim@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352934Sktlim@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362934Sktlim@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372934Sktlim@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382934Sktlim@umich.edu# 392934Sktlim@umich.edu# Authors: Kevin Lim 402934Sktlim@umich.edu 412934Sktlim@umich.edufrom m5.objects import * 422995Ssaidi@eecs.umich.edufrom Benchmarks import * 432934Sktlim@umich.edu 442934Sktlim@umich.educlass CowIdeDisk(IdeDisk): 452934Sktlim@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 462934Sktlim@umich.edu read_only=False) 472934Sktlim@umich.edu 482934Sktlim@umich.edu def childImage(self, ci): 492934Sktlim@umich.edu self.image.child.image_file = ci 502934Sktlim@umich.edu 516122SSteve.Reinhardt@amd.comclass MemBus(Bus): 526122SSteve.Reinhardt@amd.com badaddr_responder = BadAddr() 536122SSteve.Reinhardt@amd.com default = Self.badaddr_responder.pio 546122SSteve.Reinhardt@amd.com 556122SSteve.Reinhardt@amd.com 564520Ssaidi@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None): 574520Ssaidi@eecs.umich.edu class BaseTsunami(Tsunami): 584982Ssaidi@eecs.umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 594520Ssaidi@eecs.umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 604520Ssaidi@eecs.umich.edu pci_func=0, pci_dev=0, pci_bus=0) 612934Sktlim@umich.edu 622934Sktlim@umich.edu self = LinuxAlphaSystem() 633005Sstever@eecs.umich.edu if not mdesc: 643005Sstever@eecs.umich.edu # generic system 653304Sstever@eecs.umich.edu mdesc = SysConfig() 662995Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 672934Sktlim@umich.edu self.iobus = Bus(bus_id=0) 686122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 694965Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 705266Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 712934Sktlim@umich.edu self.bridge.side_a = self.iobus.port 722934Sktlim@umich.edu self.bridge.side_b = self.membus.port 732934Sktlim@umich.edu self.physmem.port = self.membus.port 742934Sktlim@umich.edu self.disk0 = CowIdeDisk(driveID='master') 752934Sktlim@umich.edu self.disk2 = CowIdeDisk(driveID='master') 762995Ssaidi@eecs.umich.edu self.disk0.childImage(mdesc.disk()) 772934Sktlim@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 782934Sktlim@umich.edu self.tsunami = BaseTsunami() 792934Sktlim@umich.edu self.tsunami.attachIO(self.iobus) 802934Sktlim@umich.edu self.tsunami.ide.pio = self.iobus.port 812934Sktlim@umich.edu self.tsunami.ethernet.pio = self.iobus.port 822995Ssaidi@eecs.umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 832934Sktlim@umich.edu read_only = True)) 842934Sktlim@umich.edu self.intrctrl = IntrControl() 852953Sktlim@umich.edu self.mem_mode = mem_mode 865478Snate@binkert.org self.terminal = Terminal() 872934Sktlim@umich.edu self.kernel = binary('vmlinux') 883449Shsul@eecs.umich.edu self.pal = binary('ts_osfpal') 892934Sktlim@umich.edu self.console = binary('console') 902934Sktlim@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 912934Sktlim@umich.edu 922934Sktlim@umich.edu return self 932934Sktlim@umich.edu 947014SBrad.Beckmann@amd.comdef makeLinuxAlphaRubySystem(mem_mode, mdesc = None): 956765SBrad.Beckmann@amd.com class BaseTsunami(Tsunami): 966765SBrad.Beckmann@amd.com ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 976765SBrad.Beckmann@amd.com ide = IdeController(disks=[Parent.disk0, Parent.disk2], 986765SBrad.Beckmann@amd.com pci_func=0, pci_dev=0, pci_bus=0) 996765SBrad.Beckmann@amd.com 1007014SBrad.Beckmann@amd.com physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 1017014SBrad.Beckmann@amd.com self = LinuxAlphaSystem(physmem = physmem) 1026765SBrad.Beckmann@amd.com if not mdesc: 1036765SBrad.Beckmann@amd.com # generic system 1046765SBrad.Beckmann@amd.com mdesc = SysConfig() 1056765SBrad.Beckmann@amd.com self.readfile = mdesc.script() 1066765SBrad.Beckmann@amd.com 1076765SBrad.Beckmann@amd.com # Create pio bus to connect all device pio ports to rubymem's pio port 1086765SBrad.Beckmann@amd.com self.piobus = Bus(bus_id=0) 1096893SBrad.Beckmann@amd.com 1106893SBrad.Beckmann@amd.com # 1116893SBrad.Beckmann@amd.com # Pio functional accesses from devices need direct access to memory 1126893SBrad.Beckmann@amd.com # RubyPort currently does support functional accesses. Therefore provide 1136893SBrad.Beckmann@amd.com # the piobus a direct connection to physical memory 1146893SBrad.Beckmann@amd.com # 1157014SBrad.Beckmann@amd.com self.piobus.port = physmem.port 1166893SBrad.Beckmann@amd.com 1176765SBrad.Beckmann@amd.com self.disk0 = CowIdeDisk(driveID='master') 1186765SBrad.Beckmann@amd.com self.disk2 = CowIdeDisk(driveID='master') 1196765SBrad.Beckmann@amd.com self.disk0.childImage(mdesc.disk()) 1206765SBrad.Beckmann@amd.com self.disk2.childImage(disk('linux-bigswap2.img')) 1216765SBrad.Beckmann@amd.com self.tsunami = BaseTsunami() 1226765SBrad.Beckmann@amd.com self.tsunami.attachIO(self.piobus) 1236765SBrad.Beckmann@amd.com self.tsunami.ide.pio = self.piobus.port 1246765SBrad.Beckmann@amd.com self.tsunami.ethernet.pio = self.piobus.port 1256765SBrad.Beckmann@amd.com 1266893SBrad.Beckmann@amd.com # 1277633SBrad.Beckmann@amd.com # Store the dma devices for later connection to dma ruby ports. 1287633SBrad.Beckmann@amd.com # Append an underscore to dma_devices to avoid the SimObjectVector check. 1296893SBrad.Beckmann@amd.com # 1307633SBrad.Beckmann@amd.com self._dma_devices = [self.tsunami.ide, self.tsunami.ethernet] 1316765SBrad.Beckmann@amd.com 1326765SBrad.Beckmann@amd.com self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 1336765SBrad.Beckmann@amd.com read_only = True)) 1346765SBrad.Beckmann@amd.com self.intrctrl = IntrControl() 1356765SBrad.Beckmann@amd.com self.mem_mode = mem_mode 1366765SBrad.Beckmann@amd.com self.terminal = Terminal() 1376765SBrad.Beckmann@amd.com self.kernel = binary('vmlinux') 1386765SBrad.Beckmann@amd.com self.pal = binary('ts_osfpal') 1396765SBrad.Beckmann@amd.com self.console = binary('console') 1406765SBrad.Beckmann@amd.com self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 1416765SBrad.Beckmann@amd.com 1426765SBrad.Beckmann@amd.com return self 1436765SBrad.Beckmann@amd.com 1443584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None): 1454486Sbinkertn@umich.edu class CowMmDisk(MmDisk): 1464486Sbinkertn@umich.edu image = CowDiskImage(child=RawDiskImage(read_only=True), 1474486Sbinkertn@umich.edu read_only=False) 1484486Sbinkertn@umich.edu 1494486Sbinkertn@umich.edu def childImage(self, ci): 1504486Sbinkertn@umich.edu self.image.child.image_file = ci 1514486Sbinkertn@umich.edu 1523584Ssaidi@eecs.umich.edu self = SparcSystem() 1533584Ssaidi@eecs.umich.edu if not mdesc: 1543584Ssaidi@eecs.umich.edu # generic system 1553584Ssaidi@eecs.umich.edu mdesc = SysConfig() 1563584Ssaidi@eecs.umich.edu self.readfile = mdesc.script() 1573743Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 1586122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 1594972Ssaidi@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 1603743Sgblack@eecs.umich.edu self.t1000 = T1000() 1614104Ssaidi@eecs.umich.edu self.t1000.attachOnChipIO(self.membus) 1623743Sgblack@eecs.umich.edu self.t1000.attachIO(self.iobus) 1633823Ssaidi@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(Addr('1MB'), size = '64MB'), zero = True) 1643814Ssaidi@eecs.umich.edu self.physmem2 = PhysicalMemory(range = AddrRange(Addr('2GB'), size ='256MB'), zero = True) 1653743Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 1663743Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 1673584Ssaidi@eecs.umich.edu self.physmem.port = self.membus.port 1683814Ssaidi@eecs.umich.edu self.physmem2.port = self.membus.port 1693584Ssaidi@eecs.umich.edu self.rom.port = self.membus.port 1703745Sgblack@eecs.umich.edu self.nvram.port = self.membus.port 1713745Sgblack@eecs.umich.edu self.hypervisor_desc.port = self.membus.port 1723745Sgblack@eecs.umich.edu self.partition_desc.port = self.membus.port 1733584Ssaidi@eecs.umich.edu self.intrctrl = IntrControl() 1743898Ssaidi@eecs.umich.edu self.disk0 = CowMmDisk() 1753898Ssaidi@eecs.umich.edu self.disk0.childImage(disk('disk.s10hw2')) 1763898Ssaidi@eecs.umich.edu self.disk0.pio = self.iobus.port 1774103Ssaidi@eecs.umich.edu self.reset_bin = binary('reset_new.bin') 1784103Ssaidi@eecs.umich.edu self.hypervisor_bin = binary('q_new.bin') 1794103Ssaidi@eecs.umich.edu self.openboot_bin = binary('openboot_new.bin') 1803745Sgblack@eecs.umich.edu self.nvram_bin = binary('nvram1') 1813745Sgblack@eecs.umich.edu self.hypervisor_desc_bin = binary('1up-hv.bin') 1823745Sgblack@eecs.umich.edu self.partition_desc_bin = binary('1up-md.bin') 1833584Ssaidi@eecs.umich.edu 1843584Ssaidi@eecs.umich.edu return self 1853584Ssaidi@eecs.umich.edu 1867586SAli.Saidi@arm.comdef makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False, 1877586SAli.Saidi@arm.com machine_type = None): 1887586SAli.Saidi@arm.com if bare_metal: 1897586SAli.Saidi@arm.com self = ArmSystem() 1907586SAli.Saidi@arm.com else: 1917586SAli.Saidi@arm.com self = LinuxArmSystem() 1927586SAli.Saidi@arm.com 1937586SAli.Saidi@arm.com if not mdesc: 1947586SAli.Saidi@arm.com # generic system 1957586SAli.Saidi@arm.com mdesc = SysConfig() 1967586SAli.Saidi@arm.com 1977586SAli.Saidi@arm.com self.readfile = mdesc.script() 1987586SAli.Saidi@arm.com self.iobus = Bus(bus_id=0) 1997586SAli.Saidi@arm.com self.membus = MemBus(bus_id=1) 2007586SAli.Saidi@arm.com self.membus.badaddr_responder.warn_access = "warn" 2017586SAli.Saidi@arm.com self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2027586SAli.Saidi@arm.com self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True) 2037730SAli.Saidi@ARM.com self.diskmem = PhysicalMemory(range = AddrRange(Addr('128MB'), size = '128MB'), 2047730SAli.Saidi@ARM.com file = disk('ael-arm.ext2')) 2057586SAli.Saidi@arm.com self.bridge.side_a = self.iobus.port 2067586SAli.Saidi@arm.com self.bridge.side_b = self.membus.port 2077586SAli.Saidi@arm.com self.physmem.port = self.membus.port 2087730SAli.Saidi@ARM.com self.diskmem.port = self.membus.port 2097586SAli.Saidi@arm.com 2107586SAli.Saidi@arm.com self.mem_mode = mem_mode 2117586SAli.Saidi@arm.com 2127750SAli.Saidi@ARM.com #self.cf0 = CowIdeDisk(driveID='master') 2137750SAli.Saidi@ARM.com #self.cf0.childImage(mdesc.disk()) 2147750SAli.Saidi@ARM.com #self.cf_ctrl = IdeController(disks=[self.cf0], 2157750SAli.Saidi@ARM.com # pci_func = 0, pci_dev = 0, pci_bus = 0, 2167750SAli.Saidi@ARM.com # io_shift = 1, ctrl_offset = 2, Command = 0x1, 2177750SAli.Saidi@ARM.com # BAR0 = 0x18000000, BAR0Size = '16B', 2187750SAli.Saidi@ARM.com # BAR1 = 0x18000100, BAR1Size = '1B', 2197750SAli.Saidi@ARM.com # BAR0LegacyIO = True, BAR1LegacyIO = True,) 2207750SAli.Saidi@ARM.com #self.cf_ctrl.pio = self.iobus.port 2217750SAli.Saidi@ARM.com 2227586SAli.Saidi@arm.com if machine_type == "RealView_PBX": 2237586SAli.Saidi@arm.com self.realview = RealViewPBX() 2247586SAli.Saidi@arm.com elif machine_type == "RealView_EB": 2257586SAli.Saidi@arm.com self.realview = RealViewEB() 2267586SAli.Saidi@arm.com else: 2277586SAli.Saidi@arm.com print "Unknown Machine Type" 2287586SAli.Saidi@arm.com sys.exit(1) 2297586SAli.Saidi@arm.com 2307586SAli.Saidi@arm.com if not bare_metal and machine_type: 2317586SAli.Saidi@arm.com self.machine_type = machine_type 2327586SAli.Saidi@arm.com elif bare_metal: 2337586SAli.Saidi@arm.com self.realview.uart.end_on_eot = True 2347586SAli.Saidi@arm.com 2357586SAli.Saidi@arm.com self.realview.attachOnChipIO(self.membus) 2367586SAli.Saidi@arm.com self.realview.attachIO(self.iobus) 2377586SAli.Saidi@arm.com 2387586SAli.Saidi@arm.com self.intrctrl = IntrControl() 2397586SAli.Saidi@arm.com self.terminal = Terminal() 2407730SAli.Saidi@ARM.com self.kernel = binary('vmlinux.arm') 2417730SAli.Saidi@ARM.com self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480' + \ 2427730SAli.Saidi@ARM.com ' norandmaps slram=slram0,0x8000000,+0x8000000' + \ 2437730SAli.Saidi@ARM.com ' mtdparts=slram0:- rw loglevel=8 root=/dev/mtdblock0' 2447586SAli.Saidi@arm.com 2457586SAli.Saidi@arm.com return self 2467586SAli.Saidi@arm.com 2477586SAli.Saidi@arm.com 2485222Sksewell@umich.edudef makeLinuxMipsSystem(mem_mode, mdesc = None): 2495222Sksewell@umich.edu class BaseMalta(Malta): 2505222Sksewell@umich.edu ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0) 2515222Sksewell@umich.edu ide = IdeController(disks=[Parent.disk0, Parent.disk2], 2525222Sksewell@umich.edu pci_func=0, pci_dev=0, pci_bus=0) 2535222Sksewell@umich.edu 2545222Sksewell@umich.edu self = LinuxMipsSystem() 2555222Sksewell@umich.edu if not mdesc: 2565222Sksewell@umich.edu # generic system 2575222Sksewell@umich.edu mdesc = SysConfig() 2585222Sksewell@umich.edu self.readfile = mdesc.script() 2595222Sksewell@umich.edu self.iobus = Bus(bus_id=0) 2606122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 2615222Sksewell@umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 2625222Sksewell@umich.edu self.physmem = PhysicalMemory(range = AddrRange('1GB')) 2635222Sksewell@umich.edu self.bridge.side_a = self.iobus.port 2645222Sksewell@umich.edu self.bridge.side_b = self.membus.port 2655222Sksewell@umich.edu self.physmem.port = self.membus.port 2665222Sksewell@umich.edu self.disk0 = CowIdeDisk(driveID='master') 2675222Sksewell@umich.edu self.disk2 = CowIdeDisk(driveID='master') 2685222Sksewell@umich.edu self.disk0.childImage(mdesc.disk()) 2695222Sksewell@umich.edu self.disk2.childImage(disk('linux-bigswap2.img')) 2705222Sksewell@umich.edu self.malta = BaseMalta() 2715222Sksewell@umich.edu self.malta.attachIO(self.iobus) 2725222Sksewell@umich.edu self.malta.ide.pio = self.iobus.port 2735222Sksewell@umich.edu self.malta.ethernet.pio = self.iobus.port 2745222Sksewell@umich.edu self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(), 2755222Sksewell@umich.edu read_only = True)) 2765222Sksewell@umich.edu self.intrctrl = IntrControl() 2775222Sksewell@umich.edu self.mem_mode = mem_mode 2785478Snate@binkert.org self.terminal = Terminal() 2795222Sksewell@umich.edu self.kernel = binary('mips/vmlinux') 2805222Sksewell@umich.edu self.console = binary('mips/console') 2815222Sksewell@umich.edu self.boot_osflags = 'root=/dev/hda1 console=ttyS0' 2825222Sksewell@umich.edu 2835222Sksewell@umich.edu return self 2845222Sksewell@umich.edu 2855323Sgblack@eecs.umich.edudef x86IOAddress(port): 2865357Sgblack@eecs.umich.edu IO_address_space_base = 0x8000000000000000 2875323Sgblack@eecs.umich.edu return IO_address_space_base + port; 2885323Sgblack@eecs.umich.edu 2896135Sgblack@eecs.umich.edudef makeX86System(mem_mode, numCPUs = 1, mdesc = None, self = None): 2905613Sgblack@eecs.umich.edu if self == None: 2915613Sgblack@eecs.umich.edu self = X86System() 2925613Sgblack@eecs.umich.edu 2935133Sgblack@eecs.umich.edu if not mdesc: 2945133Sgblack@eecs.umich.edu # generic system 2955133Sgblack@eecs.umich.edu mdesc = SysConfig() 2965841Sgblack@eecs.umich.edu mdesc.diskname = 'x86root.img' 2975133Sgblack@eecs.umich.edu self.readfile = mdesc.script() 2985133Sgblack@eecs.umich.edu 2996802Sgblack@eecs.umich.edu self.mem_mode = mem_mode 3006802Sgblack@eecs.umich.edu 3015133Sgblack@eecs.umich.edu # Physical memory 3026122SSteve.Reinhardt@amd.com self.membus = MemBus(bus_id=1) 3035450Sgblack@eecs.umich.edu self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) 3045133Sgblack@eecs.umich.edu self.physmem.port = self.membus.port 3055133Sgblack@eecs.umich.edu 3065613Sgblack@eecs.umich.edu # North Bridge 3075613Sgblack@eecs.umich.edu self.iobus = Bus(bus_id=0) 3085613Sgblack@eecs.umich.edu self.bridge = Bridge(delay='50ns', nack_delay='4ns') 3095613Sgblack@eecs.umich.edu self.bridge.side_a = self.iobus.port 3105613Sgblack@eecs.umich.edu self.bridge.side_b = self.membus.port 3115613Sgblack@eecs.umich.edu 3125613Sgblack@eecs.umich.edu # Platform 3135638Sgblack@eecs.umich.edu self.pc = Pc() 3145613Sgblack@eecs.umich.edu self.pc.attachIO(self.iobus) 3155613Sgblack@eecs.umich.edu 3165613Sgblack@eecs.umich.edu self.intrctrl = IntrControl() 3175613Sgblack@eecs.umich.edu 3185841Sgblack@eecs.umich.edu # Disks 3195841Sgblack@eecs.umich.edu disk0 = CowIdeDisk(driveID='master') 3205841Sgblack@eecs.umich.edu disk2 = CowIdeDisk(driveID='master') 3215841Sgblack@eecs.umich.edu disk0.childImage(mdesc.disk()) 3225841Sgblack@eecs.umich.edu disk2.childImage(disk('linux-bigswap2.img')) 3235841Sgblack@eecs.umich.edu self.pc.south_bridge.ide.disks = [disk0, disk2] 3245841Sgblack@eecs.umich.edu 3255615Sgblack@eecs.umich.edu # Add in a Bios information structure. 3265615Sgblack@eecs.umich.edu structures = [X86SMBiosBiosInformation()] 3275615Sgblack@eecs.umich.edu self.smbios_table.structures = structures 3285615Sgblack@eecs.umich.edu 3295641Sgblack@eecs.umich.edu # Set up the Intel MP table 3306135Sgblack@eecs.umich.edu for i in xrange(numCPUs): 3316135Sgblack@eecs.umich.edu bp = X86IntelMPProcessor( 3326135Sgblack@eecs.umich.edu local_apic_id = i, 3336135Sgblack@eecs.umich.edu local_apic_version = 0x14, 3346135Sgblack@eecs.umich.edu enable = True, 3356135Sgblack@eecs.umich.edu bootstrap = (i == 0)) 3366135Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(bp) 3375644Sgblack@eecs.umich.edu io_apic = X86IntelMPIOAPIC( 3386135Sgblack@eecs.umich.edu id = numCPUs, 3395644Sgblack@eecs.umich.edu version = 0x11, 3405644Sgblack@eecs.umich.edu enable = True, 3415644Sgblack@eecs.umich.edu address = 0xfec00000) 3426135Sgblack@eecs.umich.edu self.pc.south_bridge.io_apic.apic_id = io_apic.id 3435644Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(io_apic) 3445644Sgblack@eecs.umich.edu isa_bus = X86IntelMPBus(bus_id = 0, bus_type='ISA') 3455644Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(isa_bus) 3465843Sgblack@eecs.umich.edu pci_bus = X86IntelMPBus(bus_id = 1, bus_type='PCI') 3475843Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(pci_bus) 3485843Sgblack@eecs.umich.edu connect_busses = X86IntelMPBusHierarchy(bus_id=0, 3495843Sgblack@eecs.umich.edu subtractive_decode=True, parent_bus=1) 3505843Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(connect_busses) 3515843Sgblack@eecs.umich.edu pci_dev4_inta = X86IntelMPIOIntAssignment( 3525843Sgblack@eecs.umich.edu interrupt_type = 'INT', 3535843Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 3545843Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 3555843Sgblack@eecs.umich.edu source_bus_id = 1, 3565843Sgblack@eecs.umich.edu source_bus_irq = 0 + (4 << 2), 3576044Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 3585843Sgblack@eecs.umich.edu dest_io_apic_intin = 16) 3596074Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(pci_dev4_inta); 3606135Sgblack@eecs.umich.edu def assignISAInt(irq, apicPin): 3616135Sgblack@eecs.umich.edu assign_8259_to_apic = X86IntelMPIOIntAssignment( 3626135Sgblack@eecs.umich.edu interrupt_type = 'ExtInt', 3636135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 3646135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 3656135Sgblack@eecs.umich.edu source_bus_id = 0, 3666135Sgblack@eecs.umich.edu source_bus_irq = irq, 3676135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 3686135Sgblack@eecs.umich.edu dest_io_apic_intin = 0) 3696135Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_8259_to_apic) 3706135Sgblack@eecs.umich.edu assign_to_apic = X86IntelMPIOIntAssignment( 3716135Sgblack@eecs.umich.edu interrupt_type = 'INT', 3726135Sgblack@eecs.umich.edu polarity = 'ConformPolarity', 3736135Sgblack@eecs.umich.edu trigger = 'ConformTrigger', 3746135Sgblack@eecs.umich.edu source_bus_id = 0, 3756135Sgblack@eecs.umich.edu source_bus_irq = irq, 3766135Sgblack@eecs.umich.edu dest_io_apic_id = io_apic.id, 3776135Sgblack@eecs.umich.edu dest_io_apic_intin = apicPin) 3786135Sgblack@eecs.umich.edu self.intel_mp_table.add_entry(assign_to_apic) 3796135Sgblack@eecs.umich.edu assignISAInt(0, 2) 3806135Sgblack@eecs.umich.edu assignISAInt(1, 1) 3816135Sgblack@eecs.umich.edu for i in range(3, 15): 3826135Sgblack@eecs.umich.edu assignISAInt(i, i) 3835641Sgblack@eecs.umich.edu 3845613Sgblack@eecs.umich.edu 3856135Sgblack@eecs.umich.edudef makeLinuxX86System(mem_mode, numCPUs = 1, mdesc = None): 3865613Sgblack@eecs.umich.edu self = LinuxX86System() 3875613Sgblack@eecs.umich.edu 3885613Sgblack@eecs.umich.edu # Build up a generic x86 system and then specialize it for Linux 3896135Sgblack@eecs.umich.edu makeX86System(mem_mode, numCPUs, mdesc, self) 3905613Sgblack@eecs.umich.edu 3915450Sgblack@eecs.umich.edu # We assume below that there's at least 1MB of memory. We'll require 2 3925450Sgblack@eecs.umich.edu # just to avoid corner cases. 3937069Snate@binkert.org assert(self.physmem.range.second.getValue() >= 0x200000) 3945450Sgblack@eecs.umich.edu 3955450Sgblack@eecs.umich.edu # Mark the first megabyte of memory as reserved 3965450Sgblack@eecs.umich.edu self.e820_table.entries.append(X86E820Entry( 3975450Sgblack@eecs.umich.edu addr = 0, 3985450Sgblack@eecs.umich.edu size = '1MB', 3995450Sgblack@eecs.umich.edu range_type = 2)) 4005450Sgblack@eecs.umich.edu 4015450Sgblack@eecs.umich.edu # Mark the rest as available 4025450Sgblack@eecs.umich.edu self.e820_table.entries.append(X86E820Entry( 4035450Sgblack@eecs.umich.edu addr = 0x100000, 4046072Sgblack@eecs.umich.edu size = '%dB' % (self.physmem.range.second - 0x100000 + 1), 4055450Sgblack@eecs.umich.edu range_type = 1)) 4065450Sgblack@eecs.umich.edu 4075330Sgblack@eecs.umich.edu # Command line 4085847Sgblack@eecs.umich.edu self.boot_osflags = 'earlyprintk=ttyS0 console=ttyS0 lpj=7999923 ' + \ 4095845Sgblack@eecs.umich.edu 'root=/dev/hda1' 4105133Sgblack@eecs.umich.edu return self 4115133Sgblack@eecs.umich.edu 4123584Ssaidi@eecs.umich.edu 4133025Ssaidi@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile): 4142934Sktlim@umich.edu self = Root() 4152995Ssaidi@eecs.umich.edu self.testsys = testSystem 4162995Ssaidi@eecs.umich.edu self.drivesys = driveSystem 4174981Ssaidi@eecs.umich.edu self.etherlink = EtherLink() 4184981Ssaidi@eecs.umich.edu self.etherlink.int0 = Parent.testsys.tsunami.ethernet.interface 4194981Ssaidi@eecs.umich.edu self.etherlink.int1 = Parent.drivesys.tsunami.ethernet.interface 4204981Ssaidi@eecs.umich.edu 4213025Ssaidi@eecs.umich.edu if dumpfile: 4223025Ssaidi@eecs.umich.edu self.etherdump = EtherDump(file=dumpfile) 4233025Ssaidi@eecs.umich.edu self.etherlink.dump = Parent.etherdump 4242934Sktlim@umich.edu 4252934Sktlim@umich.edu return self 4265253Sksewell@umich.edu 4275263Sksewell@umich.edudef setMipsOptions(TestCPUClass): 4285253Sksewell@umich.edu #CP0 Configuration 4295253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyOptions = 0 4305253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_CompanyID = 1 4315253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_ProcessorID = 147 4325253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_PRId_Revision = 0 4335253Sksewell@umich.edu 4345253Sksewell@umich.edu #CP0 Interrupt Control 4355253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPTI = 7 4365253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_IntCtl_IPPCI = 7 4375253Sksewell@umich.edu 4385253Sksewell@umich.edu # Config Register 4395253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K23 = 0 # Since TLB 4405253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_KU = 0 # Since TLB 4415253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_BE = 0 # Little Endian 4425253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AR = 1 # Architecture Revision 2 4435253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_AT = 0 # MIPS32 4445253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config_MT = 1 # TLB MMU 4455253Sksewell@umich.edu #TestCPUClass.CoreParams.CP0_Config_K0 = 2 # Uncached 4465253Sksewell@umich.edu 4475253Sksewell@umich.edu #Config 1 Register 4485253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_M = 1 # Config2 Implemented 4495253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MMU = 63 # TLB Size 4505253Sksewell@umich.edu # ***VERY IMPORTANT*** 4515253Sksewell@umich.edu # Remember to modify CP0_Config1 according to cache specs 4525253Sksewell@umich.edu # Examine file ../common/Cache.py 4535253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IS = 1 # I-Cache Sets Per Way, 16KB cache, i.e., 1 (128) 4545253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IL = 5 # I-Cache Line Size, default in Cache.py is 64, i.e 5 4555253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_IA = 1 # I-Cache Associativity, default in Cache.py is 2, i.e, a value of 1 4565253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DS = 2 # D-Cache Sets Per Way (see below), 32KB cache, i.e., 2 4575253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DL = 5 # D-Cache Line Size, default is 64, i.e., 5 4585253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_DA = 1 # D-Cache Associativity, default is 2, i.e. 1 4595253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_C2 = 0 # Coprocessor 2 not implemented(?) 4605253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_MD = 0 # MDMX ASE not implemented in Mips32 4615253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_PC = 1 # Performance Counters Implemented 4625253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_WR = 0 # Watch Registers Implemented 4635253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_CA = 0 # Mips16e NOT implemented 4645253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_EP = 0 # EJTag Not Implemented 4655253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config1_FP = 0 # FPU Implemented 4665253Sksewell@umich.edu 4675253Sksewell@umich.edu #Config 2 Register 4685253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_M = 1 # Config3 Implemented 4695253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TU = 0 # Tertiary Cache Control 4705253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TS = 0 # Tertiary Cache Sets Per Way 4715253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TL = 0 # Tertiary Cache Line Size 4725253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_TA = 0 # Tertiary Cache Associativity 4735253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SU = 0 # Secondary Cache Control 4745253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SS = 0 # Secondary Cache Sets Per Way 4755253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SL = 0 # Secondary Cache Line Size 4765253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config2_SA = 0 # Secondary Cache Associativity 4775253Sksewell@umich.edu 4785253Sksewell@umich.edu 4795253Sksewell@umich.edu #Config 3 Register 4805253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_M = 0 # Config4 Not Implemented 4815253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_DSPP = 1 # DSP ASE Present 4825253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_LPA = 0 # Large Physical Addresses Not supported in Mips32 4835253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VEIC = 0 # EIC Supported 4845253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_VInt = 0 # Vectored Interrupts Implemented 4855253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SP = 0 # Small Pages Supported (PageGrain reg. exists) 4865253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_MT = 0 # MT Not present 4875253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_SM = 0 # SmartMIPS ASE Not implemented 4885253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_Config3_TL = 0 # TraceLogic Not implemented 4895253Sksewell@umich.edu 4905253Sksewell@umich.edu #SRS Ctl - HSS 4915253Sksewell@umich.edu TestCPUClass.CoreParams.CP0_SrsCtl_HSS = 3 # Four shadow register sets implemented 4925253Sksewell@umich.edu 4935253Sksewell@umich.edu 4945253Sksewell@umich.edu #TestCPUClass.CoreParams.tlb = TLB() 4955253Sksewell@umich.edu #TestCPUClass.CoreParams.UnifiedTLB = 1 496