FSConfig.py revision 3745
12934Sktlim@umich.edu# Copyright (c) 2006 The Regents of The University of Michigan
22934Sktlim@umich.edu# All rights reserved.
32934Sktlim@umich.edu#
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132934Sktlim@umich.edu# this software without specific prior written permission.
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272934Sktlim@umich.edu# Authors: Kevin Lim
282934Sktlim@umich.edu
292934Sktlim@umich.eduimport m5
302969Sktlim@umich.edufrom m5 import makeList
312934Sktlim@umich.edufrom m5.objects import *
322995Ssaidi@eecs.umich.edufrom Benchmarks import *
332934Sktlim@umich.edu
342934Sktlim@umich.educlass CowIdeDisk(IdeDisk):
352934Sktlim@umich.edu    image = CowDiskImage(child=RawDiskImage(read_only=True),
362934Sktlim@umich.edu                         read_only=False)
372934Sktlim@umich.edu
382934Sktlim@umich.edu    def childImage(self, ci):
392934Sktlim@umich.edu        self.image.child.image_file = ci
402934Sktlim@umich.edu
412934Sktlim@umich.educlass BaseTsunami(Tsunami):
422934Sktlim@umich.edu    ethernet = NSGigE(configdata=NSGigEPciData(),
432934Sktlim@umich.edu                      pci_bus=0, pci_dev=1, pci_func=0)
442934Sktlim@umich.edu    etherint = NSGigEInt(device=Parent.ethernet)
452934Sktlim@umich.edu    ide = IdeController(disks=[Parent.disk0, Parent.disk2],
462934Sktlim@umich.edu                        pci_func=0, pci_dev=0, pci_bus=0)
472934Sktlim@umich.edu
483005Sstever@eecs.umich.edudef makeLinuxAlphaSystem(mem_mode, mdesc = None):
492934Sktlim@umich.edu    self = LinuxAlphaSystem()
503005Sstever@eecs.umich.edu    if not mdesc:
513005Sstever@eecs.umich.edu        # generic system
523304Sstever@eecs.umich.edu        mdesc = SysConfig()
532995Ssaidi@eecs.umich.edu    self.readfile = mdesc.script()
542934Sktlim@umich.edu    self.iobus = Bus(bus_id=0)
552934Sktlim@umich.edu    self.membus = Bus(bus_id=1)
562934Sktlim@umich.edu    self.bridge = Bridge()
572995Ssaidi@eecs.umich.edu    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
582934Sktlim@umich.edu    self.bridge.side_a = self.iobus.port
592934Sktlim@umich.edu    self.bridge.side_b = self.membus.port
602934Sktlim@umich.edu    self.physmem.port = self.membus.port
612934Sktlim@umich.edu    self.disk0 = CowIdeDisk(driveID='master')
622934Sktlim@umich.edu    self.disk2 = CowIdeDisk(driveID='master')
632995Ssaidi@eecs.umich.edu    self.disk0.childImage(mdesc.disk())
642934Sktlim@umich.edu    self.disk2.childImage(disk('linux-bigswap2.img'))
652934Sktlim@umich.edu    self.tsunami = BaseTsunami()
662934Sktlim@umich.edu    self.tsunami.attachIO(self.iobus)
672934Sktlim@umich.edu    self.tsunami.ide.pio = self.iobus.port
682934Sktlim@umich.edu    self.tsunami.ethernet.pio = self.iobus.port
692995Ssaidi@eecs.umich.edu    self.simple_disk = SimpleDisk(disk=RawDiskImage(image_file = mdesc.disk(),
702934Sktlim@umich.edu                                               read_only = True))
712934Sktlim@umich.edu    self.intrctrl = IntrControl()
722953Sktlim@umich.edu    self.mem_mode = mem_mode
732934Sktlim@umich.edu    self.sim_console = SimConsole(listener=ConsoleListener(port=3456))
742934Sktlim@umich.edu    self.kernel = binary('vmlinux')
753449Shsul@eecs.umich.edu    self.pal = binary('ts_osfpal')
762934Sktlim@umich.edu    self.console = binary('console')
772934Sktlim@umich.edu    self.boot_osflags = 'root=/dev/hda1 console=ttyS0'
782934Sktlim@umich.edu
792934Sktlim@umich.edu    return self
802934Sktlim@umich.edu
813584Ssaidi@eecs.umich.edudef makeSparcSystem(mem_mode, mdesc = None):
823584Ssaidi@eecs.umich.edu    self = SparcSystem()
833584Ssaidi@eecs.umich.edu    if not mdesc:
843584Ssaidi@eecs.umich.edu        # generic system
853584Ssaidi@eecs.umich.edu        mdesc = SysConfig()
863584Ssaidi@eecs.umich.edu    self.readfile = mdesc.script()
873743Sgblack@eecs.umich.edu    self.iobus = Bus(bus_id=0)
883584Ssaidi@eecs.umich.edu    self.membus = Bus(bus_id=1)
893743Sgblack@eecs.umich.edu    self.bridge = Bridge()
903743Sgblack@eecs.umich.edu    self.t1000 = T1000()
913743Sgblack@eecs.umich.edu    self.t1000.attachIO(self.iobus)
923584Ssaidi@eecs.umich.edu    self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()))
933743Sgblack@eecs.umich.edu    self.bridge.side_a = self.iobus.port
943743Sgblack@eecs.umich.edu    self.bridge.side_b = self.membus.port
953584Ssaidi@eecs.umich.edu    self.physmem.port = self.membus.port
963584Ssaidi@eecs.umich.edu    self.rom.port = self.membus.port
973745Sgblack@eecs.umich.edu    self.nvram.port = self.membus.port
983745Sgblack@eecs.umich.edu    self.hypervisor_desc.port = self.membus.port
993745Sgblack@eecs.umich.edu    self.partition_desc.port = self.membus.port
1003584Ssaidi@eecs.umich.edu    self.intrctrl = IntrControl()
1013584Ssaidi@eecs.umich.edu    self.mem_mode = mem_mode
1023584Ssaidi@eecs.umich.edu    self.kernel = binary('vmlinux')
1033584Ssaidi@eecs.umich.edu
1043584Ssaidi@eecs.umich.edu    self.reset_bin = binary('reset.bin')
1053584Ssaidi@eecs.umich.edu    self.hypervisor_bin = binary('q.bin')
1063584Ssaidi@eecs.umich.edu    self.openboot_bin = binary('openboot.bin')
1073745Sgblack@eecs.umich.edu    self.nvram_bin = binary('nvram1')
1083745Sgblack@eecs.umich.edu    self.hypervisor_desc_bin = binary('1up-hv.bin')
1093745Sgblack@eecs.umich.edu    self.partition_desc_bin = binary('1up-md.bin')
1103584Ssaidi@eecs.umich.edu
1113584Ssaidi@eecs.umich.edu    return self
1123584Ssaidi@eecs.umich.edu
1133584Ssaidi@eecs.umich.edu
1143025Ssaidi@eecs.umich.edudef makeDualRoot(testSystem, driveSystem, dumpfile):
1152934Sktlim@umich.edu    self = Root()
1162995Ssaidi@eecs.umich.edu    self.testsys = testSystem
1172995Ssaidi@eecs.umich.edu    self.drivesys = driveSystem
1183025Ssaidi@eecs.umich.edu    self.etherlink = EtherLink(int1 = Parent.testsys.tsunami.etherint[0],
1193025Ssaidi@eecs.umich.edu                               int2 = Parent.drivesys.tsunami.etherint[0])
1203025Ssaidi@eecs.umich.edu    if dumpfile:
1213025Ssaidi@eecs.umich.edu        self.etherdump = EtherDump(file=dumpfile)
1223025Ssaidi@eecs.umich.edu        self.etherlink.dump = Parent.etherdump
1232934Sktlim@umich.edu
1242934Sktlim@umich.edu    self.clock = '1THz'
1252934Sktlim@umich.edu    return self
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